Add device tree support for sc7180
Subsystems (6)
v3 cover Add device tree support for sc7180
Changes in v3:
* PATCH 2/11: Updated the qup and uart lables to be consistent with the naming convention followed in sdm845 as suggested by Matthias
* Dropped 2 patches from v2 which added the new compatible and binding updates for sc7180 pdc and reused sdm845 compatible instead as suggested by Marc Z
This series adds DT support for basic peripherals on qualcomm's sc7180 SoC, drivers for which are already upstream.
The series has a dependency on gcc clock driver patches [1] to merge first
[1] https://www.spinics.net/lists/linux-clk/msg41851.html
Kiran Gunda (3):
arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
arm64: dts: qcom: sc7180-idp: Add RPMh regulators
Maulik Shah (3):
arm64: dts: qcom: sc7180: Add cmd_db reserved area
arm64: dts: qcom: sc7180: Add rpmh-rsc node
arm64: dts: qcom: sc7180: Add pdc interrupt controller
Rajendra Nayak (3):
dt-bindings: qcom: Add SC7180 bindings
arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
Taniya Das (1):
arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
Vivek Gautam (1):
arm64: dts: sc7180: Add device node for apps_smmu
.../devicetree/bindings/arm/qcom.yaml | 2 + .../devicetree/bindings/iommu/arm,smmu.txt | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/pm6150.dtsi | 85 ++++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 47 ++ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 256 ++++++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 459 ++++++++++++++++++ 7 files changed, 851 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
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PATCH v3 1/11 dt-bindings: qcom: Add SC7180 bindings
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
--- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/arm/qcom.yaml +2 -0
@@ -36,6 +36,7 @@ description: | mdm9615 ipq8074 sdm845 + sc7180 The 'board' element must be one of the following strings:
@@ -46,6 +47,7 @@ description: | sbc hk01 qrd + idp The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the same
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Rob Herring
maintainerRe: [PATCH v3 01/11] dt-bindings: qcom: Add SC7180 bindings
Quoted 14 lines · Rajendra Nayak
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Vinod Koul <[email protected]>--- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/arm/qcom.yaml +0
-0
Documentation/devicetree/bindings/arm/qcom.yaml description: | · line 39
Quoted 4 lines
Documentation/devicetree/bindings/arm/qcom.yaml +1
-0@@ -36,6 +36,7 @@ description: | mdm9615 ipq8074 sdm845 + sc7180
Where's the schema?
Quoted 15 lines
Documentation/devicetree/bindings/arm/qcom.yaml +1
-0The 'board' element must be one of the following strings:@@ -46,6 +47,7 @@ description: | sbc hk01 qrd + idp The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the sameSignature · 2 lines
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Re: [PATCH v3 01/11] dt-bindings: qcom: Add SC7180 bindings
Quoted 10 lines · Rob Herring
Quoted 9 lines · Rajendra Nayak
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Vinod Koul <[email protected]>--- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+)
Quoted 11 lines
Documentation/devicetree/bindings/arm/qcom.yaml description: | · line 39
Quoted 9 lines
Documentation/devicetree/bindings/arm/qcom.yaml +1
-0@@ -36,6 +36,7 @@ description: | mdm9615 ipq8074 sdm845 + sc7180Where's the schema?
sorry, missed it, will add when I repost.
Quoted 16 lines
Quoted 16 lines
Documentation/devicetree/bindings/arm/qcom.yaml +1
-0The 'board' element must be one of the following strings:@@ -46,6 +47,7 @@ description: | sbc hk01 qrd + idp The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the sameSignature · 2 lines
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Signature · 2 lines
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PATCH v3 2/11 arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
In reply to Rajendra NayakAdd skeletal sc7180 SoC dtsi and idp board dts files
---
v3:
Updated the qup and uart lables to be consistent
with the naming convention followed in sdm845
as suggested by Matthias
The patch has a dependency on gcc clock driver patches [1] to merge first
[1] https://www.spinics.net/lists/linux-clk/msg41851.html
arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7180-idp.dts | 47 ++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 300 ++++++++++++++++++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
arch/arm64/boot/dts/qcom/Makefile +1 -0
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
arch/arm64/boot/dts/qcom/sc7180-idp.dts new file +47 -0
47 lines not on this page · raw message
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +300 -0
300 lines not on this page · raw message
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Re: [PATCH v3 02/11] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
Quoting Rajendra Nayak (2019-10-23 02:02:10)
Quoted 19 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +13
-0@@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SC7180 SoC device tree source + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/clock/qcom,gcc-sc7180.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; +
arch/arm64/boot/dts/qcom/sc7180.dtsi line 23
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +10
-0+ #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board";
Can you drop the output names property? I think we don't care that the name is "xo-board" instead of "xo_board" now.
Quoted 11 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +11
-0+ #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; +
[...]
arch/arm64/boot/dts/qcom/sc7180.dtsi line 159
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +6
-0+ + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>;
Why the extra space here ^ ?
Quoted 21 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +21
-0+ compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0 0x00100000 0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; +
arch/arm64/boot/dts/qcom/sc7180.dtsi line 190
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +10
-0+ uart10: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart10_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };
Can we not add all the i2c/spi/uart cores here?
Quoted 1 line
+ };
Re: [PATCH v3 02/11] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
Quoted 25 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:10)
Quoted 24 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +18
-0@@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SC7180 SoC device tree source + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/clock/qcom,gcc-sc7180.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; +
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 23
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +5
-0+ clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board";Can you drop the output names property? I think we don't care that the name is "xo-board" instead of "
xo_board" now.
sure, will do.
Quoted 13 lines
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +11
-0+ #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; +[...]
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 159
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +6
-0+ + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>;Why the extra space here ^ ?
typo, will fix.
Quoted 26 lines
Quoted 26 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +25
-0+ compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0 0x00100000 0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart10: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se";
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 190
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +6
-0+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart10_default>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };Can we not add all the i2c/spi/uart cores here?
I see that these nodes are posted now [1].
Will pull it in as part of this series so it can be reviewed together.
[1] https://lkml.org/lkml/2019/10/31/63
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kbuild test robot
build botRe: [PATCH v3 02/11] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
In reply to Rajendra NayakI love your patch! Yet something to improve:
Hi Rajendra,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.4-rc5 next-20191029]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Rajendra-Nayak/Add-device-tree-support-for-sc7180/20191025-060212 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: arm64-defconfig (attached as .config) compiler: aarch64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag
All errors (new ones prefixed by >>):
In file included from arch/arm64/boot/dts/qcom/sc7180-idp.dts:10:
>> arch/arm64/boot/dts/qcom/sc7180.dtsi:8:10: fatal error: dt-bindings/clock/qcom,gcc-sc7180.h: No such file or directory
8 | #include <dt-bindings/clock/qcom,gcc-sc7180.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~compilation terminated.
vim +8 arch/arm64/boot/dts/qcom/sc7180.dtsi
> 8 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
PATCH v3 3/11 dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
In reply to Rajendra NayakAdd the soc specific compatible for sc7180 smmu-500
--- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/iommu/arm,smmu.txt +1 -0
@@ -30,6 +30,7 @@ conditions. Qcom SoCs implementing "arm,mmu-500" must also include, as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" + "qcom,sc7180-smmu-500", "arm,mmu-500" - reg : Base address and size of the SMMU.
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Rob Herring
maintainerRe: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
Quoted 14 lines · Rajendra Nayak
Add the soc specific compatible for sc7180 smmu-500
Signed-off-by Rajendra Nayak <[email protected]>Cc Joerg Roedel <[email protected]>Cc Mark Rutland <[email protected]>--- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/iommu/arm,smmu.txt +0
-0
Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 33
Quoted 4 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt +1
-0@@ -30,6 +30,7 @@ conditions. Qcom SoCs implementing "arm,mmu-500" must also include, as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" + "qcom,sc7180-smmu-500", "arm,mmu-500"
This is now a schema file in my tree.
Quoted 7 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt +0
-1- reg : Base address and size of the SMMU. --QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
Quoted 10 lines · Rob Herring
Quoted 9 lines · Rajendra Nayak
Add the soc specific compatible for sc7180 smmu-500
Signed-off-by Rajendra Nayak <[email protected]>Cc Joerg Roedel <[email protected]>Cc Mark Rutland <[email protected]>--- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + 1 file changed, 1 insertion(+)
Quoted 11 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 33
Quoted 9 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt +1
-0@@ -30,6 +30,7 @@ conditions. Qcom SoCs implementing "arm,mmu-500" must also include, as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" + "qcom,sc7180-smmu-500", "arm,mmu-500"This is now a schema file in my tree.
sure, will rebase on your for-next when I repost.
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt +0
-1- reg : Base address and size of the SMMU. --QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signature · 2 lines
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Re: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
In reply to Rajendra NayakQuoting Rajendra Nayak (2019-10-23 02:02:11)
Quoted 14 lines
Add the soc specific compatible for sc7180 smmu-500
Signed-off-by Rajendra Nayak <[email protected]>Cc Joerg Roedel <[email protected]>Cc Mark Rutland <[email protected]>--- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/iommu/arm,smmu.txt +0
-0
Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 33
Quoted 4 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt +1
-0@@ -30,6 +30,7 @@ conditions. Qcom SoCs implementing "arm,mmu-500" must also include, as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" + "qcom,sc7180-smmu-500", "arm,mmu-500"
Please sort.
Re: [PATCH v3 03/11] dt-bindings: arm-smmu: update binding for qcom sc7180 SoC
Quoted 10 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:11)
Quoted 9 lines
Add the soc specific compatible for sc7180 smmu-500
Signed-off-by Rajendra Nayak <[email protected]>Cc Joerg Roedel <[email protected]>Cc Mark Rutland <[email protected]>--- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + 1 file changed, 1 insertion(+)
Quoted 11 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 33
Quoted 9 lines
Documentation/devicetree/bindings/iommu/arm,smmu.txt +1
-0@@ -30,6 +30,7 @@ conditions. Qcom SoCs implementing "arm,mmu-500" must also include, as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" + "qcom,sc7180-smmu-500", "arm,mmu-500"Please sort.
thanks, will do.
Quoted 1 line
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PATCH v3 4/11 arm64: dts: sc7180: Add device node for apps_smmu
In reply to Rajendra NayakFrom: Vivek Gautam <[email protected]>
Adding device node for APPS SMMU that is connected to devices such as display, video, usb, mmc, etc. on SC7180 chipset.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 88 ++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +88 -0
@@ -211,6 +211,94 @@ }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #address-cells = <2>;
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PATCH v3 5/11 arm64: dts: qcom: sc7180: Add cmd_db reserved area
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Command_db provides mapping for resource key and address managed by remote processor. Add cmd_db reserved memory area.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +12 -0
@@ -32,6 +32,18 @@ }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cmd_db: reserved-memory@80820000 { + reg = <0x0 0x80820000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>;
Signature · 2 lines
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Re: [PATCH v3 05/11] arm64: dts: qcom: sc7180: Add cmd_db reserved area
Quoted 17 lines · Rajendra Nayak
From: Maulik Shah <[email protected]>
Command_dbprovides mapping for resource key and address managed by remote processor. Addcmd_dbreserved memory area.Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0
arch/arm64/boot/dts/qcom/sc7180.dtsi line 40
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +6
-0@@ -32,6 +32,18 @@ }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cmd_db: reserved-memory@80820000 {
aop_cmd_db_mem: memory@80820000 {
please use ^^ instead
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +6
-0+ reg = <0x0 0x80820000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>;
Signature · 3 lines
-- Sibi Sankar -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Re: [PATCH v3 05/11] arm64: dts: qcom: sc7180: Add cmd_db reserved area
Quoted 21 lines · Sibi Sankar
Quoted 20 lines · Rajendra Nayak
From: Maulik Shah <[email protected]>
Command_dbprovides mapping for resource key and address managed by remote processor. Addcmd_dbreserved memory area.Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++1 file changed, 12 insertions(+)arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0@@ -32,6 +32,18 @@ }; };
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 40
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +6
-0+ reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cmd_db: reserved-memory@80820000 {
aop_cmd_db_mem: memory@80820000 {
please use ^^ instead
right, I thought I looked up sm8150.dtsi to make sure the labeling for various things is consistent, but maybe i didn't. Will fix. Thanks.
Quoted 11 lines
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +6
-0+ reg = <0x0 0x80820000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>;
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PATCH v3 6/11 arm64: dts: qcom: sc7180: Add rpmh-rsc node
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Add device bindings for the application processor's rsc. The rsc contains the TCS that are used for communicating with the hardened resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +19 -0
@@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7180.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> / { interrupt-parent = <&intc>;
@@ -388,6 +389,24 @@ status = "disabled"; }; }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0 0x18200000 0 0x10000>, + <0 0x18210000 0 0x10000>, + <0 0x18220000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 1>; + }; }; timer {
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PATCH v3 7/11 arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +19 -0
@@ -224,6 +224,25 @@ }; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0xc440000 0 0x1100>, + <0 0xc600000 0 0x2000000>, + <0 0xe600000 0 0x100000>, + <0 0xe700000 0 0xa0000>, + <0 0xc40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>;
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Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
Quoting Rajendra Nayak (2019-10-23 02:02:15)
arch/arm64/boot/dts/qcom/sc7180.dtsi line 229
Quoted 11 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +3
-0@@ -224,6 +224,25 @@ }; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0xc440000 0 0x1100>,
Please pad out the registers to 8 numbers. See sdm845.
arch/arm64/boot/dts/qcom/sc7180.dtsi line 236
Quoted 7 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +7
-0+ <0 0xc600000 0 0x2000000>, + <0 0xe600000 0 0x100000>, + <0 0xe700000 0 0xa0000>, + <0 0xc40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
This is different than sdm845. I guess pdc is working?
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +9
-0+ qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; +
Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
Quoted 9 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:15)
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0@@ -224,6 +224,25 @@ }; };
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 229
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +3
-0+ spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0xc440000 0 0x1100>,Please pad out the registers to 8 numbers. See sdm845.
Ok.. Will address it in the next series.
Quoted 11 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +7
-0+ <0 0xc600000 0 0x2000000>, + <0 0xe600000 0 0x100000>, + <0 0xe700000 0 0xa0000>, + <0 0xc40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
Quoted 2 lines
This is different than sdm845. I guess pdc is working?
Yes. For SDM845 pdc controller support was not yet added. That's why still the GIC interrupt is used. Where as for SC7180 the same is added with https://lore.kernel.org/patchwork/patch/1143335/.
Yes. pdc is working.
Quoted 9 lines
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +9
-0+ qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; +
Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
Quoting [email protected] (2019-10-29 23:06:43)
Quoted 28 lines · Stephen Boyd
Quoted 10 lines
Quoting Rajendra Nayak (2019-10-23 02:02:15)
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0@@ -224,6 +224,25 @@ }; };Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 229
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +3
-0+ spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0xc440000 0 0x1100>,Please pad out the registers to 8 numbers. See sdm845.
Ok.. Will address it in the next series.
Quoted 11 lines
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +7
-0+ <0 0xc600000 0 0x2000000>, + <0 0xe600000 0 0x100000>, + <0 0xe700000 0 0xa0000>, + <0 0xc40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
Quoted 8 lines
Quoted 2 lines
This is different than sdm845. I guess pdc is working?
Yes. For SDM845 pdc controller support was not yet added. That's why still the GIC interrupt is used.
Where as for SC7180 the same is added with
https://lore.kernel.org/patchwork/patch/1143335/.Yes. pdc is working.
Cool. The patch that adds pdc to the DT should come before this one then. In reality, it would be better if it was all squashed down into one big commit that just introduces the SoC file and one commit for PMICs and then one commit for the idp board. Then we don't have this ordering problem.
Re: [PATCH v3 07/11] arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
Quoted 36 lines · Stephen Boyd
Quoting [email protected] (2019-10-29 23:06:43)
Quoted 35 lines · Stephen Boyd
Quoted 10 lines
Quoting Rajendra Nayak (2019-10-23 02:02:15)
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0@@ -224,6 +224,25 @@ }; };Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 229
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +3
-0+ spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0xc440000 0 0x1100>,Please pad out the registers to 8 numbers. See sdm845.
Ok.. Will address it in the next series.
Quoted 11 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +7
-0+ <0 0xc600000 0 0x2000000>, + <0 0xe600000 0 0x100000>, + <0 0xe700000 0 0xa0000>, + <0 0xc40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;Quoted 2 lines
This is different than sdm845. I guess pdc is working?
Yes. For SDM845 pdc controller support was not yet added. That's why still the GIC interrupt is used.
Where as for SC7180 the same is added with
https://lore.kernel.org/patchwork/patch/1143335/.
Quoted 7 lines
Quoted 1 line
Yes. pdc is working.
Cool. The patch that adds pdc to the DT should come before this one then. In reality, it would be better if it was all squashed down into one big commit that just introduces the SoC file and one commit for PMICs and then one commit for the idp board. Then we don't have this ordering problem.
I'll fix the ordering issues when I respin.
I could squash all of the patches touching the SoC dtsi, but given the authorship for each varies, I will keep it as is perhaps.
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PATCH v3 8/11 arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other PMIC infra modules.
--- arch/arm64/boot/dts/qcom/pm6150.dtsi | 85 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 47 ++++++++++++++ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 2 + 3 files changed, 134 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +85 -0
@@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/thermal/thermal.h> + +&spmi_bus { + pm6150_lsid0: pmic@0 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + }; + + pm6150_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm6150_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6150_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@ADC5_DIE_TEMP { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + }; + }; + + pm6150_gpio: gpios@c000 { + compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>; + + interrupt-names = "pm6150_gpio1", "pm6150_gpio2", + "pm6150_gpio3", "pm6150_gpio4", + "pm6150_gpio5", "pm6150_gpio6", + "pm6150_gpio7", "pm6150_gpio8", + "pm6150_gpio9", "pm6150_gpio10"; + }; + }; + + pm6150_lsid1: pmic@1 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
arch/arm64/boot/dts/qcom/pm6150l.dtsi new file +47 -0
47 lines not on this page · raw message
arch/arm64/boot/dts/qcom/sc7180-idp.dts +2 -0
@@ -8,6 +8,8 @@ /dts-v1/; #include "sc7180.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" / { model = "Qualcomm Technologies, Inc. SC7180 IDP";
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Re: [PATCH v3 08/11] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
Quoting Rajendra Nayak (2019-10-23 02:02:16)
Quoted 17 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +11
-0@@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/thermal/thermal.h> + +&spmi_bus { + pm6150_lsid0: pmic@0 {
arch/arm64/boot/dts/qcom/pm6150.dtsi line 21
Quoted 10 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +10
-0+ compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>;
Can this have status = "disabled"? Or is the idea that if the pmic power button isn't used it should be disabled in the board dts file?
Quoted 26 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +26
-0+ + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + }; + + pm6150_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm6150_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6150_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>;
arch/arm64/boot/dts/qcom/pm6150.dtsi line 57
Quoted 10 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +10
-0+ + adc-chan@ADC5_DIE_TEMP { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + }; + }; + + pm6150_gpio: gpios@c000 { + compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; + reg = <0xc000 0xa00>;
Drop the size?
arch/arm64/boot/dts/qcom/pm6150.dtsi line 69
Quoted 12 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +12
-0+ gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>;
Isn't this supposed to go away?
arch/arm64/boot/dts/qcom/pm6150.dtsi line 75
Quoted 6 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +6
-0+ + interrupt-names = "pm6150_gpio1", "pm6150_gpio2", + "pm6150_gpio3", "pm6150_gpio4", + "pm6150_gpio5", "pm6150_gpio6", + "pm6150_gpio7", "pm6150_gpio8", + "pm6150_gpio9", "pm6150_gpio10";
And this? And have gpio-ranges and use the irqdomain work. Basically, should look like pm8998.
Quoted 10 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +10
-0+ }; + }; + + pm6150_lsid1: pmic@1 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
Re: [PATCH v3 08/11] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
Quoted 23 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:16)
Quoted 22 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +16
-0@@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/thermal/thermal.h> + +&spmi_bus { + pm6150_lsid0: pmic@0 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; +
Quoted 9 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi line 21
Quoted 5 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +5
-0+ pm6150_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>;Can this have status = "disabled"? Or is the idea that if the pmic power button isn't used it should be disabled in the board dts file?
Yes. The idea is to go with latter option. Disable it in the board dts file if the pmic power button is not used.
Quoted 34 lines
Quoted 34 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +4
-0+ + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0
IRQ_TYPE_EDGE_BOTH>;arch/arm64/boot/dts/qcom/pm6150.dtsi new file +10
-0+ debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + }; + + pm6150_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0
IRQ_TYPE_EDGE_RISING>;arch/arm64/boot/dts/qcom/pm6150.dtsi new file +9
-0+ io-channels = <&pm6150_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6150_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0
IRQ_TYPE_EDGE_RISING>;arch/arm64/boot/dts/qcom/pm6150.dtsi new file +8
-0+ #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@ADC5_DIE_TEMP { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + };
Quoted 9 lines
Quoted 6 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +4
-0+ }; + + pm6150_gpio: gpios@c000 { + compatible = "qcom,pm6150-gpio","qcom,spmi-gpio";
+ reg = <0xc0000xa00>;Drop the size?
Will drop it in next series.
Quoted 13 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi line 69
Quoted 12 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +12
-0+ gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>;
Quoted 2 lines
Isn't this supposed to go away?
Yes. We can remove them if we want to go with the way done for pm8998.
Quoted 12 lines
Quoted 11 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +2
-0+ + interrupt-names = "pm6150_gpio1","
pm6150_gpio2",
+ "pm6150_gpio3",
"pm6150_gpio4",
+ "pm6150_gpio5",
"pm6150_gpio6",
+ "pm6150_gpio7",
"pm6150_gpio8",
+ "pm6150_gpio9",
"pm6150_gpio10";
Quoted 2 lines
And this? And have gpio-ranges and use the irqdomain work. Basically, should look like pm8998.
Ok.. We can go ahead with the pm8998 way as well. We will address it in next series.
Quoted 11 lines
Quoted 11 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +10
-0+ }; + }; + + pm6150_lsid1: pmic@1 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
Re: [PATCH v3 08/11] arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
Quoting [email protected] (2019-10-30 00:06:05)
Quoted 35 lines · Stephen Boyd
Quoted 25 lines
Quoting Rajendra Nayak (2019-10-23 02:02:16)
Quoted 24 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +17
-0@@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/thermal/thermal.h> + +&spmi_bus { + pm6150_lsid0: pmic@0 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150_pon: pon@800 {Quoted 9 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi line 21
Quoted 4 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +4
-0+ compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>;Can this have status = "disabled"? Or is the idea that if the pmic power
button isn't used it should be disabled in the board dts file?
Quoted 3 lines
Yes. The idea is to go with latter option. Disable it in the board dts file if the
pmic power button is not used.
Ok. Thanks.
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +2
-0+ + interrupt-names = "pm6150_gpio1","
pm6150_gpio2",
+ "pm6150_gpio3",
"pm6150_gpio4",
+ "pm6150_gpio5",
"pm6150_gpio6",
+ "pm6150_gpio7",
"pm6150_gpio8",
+ "pm6150_gpio9",
"pm6150_gpio10";
Quoted 4 lines
Quoted 2 lines
And this? And have gpio-ranges and use the irqdomain work. Basically, should look like pm8998.
Ok.. We can go ahead with the pm8998 way as well. We will address it in next series.
Yes please use the pm8998 way..
PATCH v3 9/11 arm64: dts: qcom: sc7180-idp: Add RPMh regulators
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add the rpmh regulators for the sc7180 idp platform. This platform consists of PMIC PM6150 and PM6150l
--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 207 ++++++++++++++++++++++++ 1 file changed, 207 insertions(+)
arch/arm64/boot/dts/qcom/sc7180-idp.dts +207 -0
@@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc7180.dtsi" #include "pm6150.dtsi" #include "pm6150l.dtsi"
@@ -24,6 +25,212 @@ }; }; +&apps_rsc { + pm6150-rpmh-regulators { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s1a_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s4a_1p0: smps4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_l1a_1p2: ldo1 { + regulator-min-microvolt = <1178000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l4a_0p8: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_2p7: ldo5 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p6: ldo6 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <648000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p6: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l19a_2p9: ldo19 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; + + pm6150l-rpmh-regulators { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + }; +}; + &qupv3_id_1 { status = "okay"; };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v3 10/11 arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
In reply to Rajendra NayakFrom: Taniya Das <[email protected]>
Add node for rpmhcc clock driver.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +11 -0
@@ -6,6 +6,7 @@ */ #include <dt-bindings/clock/qcom,gcc-sc7180.h> +#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -175,6 +176,9 @@ gcc: clock-controller@100000 { compatible = "qcom,gcc-sc7180"; reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
@@ -425,6 +429,13 @@ <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 1>; + + rpmhcc: clock-controller { + compatible = "qcom,sc7180-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; }; };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v3 11/11 arm64: dts: qcom: sc7180: Add pdc interrupt controller
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
---
v3:
Used the qcom,sdm845-pdc compatible for pdc node
arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +10 -0
@@ -184,6 +184,16 @@ #power-domain-cells = <1>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0 0xb220000 0 0x30000>; + qcom,pdc-ranges = <0 480 15>, <17 497 98>, + <119 634 4>, <124 639 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Hi Rajendra/Maulik,
Quoted 18 lines · Rajendra Nayak
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc nodearch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0
arch/arm64/boot/dts/qcom/sc7180.dtsi line 187
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +1
-0@@ -184,6 +184,16 @@ #power-domain-cells = <1>; }; + pdc: interrupt-controller@b220000 {
Aren't the nodes supposed to be ordered by address as for SDM845? If so this node should be added after 'qupv3_id_1: geniqup@ac0000', not before.
Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoted 24 lines · Matthias Kaehlcke
Hi Rajendra/Maulik,
Quoted 21 lines · Rajendra Nayak
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc nodearch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0@@ -184,6 +184,16 @@ #power-domain-cells = <1>; };
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 187
Quoted 1 line
arch/arm64/boot/dts/qcom/sc7180.dtsi +1
-0+ pdc: interrupt-controller@b220000 {Aren't the nodes supposed to be ordered by address as for SDM845? If so this node should be added after '
qupv3_id_1: geniqup@ac0000', not before.
yes, indeed. my sorting seems to have gone wrong. Will fix and repost. thanks
Quoted 1 line
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
In reply to Rajendra NayakQuoting Rajendra Nayak (2019-10-23 02:02:19)
Quoted 9 lines
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc node
Everything else isn't doing the weird old compatible thing. Why not just add the new compatible and update the driver? I guess I'll have to go read the history.
Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoted 11 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:19)
Quoted 9 lines
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc node
Quoted 3 lines
Everything else isn't doing the weird old compatible thing. Why not just add the new compatible and update the driver? I guess I'll have to go read the history.
Marc Zyngier complained on v2 about the churn from adding compatible strings for identical components, and I kinda see his point.
I agree that using the 'sdm845' compatible string for sc7180 is odd too. Maybe we should introduce SoC independent compatible strings for IP blocks that are shared across multiple SoCs? If differentiation is needed SoC specific strings can be added.
Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoted 16 lines · Matthias Kaehlcke
Quoted 11 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:19)
Quoted 9 lines
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc nodeQuoted 3 lines
Everything else isn't doing the weird old compatible thing. Why not just add the new compatible and update the driver? I guess I'll have to go read the history.
Quoted 7 lines
Marc Zyngier complained on v2 about the churn from adding compatible strings for identical components, and I kinda see his point.
I agree that using the 'sdm845' compatible string for sc7180 is odd too. Maybe we should introduce SoC independent compatible strings for IP blocks that are shared across multiple SoCs? If differentiation is needed SoC specific strings can be added.
Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid confusion.
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Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoted 22 lines · Rajendra Nayak
Quoted 19 lines · Matthias Kaehlcke
Quoted 11 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:19)
Quoted 9 lines
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc nodeQuoted 3 lines
Everything else isn't doing the weird old compatible thing. Why not just add the new compatible and update the driver? I guess I'll have to go read the history.
Marc Zyngier complained on v2 about the churn from adding compatible strings for identical components, and I kinda see his point.
Quoted 8 lines
Quoted 4 lines
I agree that using the 'sdm845' compatible string for sc7180 is odd too. Maybe we should introduce SoC independent compatible strings for IP blocks that are shared across multiple SoCs? If differentiation is needed SoC specific strings can be added.
Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid confusion.
I agree,
compatible = "qcom,sc7180-pdc", "qcom,pdc";
is the way to go.
Reusing qcom,sdm845-pdc would prevent us from tackling any unforeseen issues/variations/erratas with one or the other platform in the future.
Regards,
Bjorn
Quoted 4 lines
Signature · 3 lines
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Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoted 33 lines · Bjorn Andersson
Quoted 22 lines · Rajendra Nayak
Quoted 19 lines · Matthias Kaehlcke
Quoted 11 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:19)
Quoted 9 lines
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc nodeQuoted 3 lines
Everything else isn't doing the weird old compatible thing. Why not just add the new compatible and update the driver? I guess I'll have to go read the history.
Marc Zyngier complained on v2 about the churn from adding compatible strings for identical components, and I kinda see his point.
Quoted 8 lines
Quoted 4 lines
I agree that using the 'sdm845' compatible string for sc7180 is odd too. Maybe we should introduce SoC independent compatible strings for IP blocks that are shared across multiple SoCs? If differentiation is needed SoC specific strings can be added.
Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid confusion.
Quoted 5 lines
I agree,
compatible = "qcom,sc7180-pdc", "qcom,pdc";
is the way to go.
I wasn't planning on adding a qcom,sc7180-pdc, but instead just use the qcom,pdc one for sc7180.
Quoted 3 lines
Reusing qcom,sdm845-pdc would prevent us from tackling any unforeseen issues/variations/erratas with one or the other platform in the future.
That was the intention of adding qcom,sc7180-pdc in the first place, but Marc Zyngier was not happy with the churn, given there aren't really any variations or erratas that we know of.
Quoted 8 lines
Regards,
BjornQuoted 4 lines
Signature · 3 lines
-- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoted 46 lines · Rajendra Nayak
Quoted 33 lines · Bjorn Andersson
Quoted 22 lines · Rajendra Nayak
Quoted 19 lines · Matthias Kaehlcke
Quoted 11 lines · Stephen Boyd
Quoting Rajendra Nayak (2019-10-23 02:02:19)
Quoted 9 lines
From: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
Signed-off-by Maulik Shah <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
v3:
Used the qcom,sdm845-pdc compatible for pdc nodeQuoted 3 lines
Everything else isn't doing the weird old compatible thing. Why not just add the new compatible and update the driver? I guess I'll have to go read the history.
Marc Zyngier complained on v2 about the churn from adding compatible strings for identical components, and I kinda see his point.
Quoted 8 lines
Quoted 4 lines
I agree that using the 'sdm845' compatible string for sc7180 is odd too. Maybe we should introduce SoC independent compatible strings for IP blocks that are shared across multiple SoCs? If differentiation is needed SoC specific strings can be added.
Sure, I will perhaps add a qcom,pdc SoC independent compatible to avoid confusion.
Quoted 5 lines
I agree,
compatible = "qcom,sc7180-pdc", "qcom,pdc";
is the way to go.
I wasn't planning on adding a qcom,sc7180-pdc, but instead just use the qcom,pdc one for sc7180.
Quoted 1 line
Quoted 7 lines
Quoted 2 lines
Reusing qcom,sdm845-pdc would prevent us from tackling any unforeseen issues/variations/erratas with one or the other platform in the future.
That was the intention of adding qcom,sc7180-pdc in the first place, but Marc Zyngier was not happy with the churn, given there aren't really any variations or erratas that we know of.
Right, but by putting both compatibles in the dts and the generic one in the driver we avoid the driver churn and we're future compatible.
And given that we haven't yet added the qcom,sdm845-pdc node to the sdm845.dtsi we don't need to maintain the qcom,sdm845-pdc in the driver. So switch qcom,sdm845-pdc to qcom,pdc in qcom-pdc.c.
Regards,
Bjorn
Quoted 12 lines
Quoted 8 lines
Regards,
BjornQuoted 4 lines
Signature · 3 lines
-- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux FoundationSignature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v3 11/11] arm64: dts: qcom: sc7180: Add pdc interrupt controller
Quoting Bjorn Andersson (2019-11-03 23:10:27)
Quoted 8 lines
Right, but by putting both compatibles in the dts and the generic one in the driver we avoid the driver churn and we're future compatible.
And given that we haven't yet added the qcom,sdm845-pdc node to the
sdm845.dtsiwe don't need to maintain the qcom,sdm845-pdc in the driver. So switch qcom,sdm845-pdc to qcom,pdc inqcom-pdc.c.
I like this plan!