Add Error Disconnect Recover (EDR) support

From: Kuppuswamy Sathyanarayanan <[email protected]>

As per ACPI specification r6.3, sec 5.6.6, when firmware owns Downstream Port Containment (DPC), its expected to use the "Error Disconnect Recover" (EDR) notification to alert OSPM of a DPC event and if OS supports EDR, its expected to handle the software state invalidation and port recovery in OS, and also let firmware know the recovery status via _OST ACPI call. Related _OST status codes can be found in ACPI specification r6.3, sec 6.3.5.2.

Also, as per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, table 4-6, If DPC is controlled by firmware (firmware first mode), firmware is responsible for configuring the DPC and OS is responsible for error recovery. Also, OS is allowed to modify DPC registers only during the EDR notification window. So with EDR support, OS should provide DPC port services even in firmware first mode.

Cc Keith Busch <[email protected]>

Signed-off-by Kuppuswamy Sathyanarayanan <[email protected]>

Acked-by Keith Busch <[email protected]>

Tested-by Huong Nguyen <[email protected]>

Tested-by Austin Bolen <[email protected]>

---
 drivers/pci/pci-acpi.c   |  98 ++++++++++++++++++++++++++++++
 drivers/pci/pcie/Kconfig |  10 ++++
 drivers/pci/pcie/dpc.c   | 125 ++++++++++++++++++++++++++++++++++++++-
 include/linux/pci-acpi.h |  11 ++++
 4 files changed, 243 insertions(+), 1 deletion(-)

drivers/pci/pci-acpi.c +0 -0

index 0c02d500158f..13086518de27 100644

drivers/pci/pci-acpi.c +17 -0

+/*
+ * _DSM wrapper function to enable/disable DPC port.
+ * @dpc   : DPC device structure
+ * @enable: status of DPC port (0 or 1).
+ *
+ * returns 0 on success or errno on failure.
+ */
+int acpi_enable_dpc_port(struct pci_dev *pdev, acpi_handle handle, bool enable)
+{
+	union acpi_object *obj, argv4, req;
+	int status = 0;
+
+	req.type = ACPI_TYPE_INTEGER;
+	req.integer.value = enable;
+
+	argv4.type = ACPI_TYPE_PACKAGE;
+	argv4.package.count = 1;

drivers/pci/pci-acpi.c +69 -0

+
+	if (obj->type != ACPI_TYPE_INTEGER || obj->integer.value != enable)
+		status = -EIO;
+
+	ACPI_FREE(obj);
+
+	return status;
+}
+
+/*
+ * _DSM wrapper function to locate DPC port.
+ * @dpc   : DPC device structure
+ *
+ * returns pci_dev or NULL.
+ */
+struct pci_dev *acpi_locate_dpc_port(struct pci_dev *pdev, acpi_handle handle)
+{
+	union acpi_object *obj;
+	u16 port;
+
+	obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 5,
+				EDR_PORT_LOCATE_DSM, NULL);
+	if (!obj)
+		return pci_dev_get(pdev);
+
+	if (obj->type != ACPI_TYPE_INTEGER) {
+		ACPI_FREE(obj);
+		return NULL;
+	}
+
+	/*
+	 * Firmware returns DPC port BDF details in following format:
+	 *	15:8 = bus
+	 *	7:3 = device
+	 *	2:0 = function
+	 */
+	port = obj->integer.value;
+
+	ACPI_FREE(obj);
+
+	return pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
+					   PCI_BUS_NUM(port), port & 0xff);
+}
+
+/*
+ * _OST wrapper function to let firmware know the status of EDR event.
+ * @dpc   : DPC device structure.
+ * @status: Status of EDR event.
+ */
+int acpi_send_edr_status(struct pci_dev *pdev,  acpi_handle handle, u16 status)
+{
+	u32 ost_status;
+
+	pci_dbg(pdev, "Sending EDR status :%x\n", status);
+
+	ost_status =  PCI_DEVID(pdev->bus->number, pdev->devfn);
+	ost_status = (ost_status << 16) | status;
+
+	status = acpi_evaluate_ost(handle,
+				   ACPI_NOTIFY_DISCONNECT_RECOVER,
+				   ost_status, NULL);
+	if (ACPI_FAILURE(status))
+		return -EINVAL;
+
+	return 0;
+}
+
+#endif /* CONFIG_PCIE_DPC && CONFIG_ACPI */
+
 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 {
 	acpi_status status = AE_NOT_EXIST;

drivers/pci/pcie/Kconfig +10 -0

index 6e3c04b46fb1..2db8a3109cb5 100644
@@ -140,3 +140,13 @@ config PCIE_BW
 	  This enables PCI Express Bandwidth Change Notification.  If
 	  you know link width or rate changes occur only to correct
 	  unreliable links, you may answer Y.
+
+config PCIE_EDR
+	bool "PCI Express Error Disconnect Recover support"
+	default n
+	depends on PCIE_DPC && ACPI
+	help
+	  This options adds Error Disconnect Recover support as specified
+	  in PCI firmware specification v3.2 Downstream Port Containment
+	  Related Enhancements ECN. Enable this if you want to support hybrid
+	  DPC model which uses both firmware and OS to implement DPC.

drivers/pci/pcie/dpc.c +53 -0

index d29f5d25f3f9..63366344acff 100644
@@ -13,6 +13,8 @@
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/pci.h>
+#include <linux/acpi.h>
+#include <linux/pci-acpi.h>
 
 #include "portdrv.h"
 #include "../pci.h"

@@ -23,6 +25,11 @@ struct dpc_dev {
 	bool			rp_extensions;
 	u8			rp_log_size;
 	bool			edr_enabled; /* EDR mode is supported */
+	pci_ers_result_t	error_state;
+	struct mutex		edr_lock;
+#ifdef CONFIG_ACPI
+	struct acpi_device	*adev;
+#endif
 };
 
 static const char * const rp_pio_error_string[] = {

@@ -161,6 +168,9 @@ static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
 	if (!pcie_wait_for_link(pdev, true))
 		return PCI_ERS_RESULT_DISCONNECT;
 
+	/* Since the device recovery is done just update the error state */
+	dpc->error_state = PCI_ERS_RESULT_RECOVERED;
 	return PCI_ERS_RESULT_RECOVERED;
 }
 

@@ -305,13 +315,93 @@ static irqreturn_t dpc_irq(int irq, void *context)
 	return IRQ_HANDLED;
 }
 
+static void dpc_error_resume(struct pci_dev *dev)
+{
+	struct dpc_dev *dpc = to_dpc_dev(dev);
+
+	dpc->error_state = PCI_ERS_RESULT_RECOVERED;
+}
+
+#ifdef CONFIG_ACPI
+
+static void edr_handle_event(acpi_handle handle, u32 event, void *data)
+{
+	struct dpc_dev *dpc = (struct dpc_dev *) data;
+	struct pci_dev *pdev = dpc->dev->port;
+	u16 status;
+
+	pci_info(pdev, "ACPI event %x received\n", event);
+
+	if (event != ACPI_NOTIFY_DISCONNECT_RECOVER)
+		return;
+
+	/*
+	 * Check if _DSM(0xD) is available, and if present locate the
+	 * port which issued EDR event.
+	 */
+	pdev = acpi_locate_dpc_port(pdev, dpc->adev->handle);
+	if (!pdev) {
+		pdev = dpc->dev->port;
+		pci_err(pdev, "No valid port found\n");
+		return;
+	}
+
+	dpc = to_dpc_dev(pdev);
+	if (!dpc) {
+		pci_err(pdev, "DPC port is NULL\n");
+		goto done;
+	}
+
+	mutex_lock(&dpc->edr_lock);
+
+	dpc->error_state = PCI_ERS_RESULT_DISCONNECT;
+
+	/*
+	 * Check if the port supports DPC:
+	 *

drivers/pci/pcie/dpc.c +14 -1

+	acpi_send_edr_status(pdev, dpc->adev->handle, status);
+
+edr_unlock:
+	mutex_unlock(&dpc->edr_lock);
+done:
+	pci_dev_put(pdev);
+}
+
+#endif
+
 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
 static int dpc_probe(struct pcie_device *dev)
 {
 	struct dpc_dev *dpc;
 	struct pci_dev *pdev = dev->port;
 	struct device *device = &dev->device;
-	int status;
+	int status = 0;
 	u16 ctl, cap;
 
 	dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);

@@ -324,6 +414,9 @@ static int dpc_probe(struct pcie_device *dev)
 		dpc->edr_enabled = 1;
 	set_service_data(dev, dpc);
 
+	dpc->error_state = PCI_ERS_RESULT_NONE;
+	mutex_init(&dpc->edr_lock);
+
 	/*
 	 * As per PCIe spec r5.0, implementation note titled "Determination
 	 * of DPC Control", to avoid conflicts over whether platform

drivers/pci/pcie/dpc.c +27 -0

+	if (pcie_aer_get_firmware_first(pdev) && adev) {
+		acpi_status astatus;
+
+		dpc->adev = adev;
+
+		astatus = acpi_install_notify_handler(adev->handle,
+						      ACPI_SYSTEM_NOTIFY,
+						      edr_handle_event,
+						      dpc);
+
+		if (ACPI_FAILURE(astatus)) {
+			pci_err(pdev,
+				"Install ACPI_SYSTEM_NOTIFY handler failed\n");
+			return -EBUSY;
+		}
+
+		status = acpi_enable_dpc_port(pdev, adev->handle, true);
+		if (status) {
+			pci_warn(pdev, "Enable DPC port failed\n");
+			acpi_remove_notify_handler(adev->handle,
+						   ACPI_SYSTEM_NOTIFY,
+						   edr_handle_event);
+			return status;
+		}
+	}
+#endif
 	pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
 	pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 

@@ -403,6 +525,7 @@ static struct pcie_port_service_driver dpcdriver = {
 	.probe		= dpc_probe,
 	.remove		= dpc_remove,
 	.reset_link	= dpc_reset_link,
+	.error_resume   = dpc_error_resume,
 };
 
 int __init pcie_dpc_init(void)

include/linux/pci-acpi.h +0 -0

index 62b7fdcc661c..36ffe1e16e69 100644

include/linux/pci-acpi.h +8 -0

+int acpi_enable_dpc_port(struct pci_dev *pdev, acpi_handle handle,
+			 bool enable);
+struct pci_dev *acpi_locate_dpc_port(struct pci_dev *pdev,
+				     acpi_handle handle);
+int acpi_send_edr_status(struct pci_dev *pdev,
+			 acpi_handle handle, u16 status);
+#endif
+
 #ifdef CONFIG_ACPI_APEI
 extern bool aer_acpi_firmware_first(void);
 #else

Signature · 1 line

2.21.0

From: Kuppuswamy Sathyanarayanan <[email protected]>

As per PCI firmware specification r3.2 System Firmware Intermediary (SFI) _OSC and DPC Updates ECR
(https://members.pcisig.com/wg/PCI-SIG/document/13563), sec titled "DPC Event Handling Implementation Note", page 10, Error Disconnect Recover (EDR) support allows OS to handle error recovery and clearing Error Registers even in FF mode. So create exception for FF mode checks in pci_cleanup_aer_uncorrect_error_status(), pci_aer_clear_fatal_status() and pci_cleanup_aer_error_status_regs() functions when its being called from DPC code path.

Signed-off-by Kuppuswamy Sathyanarayanan <[email protected]>

Acked-by Keith Busch <[email protected]>

---
 Documentation/PCI/pcieaer-howto.rst       |  2 +-
 drivers/net/ethernet/intel/ice/ice_main.c |  2 +-
 drivers/ntb/hw/idt/ntb_hw_idt.c           |  2 +-
 drivers/pci/pci.c                         |  2 +-
 drivers/pci/pci.h                         |  2 +-
 drivers/pci/pcie/aer.c                    | 16 ++++++++--------
 drivers/pci/pcie/dpc.c                    |  4 ++--
 drivers/pci/pcie/err.c                    |  2 +-
 drivers/scsi/lpfc/lpfc_attr.c             |  2 +-
 include/linux/aer.h                       | 12 ++++++++----
 10 files changed, 25 insertions(+), 21 deletions(-)

Documentation/PCI/pcieaer-howto.rst +1 -1

index 18bdefaafd1a..184c966b61cb 100644
@@ -243,7 +243,7 @@ messages to root port when an error is detected.
 
 ::
 
-  int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);`
+  int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev, bool ff_check);
 
 pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable
 error status register.

drivers/net/ethernet/intel/ice/ice_main.c +1 -1

index 69bff085acf7..8378dbf3500b 100644
@@ -3491,7 +3491,7 @@ static pci_ers_result_t ice_pci_err_slot_reset(struct pci_dev *pdev)
 			result = PCI_ERS_RESULT_DISCONNECT;
 	}
 
-	err = pci_cleanup_aer_uncorrect_error_status(pdev);
+	err = pci_cleanup_aer_uncorrect_error_status(pdev, 1);
 	if (err)
 		dev_dbg(&pdev->dev,
 			"pci_cleanup_aer_uncorrect_error_status failed, error %d\n",

drivers/ntb/hw/idt/ntb_hw_idt.c +1 -1

index dcf234680535..9023308be2de 100644
@@ -2675,7 +2675,7 @@ static int idt_init_pci(struct idt_ntb_dev *ndev)
 	if (ret != 0)
 		dev_warn(&pdev->dev, "PCIe AER capability disabled\n");
 	else /* Cleanup uncorrectable error status before getting to init */
-		pci_cleanup_aer_uncorrect_error_status(pdev);
+		pci_cleanup_aer_uncorrect_error_status(pdev, 1);
 
 	/* First enable the PCI device */
 	ret = pcim_enable_device(pdev);

drivers/pci/pcie/dpc.c +2 -2

index 63366344acff..5bd72d9343f6 100644
@@ -280,8 +280,8 @@ static void dpc_process_error(struct dpc_dev *dpc)
 		 dpc_get_aer_uncorrect_severity(pdev, &info) &&
 		 aer_get_device_error_info(pdev, &info)) {
 		aer_print_error(pdev, &info);
-		pci_cleanup_aer_uncorrect_error_status(pdev);
-		pci_aer_clear_fatal_status(pdev);
+		pci_cleanup_aer_uncorrect_error_status(pdev, 0);
+		pci_aer_clear_fatal_status(pdev, 0);
 	}
 
 	/* We configure DPC so it only triggers on ERR_FATAL */

drivers/scsi/lpfc/lpfc_attr.c +1 -1

index 4ff82b36a37a..5b37efd29e20 100644
@@ -4810,7 +4810,7 @@ lpfc_aer_cleanup_state(struct device *dev, struct device_attribute *attr,
 		return -EINVAL;
 
 	if (phba->hba_flag & HBA_AER_ENABLED)
-		rc = pci_cleanup_aer_uncorrect_error_status(phba->pcidev);
+		rc = pci_cleanup_aer_uncorrect_error_status(phba->pcidev, 1);
 
 	if (rc == 0)
 		return strlen(buf);

include/linux/aer.h +0 -0

index fa19e01f418a..f4f49df500ad 100644

include/linux/aer.h +4 -2

 void pci_save_aer_state(struct pci_dev *dev);
 void pci_restore_aer_state(struct pci_dev *dev);
 #else

@@ -57,11 +59,13 @@ static inline int pci_disable_pcie_error_reporting(struct pci_dev *dev)
 {
 	return -EINVAL;
 }
-static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
+static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev,
+							 bool ff_check)
 {
 	return -EINVAL;
 }
-static inline int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)
+static inline int pci_cleanup_aer_error_status_regs(struct pci_dev *dev,
+						    bool ff_check)
 {
 	return -EINVAL;
 }

Signature · 1 line

2.21.0

From: Kuppuswamy Sathyanarayanan <[email protected]>

As per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, OS must implement following steps to enable/use EDR feature.

1. OS can use bit 7 of _OSC Control Field to negotiate control over Downstream Port Containment (DPC) configuration of PCIe port. After _OSC negotiation, firmware will Set this bit to grant OS control over PCIe DPC configuration and Clear it if this feature was requested and denied, or was not requested.

2. Also, if OS supports EDR, it should expose its support to BIOS by setting bit 7 of _OSC Support Field. And if OS sets bit 7 of _OSC Control Field it must also expose support for EDR by setting bit 7 of _OSC Support Field.

Cc Bjorn Helgaas <[email protected]>

Cc "Rafael J. Wysocki" <[email protected]>

Cc Len Brown <[email protected]>

Signed-off-by Kuppuswamy Sathyanarayanan <[email protected]>

Acked-by Keith Busch <[email protected]>

Tested-by Huong Nguyen <[email protected]>

Tested-by Austin Bolen <[email protected]>

---
 drivers/acpi/pci_root.c         | 9 +++++++++
 drivers/pci/pcie/portdrv_core.c | 7 +++++--
 drivers/pci/probe.c             | 1 +
 include/linux/acpi.h            | 6 ++++--
 include/linux/pci.h             | 3 ++-
 5 files changed, 21 insertions(+), 5 deletions(-)

drivers/acpi/pci_root.c +4 -0

index d1e666ef3fcc..134e20474dfd 100644
@@ -131,6 +131,7 @@ static struct pci_osc_bit_struct pci_osc_support_bit[] = {
 	{ OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
 	{ OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
 	{ OSC_PCI_MSI_SUPPORT, "MSI" },
+	{ OSC_PCI_EDR_SUPPORT, "EDR" },
 	{ OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
 };
 

@@ -141,6 +142,7 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = {
 	{ OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
 	{ OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
 	{ OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
+	{ OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
 };
 
 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,

@@ -440,6 +442,8 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
 		support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
 	if (pci_msi_enabled())
 		support |= OSC_PCI_MSI_SUPPORT;
+	if (IS_ENABLED(CONFIG_PCIE_EDR))
+		support |= OSC_PCI_EDR_SUPPORT;
 
 	decode_osc_support(root, "OS supports", support);
 	status = acpi_pci_osc_support(root, support);

drivers/acpi/pci_root.c +2 -0

 	requested = control;
 	status = acpi_pci_osc_control_set(handle, &control,
 					  OSC_PCI_EXPRESS_CAPABILITY_CONTROL);

@@ -916,6 +923,8 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
 		host_bridge->native_pme = 0;
 	if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
 		host_bridge->native_ltr = 0;
+	if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
+		host_bridge->native_dpc = 0;
 
 	/*
 	 * Evaluate the "PCI Boot Configuration" _DSM Function.  If it

drivers/pci/pcie/portdrv_core.c +5 -2

index 5075cb9e850c..009742c865d6 100644
@@ -253,10 +253,13 @@ static int get_port_device_capability(struct pci_dev *dev)
 	/*
 	 * With dpc-native, allow Linux to use DPC even if it doesn't have
 	 * permission to use AER.
+	 * If EDR support is enabled in OS, then even if AER is not handled in
+	 * OS, DPC service can be enabled.
 	 */
 	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) &&
-	    pci_aer_available() &&
-	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))
+	    ((IS_ENABLED(CONFIG_PCIE_EDR) && !host->native_dpc) ||
+	    (pci_aer_available() &&
+	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))))
 		services |= PCIE_PORT_SERVICE_DPC;
 
 	if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||

drivers/pci/probe.c +1 -0

index 512cb4312ddd..c9a9c5b42e72 100644
@@ -598,6 +598,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
 	bridge->native_shpc_hotplug = 1;
 	bridge->native_pme = 1;
 	bridge->native_ltr = 1;
+	bridge->native_dpc = 1;
 }
 
 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)

include/linux/acpi.h +4 -2

index 0f37a7d5fa77..0a7aaa452a98 100644
@@ -515,8 +515,9 @@ extern bool osc_pc_lpi_support_confirmed;
 #define OSC_PCI_CLOCK_PM_SUPPORT		0x00000004
 #define OSC_PCI_SEGMENT_GROUPS_SUPPORT		0x00000008
 #define OSC_PCI_MSI_SUPPORT			0x00000010
+#define OSC_PCI_EDR_SUPPORT			0x00000080
 #define OSC_PCI_HPX_TYPE_3_SUPPORT		0x00000100
-#define OSC_PCI_SUPPORT_MASKS			0x0000011f
+#define OSC_PCI_SUPPORT_MASKS			0x0000019f
 
 /* PCI Host Bridge _OSC: Capabilities DWORD 3: Control Field */
 #define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL	0x00000001

@@ -525,7 +526,8 @@ extern bool osc_pc_lpi_support_confirmed;
 #define OSC_PCI_EXPRESS_AER_CONTROL		0x00000008
 #define OSC_PCI_EXPRESS_CAPABILITY_CONTROL	0x00000010
 #define OSC_PCI_EXPRESS_LTR_CONTROL		0x00000020
-#define OSC_PCI_CONTROL_MASKS			0x0000003f
+#define OSC_PCI_EXPRESS_DPC_CONTROL		0x00000080
+#define OSC_PCI_CONTROL_MASKS			0x000000bf
 
 #define ACPI_GSB_ACCESS_ATTRIB_QUICK		0x00000002
 #define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV         0x00000004

include/linux/pci.h +0 -0

index c393dff2d66f..0b7c63c7888d 100644

include/linux/pci.h +0 -0

 	/* Resource alignment requirements */
 	resource_size_t (*align_resource)(struct pci_dev *dev,
 			const struct resource *res,

Signature · 1 line

2.21.0

Quoted 62 lines · On Sun, Jan 12, 2020 at 02:44:02PM -0800…

From: Kuppuswamy Sathyanarayanan <[email protected]>

As per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, OS must implement following steps to enable/use EDR feature.

1. OS can use bit 7 of _OSC Control Field to negotiate control over Downstream Port Containment (DPC) configuration of PCIe port. After _OSC negotiation, firmware will Set this bit to grant OS control over PCIe DPC configuration and Clear it if this feature was requested and denied, or was not requested.

2. Also, if OS supports EDR, it should expose its support to BIOS by setting bit 7 of _OSC Support Field. And if OS sets bit 7 of _OSC Control Field it must also expose support for EDR by setting bit 7 of _OSC Support Field.

Cc Bjorn Helgaas <[email protected]>

Cc "Rafael J. Wysocki" <[email protected]>

Cc Len Brown <[email protected]>

Signed-off-by Kuppuswamy Sathyanarayanan <[email protected]>

Acked-by Keith Busch <[email protected]>

Tested-by Huong Nguyen <[email protected]>

Tested-by Austin Bolen <[email protected]>

---
  drivers/acpi/pci_root.c         | 9 +++++++++
  drivers/pci/pcie/portdrv_core.c | 7 +++++--
  drivers/pci/probe.c             | 1 +
  include/linux/acpi.h            | 6 ++++--
  include/linux/pci.h             | 3 ++-
  5 files changed, 21 insertions(+), 5 deletions(-)

drivers/acpi/pci_root.c +4 -0

index d1e666ef3fcc..134e20474dfd 100644
@@ -131,6 +131,7 @@ static struct pci_osc_bit_struct pci_osc_support_bit[] = {
  	{ OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
  	{ OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
  	{ OSC_PCI_MSI_SUPPORT, "MSI" },
+	{ OSC_PCI_EDR_SUPPORT, "EDR" },
  	{ OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
  };
 

@@ -141,6 +142,7 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = {
  	{ OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
  	{ OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
  	{ OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
+	{ OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
  };
 
  static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,

@@ -440,6 +442,8 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
  		support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
  	if (pci_msi_enabled())
  		support |= OSC_PCI_MSI_SUPPORT;
+	if (IS_ENABLED(CONFIG_PCIE_EDR))
+		support |= OSC_PCI_EDR_SUPPORT;
 
  	decode_osc_support(root, "OS supports", support);
  	status = acpi_pci_osc_support(root, support);

drivers/acpi/pci_root.c static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, · line 495

Quoted 5 lines

drivers/acpi/pci_root.c +2 -0

@@ -487,6 +491,9 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
  			control |= OSC_PCI_EXPRESS_AER_CONTROL;
  	}
 
+	if (IS_ENABLED(CONFIG_PCIE_DPC))
+		control |= OSC_PCI_EXPRESS_DPC_CONTROL;

The ECN [1] says:

If this bit is set by the OS, this indicates that it supports both native OS control and firmware ownership models (i.e. Error Disconnect Recover notification) of Downstream Port Containment.

But if CONFIG_PCIE_DPC=y and CONFIG_PCIE_EDR is not set, we will set OSC_PCI_EXPRESS_DPC_CONTROL even though we don't support EDR. That doesn't seem to match what the spec says.

I think this needs to be something like:

   if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
     control |= OSC_PCI_EXPRESS_DPC_CONTROL;

[1] Downstream Port Containment related Enhancements, PCI ECN, Jan 28, 2019, Section 4.5.1, Table 4-5.

Quoted 74 lines

drivers/acpi/pci_root.c +2 -0

  	requested = control;
  	status = acpi_pci_osc_control_set(handle, &control,
  					  OSC_PCI_EXPRESS_CAPABILITY_CONTROL);

@@ -916,6 +923,8 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
  		host_bridge->native_pme = 0;
  	if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
  		host_bridge->native_ltr = 0;
+	if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
+		host_bridge->native_dpc = 0;
 
  	/*
  	 * Evaluate the "PCI Boot Configuration" _DSM Function.  If it

drivers/pci/pcie/portdrv_core.c +5 -2

index 5075cb9e850c..009742c865d6 100644
@@ -253,10 +253,13 @@ static int get_port_device_capability(struct pci_dev *dev)
  	/*
  	 * With dpc-native, allow Linux to use DPC even if it doesn't have
  	 * permission to use AER.
+	 * If EDR support is enabled in OS, then even if AER is not handled in
+	 * OS, DPC service can be enabled.
  	 */
  	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) &&
-	    pci_aer_available() &&
-	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))
+	    ((IS_ENABLED(CONFIG_PCIE_EDR) && !host->native_dpc) ||
+	    (pci_aer_available() &&
+	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))))
  		services |= PCIE_PORT_SERVICE_DPC;
 
  	if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM ||

drivers/pci/probe.c +1 -0

index 512cb4312ddd..c9a9c5b42e72 100644
@@ -598,6 +598,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
  	bridge->native_shpc_hotplug = 1;
  	bridge->native_pme = 1;
  	bridge->native_ltr = 1;
+	bridge->native_dpc = 1;
  }
 
  struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)

include/linux/acpi.h +4 -2

index 0f37a7d5fa77..0a7aaa452a98 100644
@@ -515,8 +515,9 @@ extern bool osc_pc_lpi_support_confirmed;
  #define OSC_PCI_CLOCK_PM_SUPPORT		0x00000004
  #define OSC_PCI_SEGMENT_GROUPS_SUPPORT		0x00000008
  #define OSC_PCI_MSI_SUPPORT			0x00000010
+#define OSC_PCI_EDR_SUPPORT			0x00000080
  #define OSC_PCI_HPX_TYPE_3_SUPPORT		0x00000100
-#define OSC_PCI_SUPPORT_MASKS			0x0000011f
+#define OSC_PCI_SUPPORT_MASKS			0x0000019f
 
  /* PCI Host Bridge _OSC: Capabilities DWORD 3: Control Field */
  #define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL	0x00000001

@@ -525,7 +526,8 @@ extern bool osc_pc_lpi_support_confirmed;
  #define OSC_PCI_EXPRESS_AER_CONTROL		0x00000008
  #define OSC_PCI_EXPRESS_CAPABILITY_CONTROL	0x00000010
  #define OSC_PCI_EXPRESS_LTR_CONTROL		0x00000020
-#define OSC_PCI_CONTROL_MASKS			0x0000003f
+#define OSC_PCI_EXPRESS_DPC_CONTROL		0x00000080
+#define OSC_PCI_CONTROL_MASKS			0x000000bf
 
  #define ACPI_GSB_ACCESS_ATTRIB_QUICK		0x00000002
  #define ACPI_GSB_ACCESS_ATTRIB_SEND_RCV         0x00000004

include/linux/pci.h +0 -0

index c393dff2d66f..0b7c63c7888d 100644

include/linux/pci.h struct pci_host_bridge { · line 515

Quoted 7 lines

include/linux/pci.h +2 -1

@@ -510,8 +510,9 @@ struct pci_host_bridge {
  	unsigned int	native_shpc_hotplug:1;	/* OS may use SHPC hotplug */
  	unsigned int	native_pme:1;		/* OS may use PCIe PME */
  	unsigned int	native_ltr:1;		/* OS may use PCIe LTR */
-	unsigned int	preserve_config:1;	/* Preserve FW resource setup */
+	unsigned int	native_dpc:1;		/* OS may use PCIe DPC */
 
+	unsigned int	preserve_config:1;	/* Preserve FW resource setup */

The blank line should stay after the bitfields. Then this will look like the simple insertion of native_dpc, as it should.

Quoted 6 lines

include/linux/pci.h +0 -0

  	/* Resource alignment requirements */
  	resource_size_t (*align_resource)(struct pci_dev *dev,
  			const struct resource *res,

Signature · 1 line

2.21.0

Quoted 66 lines · Bjorn Helgaas

Quoted 59 lines · On Sun, Jan 12, 2020 at 02:44:02PM -0800…

From: Kuppuswamy Sathyanarayanan <[email protected]>

As per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, OS must implement following steps to enable/use EDR feature.

1. OS can use bit 7 of _OSC Control Field to negotiate control over Downstream Port Containment (DPC) configuration of PCIe port. After _OSC negotiation, firmware will Set this bit to grant OS control over PCIe DPC configuration and Clear it if this feature was requested and denied, or was not requested.

2. Also, if OS supports EDR, it should expose its support to BIOS by setting bit 7 of _OSC Support Field. And if OS sets bit 7 of _OSC Control Field it must also expose support for EDR by setting bit 7 of _OSC Support Field.

Cc Bjorn Helgaas <[email protected]>

Cc "Rafael J. Wysocki" <[email protected]>

Cc Len Brown <[email protected]>

Signed-off-by Kuppuswamy Sathyanarayanan <[email protected]>

Acked-by Keith Busch <[email protected]>

Tested-by Huong Nguyen <[email protected]>

Tested-by Austin Bolen <[email protected]>

---
  drivers/acpi/pci_root.c         | 9 +++++++++
  drivers/pci/pcie/portdrv_core.c | 7 +++++--
  drivers/pci/probe.c             | 1 +
  include/linux/acpi.h            | 6 ++++--
  include/linux/pci.h             | 3 ++-
  5 files changed, 21 insertions(+), 5 deletions(-)

drivers/acpi/pci_root.c +4 -0

index d1e666ef3fcc..134e20474dfd 100644
@@ -131,6 +131,7 @@ static struct pci_osc_bit_struct pci_osc_support_bit[] = {
  	{ OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
  	{ OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
  	{ OSC_PCI_MSI_SUPPORT, "MSI" },
+	{ OSC_PCI_EDR_SUPPORT, "EDR" },
  	{ OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
  };

@@ -141,6 +142,7 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = {
  	{ OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
  	{ OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
  	{ OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
+	{ OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
  };
  static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,

@@ -440,6 +442,8 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
  		support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
  	if (pci_msi_enabled())
  		support |= OSC_PCI_MSI_SUPPORT;
+	if (IS_ENABLED(CONFIG_PCIE_EDR))
+		support |= OSC_PCI_EDR_SUPPORT;
  	decode_osc_support(root, "OS supports", support);
  	status = acpi_pci_osc_support(root, support);

drivers/acpi/pci_root.c static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm, · line 494

Quoted 4 lines

drivers/acpi/pci_root.c +2 -0

@@ -487,6 +491,9 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
  			control |= OSC_PCI_EXPRESS_AER_CONTROL;
  	}
+	if (IS_ENABLED(CONFIG_PCIE_DPC))
+		control |= OSC_PCI_EXPRESS_DPC_CONTROL;

The ECN [1] says:

Quoted 7 lines

If this bit is set by the OS, this indicates that it supports both native OS control and firmware ownership models (i.e. Error Disconnect Recover notification) of Downstream Port Containment.

But if CONFIG_PCIE_DPC=y and CONFIG_PCIE_EDR is not set, we will set OSC_PCI_EXPRESS_DPC_CONTROL even though we don't support EDR. That doesn't seem to match what the spec says.

Agreed.

Quoted 3 lines

I think this needs to be something like:

Quoted 2 lines

   if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
     control |= OSC_PCI_EXPRESS_DPC_CONTROL;

Since CONFIG_PCIE_EDR has dependency on CONFIG_PCIE_DPC, I think we can just use IS_ENABLED(CONFIG_PCIE_EDR) here.

I will fix it and send an update. You want to me to send a new patch set of just an update to this patch ?

I'm still working through the rest of these, so I'd suggest making this change in your local copy but waiting to send it for a few days. Unless there's more substantial stuff to change, I can fix this myself.

Bjorn

From: Kuppuswamy Sathyanarayanan <[email protected]>

As per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, OS must implement following steps to enable/use EDR feature.

1. OS can use bit 7 of _OSC Control Field to negotiate control over Downstream Port Containment (DPC) configuration of PCIe port. After _OSC negotiation, firmware will Set this bit to grant OS control over PCIe DPC configuration and Clear it if this feature was requested and denied, or was not requested.

2. Also, if OS supports EDR, it should expose its support to BIOS by setting bit 7 of _OSC Support Field. And if OS sets bit 7 of _OSC Control Field it must also expose support for EDR by setting bit 7 of _OSC Support Field.

drivers/pci/pcie/portdrv_core.c +3 -2

 	 */
 	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) &&
-	    pci_aer_available() &&
-	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))
+	    ((IS_ENABLED(CONFIG_PCIE_EDR) && !host->native_dpc) ||
+	    (pci_aer_available() &&
+	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))))
 		services |= PCIE_PORT_SERVICE_DPC;

Quoted 12 lines · On Sun, Jan 12, 2020 at 02:44:02PM -0800…

From: Kuppuswamy Sathyanarayanan <[email protected]>

As per PCI firmware specification r3.2 Downstream Port Containment Related Enhancements ECN, sec 4.5.1, OS must implement following steps to enable/use EDR feature.

1. OS can use bit 7 of _OSC Control Field to negotiate control over Downstream Port Containment (DPC) configuration of PCIe port. After _OSC negotiation, firmware will Set this bit to grant OS control over PCIe DPC configuration and Clear it if this feature was requested and denied, or was not requested.

drivers/pci/pcie/portdrv_core.c static int get_port_device_capability(struct pci_dev *dev) · line 257

Quoted 12 lines

2. Also, if OS supports EDR, it should expose its support to BIOS by setting bit 7 of _OSC Support Field. And if OS sets bit 7 of _OSC Control Field it must also expose support for EDR by setting bit 7 of _OSC Support Field.

drivers/pci/pcie/portdrv_core.c +2 -0

@@ -253,10 +253,13 @@ static int get_port_device_capability(struct pci_dev *dev)
  	/*
  	 * With dpc-native, allow Linux to use DPC even if it doesn't have
  	 * permission to use AER.
+	 * If EDR support is enabled in OS, then even if AER is not handled in
+	 * OS, DPC service can be enabled.

Can you clarify this comment? It talks about AER, but the code you added:

   (IS_ENABLED(CONFIG_PCIE_EDR) && !host->native_dpc)

doesn't have anything to do with AER.

Quoted 8 lines

drivers/pci/pcie/portdrv_core.c +3 -2

  	 */
  	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) &&
-	    pci_aer_available() &&
-	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))
+	    ((IS_ENABLED(CONFIG_PCIE_EDR) && !host->native_dpc) ||
+	    (pci_aer_available() &&
+	    (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER)))))
  		services |= PCIE_PORT_SERVICE_DPC;

From: Kuppuswamy Sathyanarayanan <[email protected]>
...
Changes since v11:
* Allowed error recovery to proceed after successful reset_link().
* Used correct ACPI handle for sending EDR status.
* Rebased on top of v5.5-rc5

From: Kuppuswamy Sathyanarayanan <[email protected]>

This patchset adds support for following features:

1. Error Disconnect Recover (EDR) support.
2. _OSC based negotiation support for DPC.

You can find EDR spec in the following link.

https://members.pcisig.com/wg/PCI-SIG/document/12614

Quoted 4 lines · On Sun, Jan 12, 2020 at 02:43:54PM -0800…

From: Kuppuswamy Sathyanarayanan <[email protected]>

This patchset adds support for following features:

Quoted 6 lines

1. Error Disconnect Recover (EDR) support.
2. _OSC based negotiation support for DPC.

You can find EDR spec in the following link.

https://members.pcisig.com/wg/PCI-SIG/document/12614

When you update this, please incorporate the changes I've made below..

drivers/acpi/pci_root.c +7 -1

index 134e20474dfd..0cb9df5462c3 100644
@@ -491,7 +491,13 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
  			control |= OSC_PCI_EXPRESS_AER_CONTROL;
  	}
 
-	if (IS_ENABLED(CONFIG_PCIE_DPC))
+	/*
+	 * Per the Downstream Port Containment Related Enhancements ECN to
+	 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5,
+	 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC
+	 * and EDR.
+	 */
+	if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
  		control |= OSC_PCI_EXPRESS_DPC_CONTROL;
 
  	requested = control;

drivers/pci/pci-acpi.c +8 -8

index 13086518de27..547089361d4d 100644
@@ -103,8 +103,7 @@ int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
  }
  #endif
 
-#if defined(CONFIG_PCIE_DPC) && defined(CONFIG_ACPI)
-
+#if defined(CONFIG_PCIE_DPC)
  /*
   * _DSM wrapper function to enable/disable DPC port.
   * @dpc   : DPC device structure

@@ -124,14 +123,15 @@ int acpi_enable_dpc_port(struct pci_dev *pdev, acpi_handle handle, bool enable)
  	argv4.package.count = 1;
  	argv4.package.elements = &req;
 
-	/* As per PCI firmware specification r3.2 Downstream Port Containment
-	 * Related Enhancements ECN, sec 4.6.12, EDR_PORT_ENABLE_DSM is
-	 * optional and hence if its not implemented return success.
+	/*
+	 * Per the Downstream Port Containment Related Enhancements ECN to
+	 * the PCI Firmware Specification r3.2, sec 4.6.12,
+	 * EDR_PORT_ENABLE_DSM is optional.  Return success if it's not
+	 * implemented.
  	 */
-	obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 5,
-				EDR_PORT_ENABLE_DSM, &argv4);
+	obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 5, EDR_PORT_ENABLE_DSM, &argv4);
  	if (!obj)
-		return status;
+		return 0;
 
  	if (obj->type != ACPI_TYPE_INTEGER || obj->integer.value != enable)
  		status = -EIO;

drivers/pci/pci-acpi.c +5 -6

  	if (!obj)
  		return pci_dev_get(pdev);
 

@@ -165,8 +164,8 @@ struct pci_dev *acpi_locate_dpc_port(struct pci_dev *pdev, acpi_handle handle)
  	/*
  	 * Firmware returns DPC port BDF details in following format:
  	 *	15:8 = bus
-	 *	7:3 = device
-	 *	2:0 = function
+	 *	 7:3 = device
+	 *	 2:0 = function
  	 */
  	port = obj->integer.value;
 

@@ -181,11 +180,11 @@ struct pci_dev *acpi_locate_dpc_port(struct pci_dev *pdev, acpi_handle handle)
   * @dpc   : DPC device structure.
   * @status: Status of EDR event.
   */
-int acpi_send_edr_status(struct pci_dev *pdev,  acpi_handle handle, u16 status)
+int acpi_send_edr_status(struct pci_dev *pdev, acpi_handle handle, u16 status)
  {
  	u32 ost_status;
 
-	pci_dbg(pdev, "Sending EDR status :%x\n", status);
+	pci_dbg(pdev, "Sending EDR status: %#x\n", status);
 
  	ost_status =  PCI_DEVID(pdev->bus->number, pdev->devfn);
  	ost_status = (ost_status << 16) | status;

@@ -198,8 +197,7 @@ int acpi_send_edr_status(struct pci_dev *pdev,  acpi_handle handle, u16 status)
 
  	return 0;
  }
-
-#endif /* CONFIG_PCIE_DPC && CONFIG_ACPI */
+#endif /* CONFIG_PCIE_DPC */
 
  phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
  {

drivers/pci/pcie/Kconfig +5 -5

index 2db8a3109cb5..772b1f4cb19e 100644
@@ -143,10 +143,10 @@ config PCIE_BW
 
  config PCIE_EDR
  	bool "PCI Express Error Disconnect Recover support"
-	default n
  	depends on PCIE_DPC && ACPI
  	help
-	  This options adds Error Disconnect Recover support as specified
-	  in PCI firmware specification v3.2 Downstream Port Containment
-	  Related Enhancements ECN. Enable this if you want to support hybrid
-	  DPC model which uses both firmware and OS to implement DPC.
+	  This option adds Error Disconnect Recover support as specified
+	  in the Downstream Port Containment Related Enhancements ECN to
+	  the PCI Firmware Specification r3.2.  Enable this if you want to
+	  support hybrid DPC model which uses both firmware and OS to
+	  implement DPC.

drivers/pci/pcie/dpc.c +10 -11

index 49e020d46ea1..292ce4b69e7a 100644
@@ -79,7 +79,7 @@ void pci_save_dpc_state(struct pci_dev *dev)
 
  	/*
  	 * If DPC is controlled by firmware then save/restore tasks are also
-	 * controller by firmware. So skip rest of the function if DPC is
+	 * controlled by firmware. So skip rest of the function if DPC is
  	 * controlled by firmware.
  	 */
  	if (dpc->edr_enabled)

@@ -108,7 +108,7 @@ void pci_restore_dpc_state(struct pci_dev *dev)
 
  	/*
  	 * If DPC is controlled by firmware then save/restore tasks are also
-	 * controller by firmware. So skip rest of the function if DPC is
+	 * controlled by firmware. So skip rest of the function if DPC is
  	 * controlled by firmware.
  	 */
  	if (dpc->edr_enabled)

@@ -331,14 +331,13 @@ static void dpc_error_resume(struct pci_dev *dev)
  }
 
  #ifdef CONFIG_ACPI
-
  static void edr_handle_event(acpi_handle handle, u32 event, void *data)
  {
-	struct dpc_dev *dpc = (struct dpc_dev *) data;
+	struct dpc_dev *dpc = data;
  	struct pci_dev *pdev = dpc->dev->port;
  	u16 status;
 
-	pci_info(pdev, "ACPI event %x received\n", event);
+	pci_info(pdev, "ACPI event %#x received\n", event);
 
  	if (event != ACPI_NOTIFY_DISCONNECT_RECOVER)
  		return;

@@ -375,7 +374,7 @@ static void edr_handle_event(acpi_handle handle, u32 event, void *data)
  		pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,
  				     &status);
  		if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
-			pci_err(pdev, "Invalid DPC trigger %x\n", status);
+			pci_err(pdev, "Invalid DPC trigger %#010x\n", status);
  			goto edr_unlock;
  		}
  		dpc_process_error(dpc);

@@ -391,7 +390,7 @@ static void edr_handle_event(acpi_handle handle, u32 event, void *data)
  		status = 0x81;
 
  	/* Use ACPI handle of DPC event device for sending EDR status */
-	dpc = (struct dpc_dev *) data;
+	dpc = data;
 
  	acpi_send_edr_status(pdev, dpc->adev->handle, status);
 

@@ -400,7 +399,6 @@ static void edr_handle_event(acpi_handle handle, u32 event, void *data)
  done:
  	pci_dev_put(pdev);
  }
-
  #endif
 
  #define FLAG(x, y) (((x) & (y)) ? '+' : '-')

@@ -426,11 +424,12 @@ static int dpc_probe(struct pcie_device *dev)
  	mutex_init(&dpc->edr_lock);
 
  	/*
-	 * As per PCIe spec r5.0, implementation note titled "Determination
+	 * PCIe r5.0, sec 6.2.10, implementation note titled "Determination
  	 * of DPC Control", to avoid conflicts over whether platform
  	 * firmware or the operating system have control of DPC, it is
-	 * recommended that platform firmware and operating systems always link
-	 * the control of DPC to the control of Advanced Error Reporting.
+	 * recommended that platform firmware and operating systems always
+	 * link the control of DPC to the control of Advanced Error
+	 * Reporting.
  	 *
  	 * So use AER FF mode check API pcie_aer_get_firmware_first() to decide
  	 * whether DPC is controlled by software or firmware.

include/linux/pci.h +1 -1

index 0b7c63c7888d..d0739e90f4e7 100644
@@ -511,8 +511,8 @@ struct pci_host_bridge {
  	unsigned int	native_pme:1;		/* OS may use PCIe PME */
  	unsigned int	native_ltr:1;		/* OS may use PCIe LTR */
  	unsigned int	native_dpc:1;		/* OS may use PCIe DPC */
-
  	unsigned int	preserve_config:1;	/* Preserve FW resource setup */
+
  	/* Resource alignment requirements */
  	resource_size_t (*align_resource)(struct pci_dev *dev,
  			const struct resource *res,

drivers/pci/pci-acpi.c struct pci_dev *acpi_locate_dpc_port(struct pci_dev *pdev, acpi_handle handle) · line 155

Quoted 3 lines · Bjorn Helgaas

drivers/pci/pci-acpi.c +1 -2

-	obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 5,
-				EDR_PORT_LOCATE_DSM, NULL);
+	obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 5, EDR_PORT_LOCATE_DSM, NULL);

This line goes over 80 chars, do you still want to keep them in same line ?