dt-bindings: msm: disp: add yaml schemas for DPU and DSI bindings

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+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display Dpu dt properties.
+
+maintainers:
+ - Krishna Manikandan <[email protected]>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS and DPU are mentioned for SC7180 target.
+
+properties:
+ "mdss":
+  type: object
+  description: |
+   Node containing MDSS that encapsulated sub-blocks like DPU, DSI and DP
+   interfaces.
+
+  properties:
+   compatible:
+    items:
+     - const: qcom,sc7180-mdss
+   reg:
+    description: |
+     Physical base address and length of controller's registers.
+
+   reg-names:
+    description: |
+     Names for different register regions defined above. The required region
+     is mentioned below.
+    items:
+     - const: mdss
+
+   power-domains:
+    description: |
+     A power domain consumer specifier according to
+     Documentation/devicetree/bindings/power/power_domain.txt.
+
+   clocks:
+    description: |
+     List of clock specifiers for clocks needed by the device.
+
+   clock-names:
+    description: |
+     Device clock names in the same order as mentioned in clocks property.
+     The required clocks are mentioned below.
+    items:
+     - const: iface
+     - const: bus
+     - const: ahb
+     - const: core
+
+   interrupts:
+    description: |
+     Interrupt signal from MDSS.
+
+   interrupt-controller:
+    description: |
+     Identifies the node as an interrupt controller.
+
+   "#interrupt-cells":
+    description: |
+     Specifies the number of cells needed to encode an interrupt source.
+    const: 1
+
+   iommus:
+    description: |
+     Phandle of iommu device node.
+
+   "#address-cells":
+    description: |
+     Indicate how many cells (32 bits values) are needed to form the base
+     address part in the reg property.
+
+   "#size-cells":
+    description: |
+     Indicate how many cells (32 bits values) are needed to specify the size
+     part in the reg property.
+
+   ranges:
+    description: |
+     Parent bus address space is the same as the child bus address space.
+
+   interconnects :
+    description: |
+     Interconnect path specifier for MDSS according to
+     Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
+     2 paths corresponding to 2 AXI ports.
+
+   interconnect-names:
+    description: |
+     MDSS will have 2 port names to differentiate between the
+     2 interconnect paths defined with interconnect specifier.
+
+   properties:
+    description: |
+     Optional properties for MDSS.
+
+     assigned-clocks:
+      description: |
+       List of clock specifiers for clocks needing rate assignment.
+
+     assigned-clock-rates:
+      description: |
+       List of clock frequencies sorted in the same order as the assigned-clocks
+       property.
+
+   "mdp":
+    type: object
+    description: |
+     Node containing the properties of DPU.
+    properties:
+     compatible:
+      items:
+       - const: qcom,sc7180-dpu
+
+     reg:
+      description: |
+       Physical base address and length of controller's registers.
+
+     reg-names:
+      description: |
+       Register region names. The following regions are required.
+      items:
+        - const: mdp
+        - const: vbif
+
+     clocks:
+      description: |
+       List of clock specifiers for clocks needed by the device.
+
+     clock-names:
+      description: |
+       Device clock names, must be in same order as clocks property.
+       The following clocks are required. "bus" is an optional property
+       in sc7180 due to architecture change.
+      items:
+        - const: iface
+        - const: core
+        - const: vsync
+
+     interrupts:
+      description: |
+       Interrupt line from DPU to MDSS.
+
+     ports:
+      type: object
+      description: |
+       Contains the list of output ports from DPU device. These ports connect
+       to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+       Each output port contains an endpoint that describes how it is connected
+       to an external interface. These are described by the standard properties
+       documented in files mentioned below.
+
+       Documentation/devicetree/bindings/graph.txt
+       Documentation/devicetree/bindings/media/video-interfaces.txt
+
+      properties:
+       port0:
+        type: object
+        description: |
+         DPU_INTF1 (DSI1)
+       port1:
+        type: object
+        description: |
+         DPU_INTF2 (DSI2)
+
+     properties:
+      description: |
+       Optional properties for DPU.
+
+       assigned-clocks:
+        description: |
+         List of clock specifiers for clocks needing rate assignment.
+
+       assigned-clock-rates:
+        description: |
+         List of clock frequencies sorted in the same order as the
+         assigned-clocks property.
+
+       clock-names:
+        description: |
+         Optional device clocks, needed for accessing LUT blocks.
+        items:
+         - const: rot
+         - const: lut
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-controller
+ - iommus
+ - ports
+
+examples:
+- |
+    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,sdm845.h>
+    mdss: mdss@ae00000 {
+         compatible = "qcom,sc7180-mdss";
+         reg = <0xae00000 0x1000>;
+         reg-names = "mdss";
+         power-domains = <&clock_dispcc 0>;
+         clocks = <&gcc GCC_DISP_AHB_CLK>,
+                  <&gcc GCC_DISP_HF_AXI_CLK>,
+                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
+         clock-names = "iface", "gcc_bus", "core";
+         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+         assigned-clock-rates = <300000000>;
+
+         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+         interrupt-controller;
+         #interrupt-cells = <1>;
+
+         interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
+
+         interconnect-names = "mdp0-mem";
+
+         iommus = <&apps_smmu 0x800 0x2>;
+
+         #address-cells = <2>;
+         #size-cells = <2>;
+
+         mdss_mdp: mdp@ae01000 {
+                   compatible = "qcom,sc7180-dpu";
+                   reg = <0 0x0ae01000 0 0x8f000>,
+                         <0 0x0aeb0000 0 0x2008>,
+                         <0 0x0af03000 0 0x16>;
+                   reg-names = "mdp", "vbif", "disp_cc";
+
+                   clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                            <&dispcc DISP_CC_MDSS_ROT_CLK>,
+                            <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+                            <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                            <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                   clock-names = "iface", "rot", "lut", "core",
+                                                "vsync";
+                   assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                   assigned-clock-rates = <300000000>, <19200000>;
+                   interrupt-parent = <&mdss>;
+                   interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+                   ports {
+                           #address-cells = <1>;
+                           #size-cells = <0>;
+
+                           port@0 {
+                                   reg = <0>;
+                                   dpu_intf1_out: endpoint {
+                                                  remote-endpoint = <&dsi0_in>;
+                                   };
+                           };
+                   };
+         };
+    };
+...

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