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clk: agilex: add clock driver

PATCH Superseded Dinh Nguyen 2 participants 8 messages Mar 20, 2020 – Mar 31, 2020

Subsystems (3)
Device tree bindings Common clk Arm/socfpga clock framework support

v4 of 7 Superseded Latest is v7 →

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Dinh Nguyen

author maintainer
#0 lore raw

v4 cover clk: agilex: add clock driver

Hi,

This is version 4 of the patchset to add a clock driver to the Agilex platform.

The change from v3 is fixing the build of the dt-bindings file.

Thanks,

Dinh Nguyen (5):
clk: socfpga: stratix10: use new parent data scheme
clk: socfpga: remove clk_ops enable/disable methods
clk: socfpga: add const to _ops data structures
dt-bindings: documentation: add clock bindings information for Agilex
clk: socfpga: agilex: add clock driver for the Agilex platform

 .../bindings/clock/intel,agilex.yaml          |  36 ++
 drivers/clk/Makefile                          |   3 +-
 drivers/clk/socfpga/Makefile                  |   2 +
 drivers/clk/socfpga/clk-agilex.c              | 454 ++++++++++++++++++
 drivers/clk/socfpga/clk-gate-s10.c            |   5 +-
 drivers/clk/socfpga/clk-periph-s10.c          |  10 +-
 drivers/clk/socfpga/clk-pll-a10.c             |   4 +-
 drivers/clk/socfpga/clk-pll-s10.c             |  78 ++-
 drivers/clk/socfpga/clk-pll.c                 |   4 +-
 drivers/clk/socfpga/clk-s10.c                 | 160 ++++--
 drivers/clk/socfpga/stratix10-clk.h           |  10 +-
 include/dt-bindings/clock/agilex-clock.h      |  70 +++
 12 files changed, 784 insertions(+), 52 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
 create mode 100644 drivers/clk/socfpga/clk-agilex.c
 create mode 100644 include/dt-bindings/clock/agilex-clock.h
Signature · 1 line
2.25.1
author maintainer
#1 lore raw

PATCH v4 1/5 clk: socfpga: stratix10: use new parent data scheme

Convert, where possible, the stratix10 clock driver to the new parent data scheme by specifying the parent data for clocks that have multiple parents.

Signed-off-by Dinh Nguyen <[email protected]>

---
v4: no change
v3: no change
v2: add fw_name

---
 drivers/clk/socfpga/clk-gate-s10.c   |   5 +-
 drivers/clk/socfpga/clk-periph-s10.c |  10 +-
 drivers/clk/socfpga/clk-pll-s10.c    |   4 +-
 drivers/clk/socfpga/clk-s10.c        | 160 ++++++++++++++++++++++-----
 drivers/clk/socfpga/stratix10-clk.h  |   8 +-
 5 files changed, 146 insertions(+), 41 deletions(-)
drivers/clk/socfpga/clk-gate-s10.c +3 -2
index 8be4722f6064..083b2ec21fdd 100644
@@ -70,7 +70,6 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
 	struct clk *clk;
 	struct socfpga_gate_clk *socfpga_clk;
 	struct clk_init_data init;
-	const char * const *parent_names = clks->parent_names;
 	const char *parent_name = clks->parent_name;
 
 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);

@@ -108,7 +107,9 @@ struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __io
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names ? parent_names : &parent_name;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	if (init.parent_names == NULL)
+		init.parent_data = clks->parent_data;
 	socfpga_clk->hw.hw.init = &init;
 
 	clk = clk_register(NULL, &socfpga_clk->hw.hw);
drivers/clk/socfpga/clk-periph-s10.c +6 -4
index dd6d4056e9de..397b77b89b16 100644
@@ -81,7 +81,6 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
 	struct clk_init_data init;
 	const char *name = clks->name;
 	const char *parent_name = clks->parent_name;
-	const char * const *parent_names = clks->parent_names;
 
 	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
 	if (WARN_ON(!periph_clk))

@@ -94,7 +93,9 @@ struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names ? parent_names : &parent_name;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	if (init.parent_names == NULL)
+		init.parent_data = clks->parent_data;
 
 	periph_clk->hw.hw.init = &init;
 

@@ -114,7 +115,6 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
 	struct clk_init_data init;
 	const char *name = clks->name;
 	const char *parent_name = clks->parent_name;
-	const char * const *parent_names = clks->parent_names;
 
 	periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
 	if (WARN_ON(!periph_clk))

@@ -137,7 +137,9 @@ struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names ? parent_names : &parent_name;
+	init.parent_names = parent_name ? &parent_name : NULL;
+	if (init.parent_names == NULL)
+		init.parent_data = clks->parent_data;
 
 	periph_clk->hw.hw.init = &init;
drivers/clk/socfpga/clk-pll-s10.c +2 -2
index a301bb22f36c..bcd3f14e9145 100644
@@ -117,7 +117,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	struct socfpga_pll *pll_clk;
 	struct clk_init_data init;
 	const char *name = clks->name;
-	const char * const *parent_names = clks->parent_names;
 
 	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
 	if (WARN_ON(!pll_clk))

@@ -134,7 +133,8 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	init.flags = clks->flags;
 
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_names;
+	init.parent_names = NULL;
+	init.parent_data = clks->parent_data;
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
drivers/clk/socfpga/clk-s10.c +131 -29

166 lines not on this page · raw message

drivers/clk/socfpga/stratix10-clk.h +4 -4
index fcabef42249c..ffbd1fb2c8ef 100644
@@ -14,7 +14,7 @@ struct stratix10_clock_data {
 struct stratix10_pll_clock {
 	unsigned int		id;
 	const char		*name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		offset;

@@ -24,7 +24,7 @@ struct stratix10_perip_c_clock {
 	unsigned int		id;
 	const char		*name;
 	const char		*parent_name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		offset;

@@ -34,7 +34,7 @@ struct stratix10_perip_cnt_clock {
 	unsigned int		id;
 	const char		*name;
 	const char		*parent_name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		offset;

@@ -47,7 +47,7 @@ struct stratix10_gate_clock {
 	unsigned int		id;
 	const char		*name;
 	const char		*parent_name;
-	const char		*const *parent_names;
+	const struct clk_parent_data	*parent_data;
 	u8			num_parents;
 	unsigned long		flags;
 	unsigned long		gate_reg;
Signature · 1 line
2.25.1
author maintainer
#2 lore raw

PATCH v4 2/5 clk: socfpga: remove clk_ops enable/disable methods

In reply to Dinh Nguyen

From: Dinh Nguyen <[email protected]>

The enable/disable clock ops are already defined in the standard clock ops, so we don't need to assign them.

Signed-off-by Dinh Nguyen <[email protected]>

---
v4: no change
v3: introduced

---
 drivers/clk/socfpga/clk-pll-a10.c | 2 --
 drivers/clk/socfpga/clk-pll-s10.c | 2 --
 drivers/clk/socfpga/clk-pll.c     | 2 --
 3 files changed, 6 deletions(-)
drivers/clk/socfpga/clk-pll-a10.c +0 -2
index 3816fc04b274..6d9395106c0c 100644
@@ -102,8 +102,6 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {
drivers/clk/socfpga/clk-pll-s10.c +0 -2
index bcd3f14e9145..9faa80ff3b53 100644
@@ -138,8 +138,6 @@ struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {
drivers/clk/socfpga/clk-pll.c +0 -2
index dc65cc0fd3bd..a001641b2f42 100644
@@ -105,8 +105,6 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
 	pll_clk->hw.hw.init = &init;
 
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-	clk_pll_ops.enable = clk_gate_ops.enable;
-	clk_pll_ops.disable = clk_gate_ops.disable;
 
 	clk = clk_register(NULL, &pll_clk->hw.hw);
 	if (WARN_ON(IS_ERR(clk))) {
Signature · 1 line
2.25.1
author maintainer
#3 lore raw

PATCH v4 3/5 clk: socfpga: add const to _ops data structures

In reply to Dinh Nguyen

From: Dinh Nguyen <[email protected]>

All the static clk_ops data structure need a const.

Signed-off-by Dinh Nguyen <[email protected]>

---
v4: no change
v3: introduced

---
 drivers/clk/socfpga/clk-pll-a10.c | 2 +-
 drivers/clk/socfpga/clk-pll-s10.c | 4 ++--
 drivers/clk/socfpga/clk-pll.c     | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/socfpga/clk-pll-a10.c +1 -1
index 6d9395106c0c..db54f7d806a0 100644
@@ -58,7 +58,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
 		CLK_MGR_PLL_CLK_SRC_MASK;
 }
 
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 	.get_parent = clk_pll_get_parent,
 };
drivers/clk/socfpga/clk-pll-s10.c +2 -2
index 9faa80ff3b53..5c3e1ee44f6b 100644
@@ -98,13 +98,13 @@ static int clk_pll_prepare(struct clk_hw *hwclk)
 	return 0;
 }
 
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 	.get_parent = clk_pll_get_parent,
 	.prepare = clk_pll_prepare,
 };
 
-static struct clk_ops clk_boot_ops = {
+static const struct clk_ops clk_boot_ops = {
 	.recalc_rate = clk_boot_clk_recalc_rate,
 	.get_parent = clk_boot_get_parent,
 	.prepare = clk_pll_prepare,
drivers/clk/socfpga/clk-pll.c +1 -1
index a001641b2f42..e5fb786843f3 100644
@@ -65,7 +65,7 @@ static u8 clk_pll_get_parent(struct clk_hw *hwclk)
 			CLK_MGR_PLL_CLK_SRC_MASK;
 }
 
-static struct clk_ops clk_pll_ops = {
+static const struct clk_ops clk_pll_ops = {
 	.recalc_rate = clk_pll_recalc_rate,
 	.get_parent = clk_pll_get_parent,
 };
Signature · 1 line
2.25.1
author maintainer
#4 lore raw

PATCH v4 4/5 dt-bindings: documentation: add clock bindings information for Agilex

In reply to Dinh Nguyen

Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.

Signed-off-by Dinh Nguyen <[email protected]>

---
v4: really fix build error(comment formatting was wrong)
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37) renamed to intel,agilex.yaml
v2: convert original document to YAML

---
 .../bindings/clock/intel,agilex.yaml          | 36 ++++++++++
 include/dt-bindings/clock/agilex-clock.h      | 70 +++++++++++++++++++
 2 files changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
 create mode 100644 include/dt-bindings/clock/agilex-clock.h
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +36 -0
new file mode 100644
index 000000000000..5cf2ee5d6fcc
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex platform clock controller binding
+
+maintainers:
+  - Dinh Nguyen <[email protected]>
+
+description:
+  The Intel Agilex Clock controller is an integrated clock controller, which
+  generates and supplies to all modules.
+
+properties:
+  compatible:
+    const: intel,agilex-clkmgr
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+examples:
+  # Clock controller node:
+  - |
+    clkmgr: clock-controller@ffd10000 {
+      compatible = "intel,agilex-clkmgr";
+      reg = <0xffd10000 0x1000>;
+      #clock-cells = <1>;
+    };
+...
include/dt-bindings/clock/agilex-clock.h new file +70 -0

70 lines not on this page · raw message

Signature · 1 line
2.25.1
maintainer
#5 lore raw

Re: [PATCH 4/5] dt-bindings: documentation: add clock bindings information for Agilex

Quoted 24 lines · Dinh Nguyen

Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.

Signed-off-by Dinh Nguyen <[email protected]>

---
v4: really fix build error(comment formatting was wrong)
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37) renamed to intel,agilex.yaml
v2: convert original document to YAML

---
 .../bindings/clock/intel,agilex.yaml          | 36 ++++++++++
 include/dt-bindings/clock/agilex-clock.h      | 70 +++++++++++++++++++
 2 files changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
 create mode 100644 include/dt-bindings/clock/agilex-clock.h
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +0 -0
new file mode 100644
index 000000000000..5cf2ee5d6fcc

Documentation/devicetree/bindings/clock/intel,agilex.yaml line 1

Quoted 1 line
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +1 -0
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0

Dual license new bindings please:

(GPL-2.0-only OR BSD-2-Clause)

Quoted 15 lines
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +15 -0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex platform clock controller binding
+
+maintainers:
+  - Dinh Nguyen <[email protected]>
+
+description:
+  The Intel Agilex Clock controller is an integrated clock controller, which
+  generates and supplies to all modules.
+
+properties:

Documentation/devicetree/bindings/clock/intel,agilex.yaml line 26

Quoted 10 lines
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +10 -0
+  compatible:
+    const: intel,agilex-clkmgr
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'

Add:

additionalProperties: false

Documentation/devicetree/bindings/clock/intel,agilex.yaml line 34

Quoted 8 lines
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +8 -0
+
+examples:
+  # Clock controller node:
+  - |
+    clkmgr: clock-controller@ffd10000 {
+      compatible = "intel,agilex-clkmgr";
+      reg = <0xffd10000 0x1000>;
+      #clock-cells = <1>;

No clock inputs?

Quoted 81 lines
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +2 -0
+    };
+...
include/dt-bindings/clock/agilex-clock.h new file +70 -0
new file mode 100644
index 000000000000..f19cf8ccbdd2
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#ifndef __AGILEX_CLOCK_H
+#define __AGILEX_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX_OSC1			0
+#define AGILEX_CB_INTOSC_HS_DIV2_CLK	1
+#define AGILEX_CB_INTOSC_LS_CLK		2
+#define AGILEX_L4_SYS_FREE_CLK		3
+#define AGILEX_F2S_FREE_CLK		4
+
+/* PLL clocks */
+#define AGILEX_MAIN_PLL_CLK		5
+#define AGILEX_MAIN_PLL_C0_CLK		6
+#define AGILEX_MAIN_PLL_C1_CLK		7
+#define AGILEX_MAIN_PLL_C2_CLK		8
+#define AGILEX_MAIN_PLL_C3_CLK		9
+#define AGILEX_PERIPH_PLL_CLK		10
+#define AGILEX_PERIPH_PLL_C0_CLK	11
+#define AGILEX_PERIPH_PLL_C1_CLK	12
+#define AGILEX_PERIPH_PLL_C2_CLK	13
+#define AGILEX_PERIPH_PLL_C3_CLK	14
+#define AGILEX_MPU_FREE_CLK		15
+#define AGILEX_MPU_CCU_CLK		16
+#define AGILEX_BOOT_CLK			17
+
+/* fixed factor clocks */
+#define AGILEX_L3_MAIN_FREE_CLK		18
+#define AGILEX_NOC_FREE_CLK		19
+#define AGILEX_S2F_USR0_CLK		20
+#define AGILEX_NOC_CLK			21
+#define AGILEX_EMAC_A_FREE_CLK		22
+#define AGILEX_EMAC_B_FREE_CLK		23
+#define AGILEX_EMAC_PTP_FREE_CLK	24
+#define AGILEX_GPIO_DB_FREE_CLK		25
+#define AGILEX_SDMMC_FREE_CLK		26
+#define AGILEX_S2F_USER0_FREE_CLK	27
+#define AGILEX_S2F_USER1_FREE_CLK	28
+#define AGILEX_PSI_REF_FREE_CLK		29
+
+/* Gate clocks */
+#define AGILEX_MPU_CLK			30
+#define AGILEX_MPU_L2RAM_CLK		31
+#define AGILEX_MPU_PERIPH_CLK		32
+#define AGILEX_L4_MAIN_CLK		33
+#define AGILEX_L4_MP_CLK		34
+#define AGILEX_L4_SP_CLK		35
+#define AGILEX_CS_AT_CLK		36
+#define AGILEX_CS_TRACE_CLK		37
+#define AGILEX_CS_PDBG_CLK		38
+#define AGILEX_CS_TIMER_CLK		39
+#define AGILEX_S2F_USER0_CLK		40
+#define AGILEX_EMAC0_CLK		41
+#define AGILEX_EMAC1_CLK		43
+#define AGILEX_EMAC2_CLK		44
+#define AGILEX_EMAC_PTP_CLK		45
+#define AGILEX_GPIO_DB_CLK		46
+#define AGILEX_NAND_CLK			47
+#define AGILEX_PSI_REF_CLK		48
+#define AGILEX_S2F_USER1_CLK		49
+#define AGILEX_SDMMC_CLK		50
+#define AGILEX_SPI_M_CLK		51
+#define AGILEX_USB_CLK			52
+#define AGILEX_NUM_CLKS			53
+
+#endif	/* __AGILEX_CLOCK_H */
Signature · 1 line
2.25.1
author maintainer
#6 lore raw

Re: [PATCH 4/5] dt-bindings: documentation: add clock bindings information for Agilex

Quoted 29 lines · Rob Herring
Quoted 24 lines · Dinh Nguyen

Document the Agilex clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Agilex platform.

Signed-off-by Dinh Nguyen <[email protected]>

---
v4: really fix build error(comment formatting was wrong)
v3: address comments from Stephen Boyd
fix build error(tab removed in line 37) renamed to intel,agilex.yaml
v2: convert original document to YAML

---
 .../bindings/clock/intel,agilex.yaml          | 36 ++++++++++
 include/dt-bindings/clock/agilex-clock.h      | 70 +++++++++++++++++++
 2 files changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
 create mode 100644 include/dt-bindings/clock/agilex-clock.h
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +0 -0
new file mode 100644
index 000000000000..5cf2ee5d6fcc

Documentation/devicetree/bindings/clock/intel,agilex.yaml line 1

Quoted 1 line
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +1 -0
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0

Dual license new bindings please:

Quoted 2 lines

(GPL-2.0-only OR BSD-2-Clause)

Okay...

Quoted 28 lines
Quoted 15 lines
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +15 -0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel SoCFPGA Agilex platform clock controller binding
+
+maintainers:
+  - Dinh Nguyen <[email protected]>
+
+description:
+  The Intel Agilex Clock controller is an integrated clock controller, which
+  generates and supplies to all modules.
+
+properties:

Documentation/devicetree/bindings/clock/intel,agilex.yaml line 26

Quoted 10 lines
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +10 -0
+  compatible:
+    const: intel,agilex-clkmgr
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'

Add:

Quoted 2 lines

additionalProperties: false

Okay..

Quoted 11 lines

Documentation/devicetree/bindings/clock/intel,agilex.yaml line 34

Quoted 8 lines
Documentation/devicetree/bindings/clock/intel,agilex.yaml new file +8 -0
+
+examples:
+  # Clock controller node:
+  - |
+    clkmgr: clock-controller@ffd10000 {
+      compatible = "intel,agilex-clkmgr";
+      reg = <0xffd10000 0x1000>;
+      #clock-cells = <1>;

No clock inputs?

The clock controller is fed the onboard OSC1. So yes, I'll update it.

Dinh

author maintainer
#7 lore raw

PATCH v4 5/5 clk: socfpga: agilex: add clock driver for the Agilex platform

In reply to Dinh Nguyen

For the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver.

Signed-off-by Dinh Nguyen <[email protected]>

---
v4: no changes
v3: Address Stephen Boyd's comments
v2: update to use clk_parent_data

---
 drivers/clk/Makefile                |   3 +-
 drivers/clk/socfpga/Makefile        |   2 +
 drivers/clk/socfpga/clk-agilex.c    | 454 ++++++++++++++++++++++++++++
 drivers/clk/socfpga/clk-pll-s10.c   |  68 +++++
 drivers/clk/socfpga/stratix10-clk.h |   2 +
 5 files changed, 528 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/socfpga/clk-agilex.c
drivers/clk/Makefile +2 -1
index f4169cc2fd31..a178e4b6001f 100644
@@ -104,10 +104,11 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_CLK_SIFIVE)		+= sifive/
 obj-$(CONFIG_ARCH_SIRF)			+= sirf/
 obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/
+obj-$(CONFIG_ARCH_AGILEX)		+= socfpga/
+obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/
 obj-$(CONFIG_ARCH_SPRD)			+= sprd/
 obj-$(CONFIG_ARCH_STI)			+= st/
-obj-$(CONFIG_ARCH_STRATIX10)		+= socfpga/
 obj-$(CONFIG_ARCH_SUNXI)		+= sunxi/
 obj-$(CONFIG_SUNXI_CCU)			+= sunxi-ng/
 obj-$(CONFIG_ARCH_TEGRA)		+= tegra/
drivers/clk/socfpga/Makefile +2 -0
index ce5aa7802eb8..bf736f8d201a 100644
@@ -3,3 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
 obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
 obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
 obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
+obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
drivers/clk/socfpga/clk-agilex.c new file +454 -0

454 lines not on this page · raw message

drivers/clk/socfpga/clk-pll-s10.c +68 -0

91 lines not on this page · raw message

drivers/clk/socfpga/stratix10-clk.h +2 -0
index ffbd1fb2c8ef..f9d5d724c694 100644
@@ -62,6 +62,8 @@ struct stratix10_gate_clock {
 
 struct clk *s10_register_pll(const struct stratix10_pll_clock *,
 			     void __iomem *);
+struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
+				void __iomem *);
 struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
 				void __iomem *);
 struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
Signature · 1 line
2.25.1