PCI: IPQ6018 platform support

PATCH Superseded Baruch Siach 5 participants 16 messages Feb 7, 2022 – Jun 9, 2022

Subsystems (6)

Arm Qualcomm mailing list PCI Tegra architecture support PCI native host bridge and endpoint drivers +2 more subsystems

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Baruch Siach

author

2022-02-07 14:57 UTC #0 lore raw

v6 cover PCI: IPQ6018 platform support

This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().

Tested on IPQ6010 based hardware.

Changes in v6:

* Drop DT patch applied to the qcom tree

* Normalize driver changes subject line

* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros

* Drop a vague comment about ASPM configuration

* Add a comment about the source of delay periods

Changes in v5:

* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)

Changes in v4:

* Drop applied DT bits

* Add max-link-speed that was missing from the applied v2 patch

* Rebase the driver on v5.16-rc3

Changes in v3:

* Drop applied patches

* Rely on generic code for speed setup

* Drop unused macros

* Formatting fixes

Changes in v2:

* Add patch moving GEN3_RELATED macros to a common header

* Drop ATU configuration from pcie-qcom

* Remove local definition of common registers

* Use bulk clk and reset APIs

* Remove msi-parent from device-tree

Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support

 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

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Baruch Siach

author

2022-02-07 14:58 UTC #1 lore raw

PATCH v6 1/3 PCI: dwc: tegra: move GEN3_RELATED DBI register to common header

From: Baruch Siach <[email protected]>

These are common dwc macros that will be used for other platforms.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Baruch Siach <[email protected]>

---
 drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
 drivers/pci/controller/dwc/pcie-tegra194.c   | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

drivers/pci/controller/dwc/pcie-designware.h +6 -0

index 7d6e9b7576be..ea87809ee298 100644
@@ -74,6 +74,12 @@
 #define PCIE_MSI_INTR0_MASK		0x82C
 #define PCIE_MSI_INTR0_STATUS		0x830
 
+#define GEN3_RELATED_OFF			0x890
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)
+
 #define PCIE_PORT_MULTI_LANE_CTRL	0x8C0
 #define PORT_MLTI_UPCFG_SUPPORT		BIT(7)

drivers/pci/controller/dwc/pcie-tegra194.c +0 -6

index b1b5f836a806..74bf66d9afeb 100644
@@ -193,12 +193,6 @@
 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK	GENMASK(23, 8)
 #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK	GENMASK(3, 0)
 
-#define GEN3_RELATED_OFF			0x890
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)
-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)
-
 #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT	0x8D0
 #define AMBA_ERROR_RESPONSE_CRS_SHIFT		3
 #define AMBA_ERROR_RESPONSE_CRS_MASK		GENMASK(1, 0)

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Baruch Siach

author

2022-02-07 14:59 UTC #2 lore raw

PATCH v6 2/3 PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

In reply to Baruch Siach

From: Baruch Siach <[email protected]>

The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning.

Signed-off-by Baruch Siach <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

drivers/pci/controller/dwc/pcie-qcom.c +13 -2

index c19cd506ed3f..01e58b057d2a 100644
@@ -69,7 +69,18 @@
 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
 #define CFG_BRIDGE_SB_INIT			BIT(0)
 
-#define PCIE_CAP_LINK1_VAL			0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000
+#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
+						PCI_EXP_SLTCAP_PCP | \
+						PCI_EXP_SLTCAP_MRLSP | \
+						PCI_EXP_SLTCAP_AIP | \
+						PCI_EXP_SLTCAP_PIP | \
+						PCI_EXP_SLTCAP_HPS | \
+						PCI_EXP_SLTCAP_HPC | \
+						PCI_EXP_SLTCAP_EIP | \
+						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
 
 #define PCIE20_PARF_Q2A_FLUSH			0x1AC

@@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 
 	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
 	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
 	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
 	val &= ~PCI_EXP_LNKCAP_ASPMS;

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Pali Rohár

2022-06-08 23:00 UTC #3 lore raw

Re: [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

Quoted 16 lines · On Monday 07 February 2022 16:51:25 Baruch Siach wrote:

From: Baruch Siach <[email protected]>
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning.
Signed-off-by Baruch Siach <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index c19cd506ed3f..01e58b057d2a 100644

drivers/pci/controller/dwc/pcie-qcom.c line 73

Quoted 6 lines

drivers/pci/controller/dwc/pcie-qcom.c +2 -1

@@ -69,7 +69,18 @@
 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
 #define CFG_BRIDGE_SB_INIT			BIT(0)
 
-#define PCIE_CAP_LINK1_VAL			0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000

Hello!

Please do not use hardcoded values for slot power limit value and scale numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS for composing mask:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79

And the important information: Slot power limit is board specific and depends on how power supply and power regulators are designed. So slot power limit **cannot** be hardcoded in driver. Instead this value should be read from device tree file for the current board.

There is a new kernel function of_pci_get_slot_power_limit() which reads it and compose PCIe slot power limit value and scale numbers. See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631

Quoted 25 lines

drivers/pci/controller/dwc/pcie-qcom.c +11 -1

+#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
+						PCI_EXP_SLTCAP_PCP | \
+						PCI_EXP_SLTCAP_MRLSP | \
+						PCI_EXP_SLTCAP_AIP | \
+						PCI_EXP_SLTCAP_PIP | \
+						PCI_EXP_SLTCAP_HPS | \
+						PCI_EXP_SLTCAP_HPC | \
+						PCI_EXP_SLTCAP_EIP | \
+						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
 
 #define PCIE20_PARF_Q2A_FLUSH			0x1AC

@@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 
 	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
 	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
 	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
 	val &= ~PCI_EXP_LNKCAP_ASPMS;

Signature · 1 line

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Baruch Siach

author

2022-06-09 03:44 UTC #4 lore raw

Re: [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

Hi Pali,

Quoted 26 lines · Pali Rohár

Quoted 16 lines · On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
From: Baruch Siach <[email protected]>
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning.
Signed-off-by Baruch Siach <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index c19cd506ed3f..01e58b057d2a 100644
drivers/pci/controller/dwc/pcie-qcom.c line 73
Quoted 6 lines
drivers/pci/controller/dwc/pcie-qcom.c +2 -1
@@ -69,7 +69,18 @@
 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
 #define CFG_BRIDGE_SB_INIT			BIT(0)
 
-#define PCIE_CAP_LINK1_VAL			0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000
Hello!

Quoted 6 lines

Please do not use hardcoded values for slot power limit value and scale numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS for composing mask:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79

Thanks for the tip.

Quoted 8 lines

And the important information: Slot power limit is board specific and depends on how power supply and power regulators are designed. So slot power limit **cannot** be hardcoded in driver. Instead this value should be read from device tree file for the current board.
There is a new kernel function of_pci_get_slot_power_limit() which reads it and compose PCIe slot power limit value and scale numbers. See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631

The 'slot-power-limit-milliwatt' property appears to be undocumented as of v5.19-rc1.

This patch should make no functional change. I guess we should keep the default hard-coded driver value for compatibility with existing DTs with no 'slot-power-limit-milliwatt'.

Thanks,
baruch

Quoted 25 lines

drivers/pci/controller/dwc/pcie-qcom.c +11 -1

+#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
+						PCI_EXP_SLTCAP_PCP | \
+						PCI_EXP_SLTCAP_MRLSP | \
+						PCI_EXP_SLTCAP_AIP | \
+						PCI_EXP_SLTCAP_PIP | \
+						PCI_EXP_SLTCAP_HPS | \
+						PCI_EXP_SLTCAP_HPC | \
+						PCI_EXP_SLTCAP_EIP | \
+						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
 
 #define PCIE20_PARF_Q2A_FLUSH			0x1AC

@@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 
 	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
 	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
 	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
 	val &= ~PCI_EXP_LNKCAP_ASPMS;

Signature · 1 line

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Signature · 3 lines

                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -

Pali Rohár

2022-06-09 08:51 UTC #5 lore raw

Re: [PATCH v6 2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

Quoted 43 lines · On Thursday 09 June 2022 06:27:34 Baruch Siach wrote:

Hi Pali,
Quoted 26 lines · Pali Rohár
Quoted 16 lines · On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
From: Baruch Siach <[email protected]>
The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better describe its meaning.
Signed-off-by Baruch Siach <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index c19cd506ed3f..01e58b057d2a 100644
drivers/pci/controller/dwc/pcie-qcom.c line 73
Quoted 6 lines
drivers/pci/controller/dwc/pcie-qcom.c +2 -1
@@ -69,7 +69,18 @@
 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
 #define CFG_BRIDGE_SB_INIT			BIT(0)
 
-#define PCIE_CAP_LINK1_VAL			0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000
Hello!
Quoted 6 lines
Please do not use hardcoded values for slot power limit value and scale numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS for composing mask:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79
Thanks for the tip.
Quoted 5 lines
And the important information: Slot power limit is board specific and depends on how power supply and power regulators are designed. So slot power limit **cannot** be hardcoded in driver. Instead this value should be read from device tree file for the current board.

Quoted 6 lines

Quoted 3 lines
There is a new kernel function of_pci_get_slot_power_limit() which reads it and compose PCIe slot power limit value and scale numbers. See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631
The 'slot-power-limit-milliwatt' property appears to be undocumented as of v5.19-rc1.

slot-power-limit-milliwatt is already documented in DT scheme pci-bus, see:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus.yaml

Quoted 38 lines

This patch should make no functional change. I guess we should keep the default hard-coded driver value for compatibility with existing DTs with no 'slot-power-limit-milliwatt'.

Thanks,
baruch

Quoted 25 lines

drivers/pci/controller/dwc/pcie-qcom.c +11 -1

+#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
+						PCI_EXP_SLTCAP_PCP | \
+						PCI_EXP_SLTCAP_MRLSP | \
+						PCI_EXP_SLTCAP_AIP | \
+						PCI_EXP_SLTCAP_PIP | \
+						PCI_EXP_SLTCAP_HPS | \
+						PCI_EXP_SLTCAP_HPC | \
+						PCI_EXP_SLTCAP_EIP | \
+						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
 
 #define PCIE20_PARF_Q2A_FLUSH			0x1AC

@@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 
 	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
 	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
 	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
 	val &= ~PCI_EXP_LNKCAP_ASPMS;

Signature · 1 line

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Signature · 3 lines

                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -

Baruch Siach

author

2022-02-07 15:00 UTC #6 lore raw

PATCH v6 3/3 PCI: qcom: Add IPQ60xx support

In reply to Baruch Siach

From: Selvam Sathappan Periakaruppan <[email protected]>

IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform.

The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0).

Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on().

[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/

Signed-off-by Selvam Sathappan Periakaruppan <[email protected]>

Signed-off-by Baruch Siach <[email protected]>

---
v6:

Address Bjorn Helgaas comments:

* Rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL

* Drop a vague comment about ASPM configuration

* Add a comment about the source of delay periods

v5:

* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)

v4:

* Rebase on v5.16-rc1

v3:
* Drop speed setup; rely on generic code (Rob Herring)

* Drop unused CLK_RATE macros (Bjorn Helgaas)

* Minor formatting fixes (Bjorn Helgaas)

* Add reference to downstream Codeaurora kernel tree (Bjorn Helgaas)

v2:
* Drop ATU configuration; rely on common code instead

* Use more common register macros

* Use bulk clk and reset APIs

---
 drivers/pci/controller/dwc/pcie-designware.h |   1 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 140 +++++++++++++++++++
 2 files changed, 141 insertions(+)

drivers/pci/controller/dwc/pcie-designware.h +1 -0

index ea87809ee298..279c3778a13b 100644
@@ -76,6 +76,7 @@
 
 #define GEN3_RELATED_OFF			0x890
 #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS	BIT(13)
 #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
 #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)

drivers/pci/controller/dwc/pcie-qcom.c +140 -0

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Lorenzo Pieralisi

2022-02-11 16:07 UTC #7 lore raw

In reply to Baruch Siach

Quoted 58 lines · Baruch Siach

This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v6:
* Drop DT patch applied to the qcom tree
* Normalize driver changes subject line
* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
Changes in v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
Changes in v4:
* Drop applied DT bits
* Add max-link-speed that was missing from the applied v2 patch
* Rebase the driver on v5.16-rc3
Changes in v3:
* Drop applied patches
* Rely on generic code for speed setup
* Drop unused macros
* Formatting fixes
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

Quoted 7 lines

Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support

 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

Bjorn, Andy,

Can you ACK please if this series is ready to be merged ?

Thanks,
Lorenzo

Robert Marko

2022-03-15 13:05 UTC #8 lore raw

Quoted 63 lines · Lorenzo Pieralisi

Quoted 61 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v6:
* Drop DT patch applied to the qcom tree
* Normalize driver changes subject line
* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
Changes in v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
Changes in v4:
* Drop applied DT bits
* Add max-link-speed that was missing from the applied v2 patch
* Rebase the driver on v5.16-rc3
Changes in v3:
* Drop applied patches
* Rely on generic code for speed setup
* Drop unused macros
* Formatting fixes
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support

Quoted 8 lines

Quoted 4 lines

 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

Bjorn, Andy,

Can you ACK please if this series is ready to be merged ?

Hi,
This would also help the IPQ8074 which has the same controller for the Gen3 port.

I have been using this for OpenWrt for a while and it works.

Regards,
Robert

Quoted 3 lines

Thanks,
Lorenzo

Signature · 7 lines

Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: [email protected]
Web: www.sartura.hr

Baruch Siach

author

2022-03-15 13:30 UTC #9 lore raw

Hi Robert,

Quoted 10 lines · Robert Marko

Quoted 8 lines · Lorenzo Pieralisi
Quoted 6 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.

[snip]

Quoted 13 lines

Quoted 13 lines
Quoted 12 lines
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support
 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

Quoted 8 lines

Quoted 3 lines
Bjorn, Andy,
Can you ACK please if this series is ready to be merged ?
This would also help the IPQ8074 which has the same controller for the Gen3 port.
I have been using this for OpenWrt for a while and it works.

Thanks for your test report.

It would be nice to have a formal Tested-by for the pcie-qcom.c patch. It might help to push the patch forward.

Can you also share the device-tree part? I'll add it to this series in case it needs a respin.

Thanks,
baruch

Signature · 3 lines

                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -

Robert Marko

2022-03-15 13:41 UTC #10 lore raw

Quoted 35 lines · Baruch Siach

Hi Robert,
Quoted 10 lines · Robert Marko
Quoted 8 lines · Lorenzo Pieralisi
Quoted 6 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
[snip]
Quoted 20 lines
Quoted 8 lines
Quoted 8 lines
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support
Quoted 8 lines
Quoted 4 lines
 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)
Bjorn, Andy,
Can you ACK please if this series is ready to be merged ?
This would also help the IPQ8074 which has the same controller for the Gen3 port.

Quoted 6 lines

Quoted 1 line
I have been using this for OpenWrt for a while and it works.
Thanks for your test report.
It would be nice to have a formal Tested-by for the pcie-qcom.c patch. It might help to push the patch forward.

Hi Baruch, I am not sure whether a Tested-by would be applicable here as its a different platform, that is why I left it out.

Quoted 3 lines

Can you also share the device-tree part? I'll add it to this series in case it needs a respin.

Currently, the IPQ8074 DTS regarding QMP PCI PHY-s and PCI controllers is incorrect, it was all based on v1 of the SoC which is not supported at all. Gen3 QMP PHY support is currently missing for IPQ8074 and I am working on upstreaming that and will fix up all of the PCI-related stuff in the DTS after that.

So, I would prefer to keep those separate and let this series get merged, especially
since the DTS part has already been merged.

Regards,
Robert

Quoted 8 lines

Thanks,
baruch
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -

Signature · 7 lines

Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: [email protected]
Web: www.sartura.hr

Lorenzo Pieralisi

2022-04-12 16:13 UTC #11 lore raw

In reply to Baruch Siach

Quoted 58 lines · Baruch Siach

This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v6:
* Drop DT patch applied to the qcom tree
* Normalize driver changes subject line
* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
Changes in v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
Changes in v4:
* Drop applied DT bits
* Add max-link-speed that was missing from the applied v2 patch
* Rebase the driver on v5.16-rc3
Changes in v3:
* Drop applied patches
* Rely on generic code for speed setup
* Drop unused macros
* Formatting fixes
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

Quoted 7 lines

Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support

 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

Hi Bjorn, Andy,

any feedback on this series please ?

Thanks,
Lorenzo

Lorenzo Pieralisi

2022-05-11 14:03 UTC #12 lore raw

Quoted 62 lines · Lorenzo Pieralisi

Quoted 61 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v6:
* Drop DT patch applied to the qcom tree
* Normalize driver changes subject line
* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
Changes in v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
Changes in v4:
* Drop applied DT bits
* Add max-link-speed that was missing from the applied v2 patch
* Rebase the driver on v5.16-rc3
Changes in v3:
* Drop applied patches
* Rely on generic code for speed setup
* Drop unused macros
* Formatting fixes
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support

Quoted 8 lines

Quoted 4 lines

 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

Hi Bjorn, Andy,

any feedback on this series please ?

Any feedback on these patches please ?

Thanks,
Lorenzo

Robert Marko

Tested-by

2022-06-07 13:12 UTC #13 lore raw

Quoted 69 lines · Lorenzo Pieralisi

Quoted 67 lines · Lorenzo Pieralisi
Quoted 65 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v6:
* Drop DT patch applied to the qcom tree
* Normalize driver changes subject line
* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
Changes in v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
Changes in v4:
* Drop applied DT bits
* Add max-link-speed that was missing from the applied v2 patch
* Rebase the driver on v5.16-rc3
Changes in v3:
* Drop applied patches
* Rely on generic code for speed setup
* Drop unused macros
* Formatting fixes
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support
 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

Quoted 5 lines

Quoted 3 lines
Hi Bjorn, Andy,
any feedback on this series please ?
Any feedback on these patches please ?

Finally dug the CP01, and for me, it works, so:

Tested-by Robert Marko <[email protected]>

Can we finally get this merged or at least looked at. IPQ8074 will also benefit from this.

Regards,
Robert

Quoted 3 lines

Thanks,
Lorenzo

Signature · 7 lines

Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: [email protected]
Web: www.sartura.hr

Bjorn Helgaas

2022-06-08 20:24 UTC #14 lore raw

[+cc Stanimir, beginning of thread at
https://lore.kernel.org/r/[email protected]]

Quoted 71 lines · Robert Marko

Quoted 69 lines · Lorenzo Pieralisi
Quoted 67 lines · Lorenzo Pieralisi
Quoted 65 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v6:
* Drop DT patch applied to the qcom tree
* Normalize driver changes subject line
* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
Changes in v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
Changes in v4:
* Drop applied DT bits
* Add max-link-speed that was missing from the applied v2 patch
* Rebase the driver on v5.16-rc3
Changes in v3:
* Drop applied patches
* Rely on generic code for speed setup
* Drop unused macros
* Formatting fixes
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support
 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)

Quoted 8 lines

Quoted 5 lines
Quoted 3 lines
Hi Bjorn, Andy,
any feedback on this series please ?
Any feedback on these patches please ?
Finally dug the CP01, and for me, it works, so:
Tested-by Robert Marko <[email protected]>

This mainly affects pcie-qcom.c, so it looks like Stanimir should have been copied on this, but wasn't. Please include him on the next iteration.

This will also need to be updated to apply on v5.19-rc1:

03:21:47 ~/linux (next)$ git checkout -b wip/baruch-ipq6018-v6 v5.19-rc1
Switched to a new branch 'wip/baruch-ipq6018-v6'
03:21:55 ~/linux (wip/baruch-ipq6018-v6)$ git am m/v6_20220207_baruch_pci_ipq6018_platform_support.mbx
Applying: PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
Applying: PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Applying: PCI: qcom: Add IPQ60xx support
error: patch failed: drivers/pci/controller/dwc/pcie-qcom.c:1531
error: drivers/pci/controller/dwc/pcie-qcom.c: patch does not apply
Patch failed at 0003 PCI: qcom: Add IPQ60xx support

Baruch Siach

author

2022-06-09 13:22 UTC #15 lore raw

Hi Bjorn,

[ Changed codeaurora.com addresses to their quicinc.com equivalents ]

Quoted 79 lines · Bjorn Helgaas

[+cc Stanimir, beginning of thread at
https://lore.kernel.org/r/[email protected]]
Quoted 75 lines · Robert Marko
Quoted 73 lines · Lorenzo Pieralisi
Quoted 70 lines · Lorenzo Pieralisi
Quoted 58 lines · Baruch Siach
This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on().
Tested on IPQ6010 based hardware.
Changes in v6:
* Drop DT patch applied to the qcom tree
* Normalize driver changes subject line
* Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros
* Drop a vague comment about ASPM configuration
* Add a comment about the source of delay periods
Changes in v5:
* Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson)
Changes in v4:
* Drop applied DT bits
* Add max-link-speed that was missing from the applied v2 patch
* Rebase the driver on v5.16-rc3
Changes in v3:
* Drop applied patches
* Rely on generic code for speed setup
* Drop unused macros
* Formatting fixes
Changes in v2:
* Add patch moving GEN3_RELATED macros to a common header
* Drop ATU configuration from pcie-qcom
* Remove local definition of common registers
* Use bulk clk and reset APIs
* Remove msi-parent from device-tree
Baruch Siach (2):
PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Quoted 7 lines
Selvam Sathappan Periakaruppan (1):
PCI: qcom: Add IPQ60xx support
 drivers/pci/controller/dwc/pcie-designware.h |   7 +
 drivers/pci/controller/dwc/pcie-qcom.c       | 155 ++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-tegra194.c   |   6 -
 3 files changed, 160 insertions(+), 8 deletions(-)
Hi Bjorn, Andy,
any feedback on this series please ?

Quoted 8 lines

Quoted 4 lines
Quoted 1 line
Any feedback on these patches please ?
Finally dug the CP01, and for me, it works, so:
Tested-by Robert Marko <[email protected]>
This mainly affects pcie-qcom.c, so it looks like Stanimir should have been copied on this, but wasn't. Please include him on the next iteration.

I somehow missed the pcie-qcom.c standalone entry in MAINTAINERS because the same file also appears on the general qcom entry. I'll add him on v7. Hopefully that will improve the fortune of this series.

Quoted 11 lines

This will also need to be updated to apply on v5.19-rc1:
03:21:47 ~/linux (next)$ git checkout -b wip/baruch-ipq6018-v6 v5.19-rc1
Switched to a new branch 'wip/baruch-ipq6018-v6'
03:21:55 ~/linux (wip/baruch-ipq6018-v6)$ git am m/v6_20220207_baruch_pci_ipq6018_platform_support.mbx
Applying: PCI: dwc: tegra: move GEN3_RELATED DBI register to common header
Applying: PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
Applying: PCI: qcom: Add IPQ60xx support
error: patch failed: drivers/pci/controller/dwc/pcie-qcom.c:1531
error: drivers/pci/controller/dwc/pcie-qcom.c: patch does not apply
Patch failed at 0003 PCI: qcom: Add IPQ60xx support

I'll rebase on v5.19-rc1.

baruch

Signature · 3 lines

                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - [email protected] - tel: +972.52.368.4656, http://www.tkos.co.il -