Risc-V Svinval support
v2 cover Risc-V Svinval support
This patch adds support for the Svinval extension as defined in the Risc V Privileged specification. This patchset depends on:
https://patchwork.kernel.org/project/linux-riscv/list/?series=632984
The feature was tested with qemu from latest master branch with following additional patch:
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00142.html
Changes in V2:
- Rebased on 5.18-rc3
- update riscv_fill_hwcap to probe Svinval extension
Mayuresh Chitale (2):
riscv: enum for svinval extension
riscv: mm: use svinval instructions instead of sfence.vma
arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/tlbflush.h | 12 ++++ arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- 6 files changed, 126 insertions(+), 6 deletions(-)
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2.17.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v2 1/2 riscv: enum for svinval extension
Similar to the other ISA extensions, this patch enables callers to check for the presence for the svinval extension.
--- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 3 insertions(+)
arch/riscv/include/asm/hwcap.h +1 -0
@@ -52,6 +52,7 @@ extern unsigned long elf_hwcap;*/ enum riscv_isa_ext_id {RISCV_ISA_EXT_SSCOFPMF =RISCV_ISA_EXT_BASE , +RISCV_ISA_EXT_SVINVAL ,RISCV_ISA_EXT_ID_MAX =RISCV_ISA_EXT_MAX , };
arch/riscv/kernel/cpu.c +1 -0
@@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node)*/ static struct riscv_isa_ext_data isa_ext_arr[] = {__RISCV_ISA_EXT_DATA (sscofpmf,RISCV_ISA_EXT_SSCOFPMF ), +__RISCV_ISA_EXT_DATA (svinval,RISCV_ISA_EXT_SVINVAL ),__RISCV_ISA_EXT_DATA ("" ,RISCV_ISA_EXT_MAX ), };
arch/riscv/kernel/cpufeature.c +1 -0
@@ -192,6 +192,7 @@ void __init riscv_fill_hwcap(void)set_bit (*ext -'a' , this_isa); }else {SET_ISA_EXT_MAP ("sscofpmf" ,RISCV_ISA_EXT_SSCOFPMF ); +SET_ISA_EXT_MAP ("svinval" ,RISCV_ISA_EXT_SVINVAL ); }#undef SET_ISA_EXT_MAP }
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2.17.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
RFC PATCH v2 2/2 riscv: mm: use svinval instructions instead of sfence.vma
In reply to Mayuresh ChitaleWhen svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma:
sfence.w.inval
svinval.vma
.
.
svinval.vma
sfence.inval.ir
The maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to PTRS_PER_PTE. This is required to avoid soft lockups and the approach is similar to that used in arm64.
--- arch/riscv/include/asm/tlbflush.h | 12 ++++ arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- 3 files changed, 123 insertions(+), 6 deletions(-)
arch/riscv/include/asm/tlbflush.h +12 -0
@@ -22,6 +22,18 @@ static inline void local_flush_tlb_page(unsigned long addr) {ALT_FLUSH_TLB_PAGE (__asm__ __volatile__ ("sfence.vma %0" : :"r" (addr) :"memory" )); } + +void riscv_tlbflush_init (void ); +void __riscv_sfence_w_inval (void ); +void __riscv_sfence_inval_ir (void ); +void __riscv_sinval_vma (unsigned long addr); +void __riscv_sinval_vma_asid (unsigned long addr,unsigned long asid); + +/* Check if we can use sinval for tlb flush */ +DECLARE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +#define riscv_use_flush_tlb_svinval () \ + static_branch_unlikely(&riscv_flush_tlb_svinval) +#else /* CONFIG_MMU */ #define local_flush_tlb_all () do { } while (0)#define local_flush_tlb_page (addr) do { } while (0)
arch/riscv/kernel/setup.c +1 -0
@@ -295,6 +295,7 @@ void __init setup_arch(char **cmdline_p)#endif riscv_fill_hwcap (); +riscv_tlbflush_init (); }static int __init topology_init (void )
arch/riscv/mm/tlbflush.c +110 -6
146 lines not on this page · raw message
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2.17.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Palmer Dabbelt
maintainerRe: [RFC PATCH v2 2/2] riscv: mm: use svinval instructions instead of sfence.vma
Quoted 181 lines · On Sun, 24 Apr 2022 02:02:16 PDT (-0700), [email protected] wrote:
When svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma:
sfence.w.inval
svinval.vma
.
.
svinval.vma
sfence.inval.irThe maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to
PTRS_PER_PTE. This is required to avoid soft lockups and the approach is similar to that used in arm64.Signed-off-by Mayuresh Chitale <[email protected]>--- arch/riscv/include/asm/tlbflush.h | 12 ++++ arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- 3 files changed, 123 insertions(+), 6 deletions(-)arch/riscv/include/asm/tlbflush.h +12
-0@@ -22,6 +22,18 @@ static inline void local_flush_tlb_page(unsigned long addr) {ALT_FLUSH_TLB_PAGE (__asm__ __volatile__ ("sfence.vma %0" : :"r" (addr) :"memory" )); } + +void riscv_tlbflush_init (void ); +void __riscv_sfence_w_inval (void ); +void __riscv_sfence_inval_ir (void ); +void __riscv_sinval_vma (unsigned long addr); +void __riscv_sinval_vma_asid (unsigned long addr,unsigned long asid); + +/* Check if we can use sinval for tlb flush */ +DECLARE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +#define riscv_use_flush_tlb_svinval () \ + static_branch_unlikely(&riscv_flush_tlb_svinval) +#else /* CONFIG_MMU */ #define local_flush_tlb_all () do { } while (0)#define local_flush_tlb_page (addr) do { } while (0)arch/riscv/kernel/setup.c +1
-0@@ -295,6 +295,7 @@ void __init setup_arch(char **cmdline_p)#endif riscv_fill_hwcap (); +riscv_tlbflush_init (); }static int __init topology_init (void )arch/riscv/mm/tlbflush.c +88
-6@@ -1,11 +1,14 @@// SPDX-License-Identifier: GPL-2.0 +#define pr_fmt (fmt) "riscv: " fmt#include <linux/mm.h> #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> #include <asm/mmu_context.h> +static unsigned long tlb_flush_all_threshold__read_mostly =PTRS_PER_PTE ; +static inline void local_flush_tlb_all_asid (unsigned long asid) { __asm__ __volatile__ ("sfence.vma x0, %0"@@ -23,22 +26,110 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +static inline void riscv_sfence_inval_ir (void ) +{ +/* +* SFENCE.INVAL.IR +* 0001100 00001 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18100073" :::"memory" ); +} + +static inline void riscv_sfence_w_inval (void ) +{ +/* +* SFENCE.W.INVAL +* 0001100 00000 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18000073" :::"memory" ); +} + +static inline void riscv_sinval_vma_asid (unsigned long vma,unsigned long asid) +{ +/* +* rs1 = a0 (VMA) +* rs2 = a1 (asid) +* SINVAL.VMA a0, a1 +* 0001011 01011 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +"add a1, %1, zero\n" +".word 0x16B50073\n" + ::"r" (vma),"r" (asid) + :"a0" ,"a1" ,"memory" ); +} + +static inline void riscv_sinval_vma (unsigned long vma) +{ +/* +* rs1 = a0 (VMA) +* rs2 = 0 +* SINVAL.VMA a0 +* 0001011 00000 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +".word 0x16050073\n" + ::"r" (vma) :"a0" ,"memory" ); +} +static inline void local_flush_tlb_range (unsigned long start,unsigned long size,unsigned long stride) { -if (size <= stride) -local_flush_tlb_page (start); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all (); + } }static inline void local_flush_tlb_range_asid (unsigned long start,unsigned long size,unsigned long stride,unsigned long asid) { -if (size <= stride) -local_flush_tlb_page_asid (start, asid); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma_asid (start, asid); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page_asid (start, asid);
arch/riscv/mm/tlbflush.c static inline void local_flush_tlb_page_asid(unsigned long addr, · line 132
Quoted 10 lines
arch/riscv/mm/tlbflush.c +9
-0+ start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all_asid (asid); + }
Sorry to dig up an old post, but svinval came up and I started looking at this again.
There's some other issues with the code, but at a higher level it's not really clear this is a useful thing to do: splitting up sfence.vma makes sense, but if there's no operations between the sfence.w.inval and sinval.vma (or sinval.vma and sfence.inval.ir) then we're not giving the HW anything else to do concurrently with the flushes and thus I don't see how this would improve performance -- if anything we're just emitting more instructions to do the samething, which would be bad for performance.
So I think if we're going to use these we really need to also split up the TLB flush operations, so we can give something for the HW to do currently with the flushing. That's be a pretty big change to our TLB model, though: essentially we're going from two phases (write the page tables, then flush) to at least three phases (write the page tables, start the flush, finish the flush) or even four (if we want to insert work between both sfence.w.inval->sinval.vma and sinval.vma->sfence.inval.ir).
Not sure if I'm just misunderstanding the performance characteristics, though. Maybe I'm over-thinking things and sfence.vma is heavy-weight enough that implementations are flushing the pipeline for even the page-based flavors and thus sfence.vma-based loops are very slow?
Do you have any benchmarks for the Svinval bits here (which are mixed in with some non-global flushing, that's a different optimization that needs to be split out)?
Quoted 10 lines
arch/riscv/mm/tlbflush.c +3
-0}static void __ipi_flush_tlb_all (void *info)@@ -149,3 +240,16 @@ void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); }#endif + +DEFINE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +EXPORT_SYMBOL_GPL (riscv_flush_tlb_svinval);
arch/riscv/mm/tlbflush.c void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, · line 255
Quoted 10 lines
arch/riscv/mm/tlbflush.c +10
-0+ +void riscv_tlbflush_init (void ) +{ +if (riscv_isa_extension_available (NULL ,SVINVAL )) { +pr_info ("Svinval extension supported\n" ); +static_branch_enable (&riscv_flush_tlb_svinval); + }else { +static_branch_disable (&riscv_flush_tlb_svinval); + } +}
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Re: [RFC PATCH v2 2/2] riscv: mm: use svinval instructions instead of sfence.vma
Quoted 197 lines · Palmer Dabbelt
Quoted 181 lines · On Sun, 24 Apr 2022 02:02:16 PDT (-0700), [email protected] wrote:
When svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma:
sfence.w.inval
svinval.vma
.
.
svinval.vma
sfence.inval.irThe maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to
PTRS_PER_PTE. This is required to avoid soft lockups and the approach is similar to that used in arm64.Signed-off-by Mayuresh Chitale <[email protected]>--- arch/riscv/include/asm/tlbflush.h | 12 ++++ arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- 3 files changed, 123 insertions(+), 6 deletions(-)arch/riscv/include/asm/tlbflush.h +12
-0@@ -22,6 +22,18 @@ static inline void local_flush_tlb_page(unsigned long addr) {ALT_FLUSH_TLB_PAGE (__asm__ __volatile__ ("sfence.vma %0" : :"r" (addr) :"memory" )); } + +void riscv_tlbflush_init (void ); +void __riscv_sfence_w_inval (void ); +void __riscv_sfence_inval_ir (void ); +void __riscv_sinval_vma (unsigned long addr); +void __riscv_sinval_vma_asid (unsigned long addr,unsigned long asid); + +/* Check if we can use sinval for tlb flush */ +DECLARE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +#define riscv_use_flush_tlb_svinval () \ + static_branch_unlikely(&riscv_flush_tlb_svinval) +#else /* CONFIG_MMU */ #define local_flush_tlb_all () do { } while (0)#define local_flush_tlb_page (addr) do { } while (0)arch/riscv/kernel/setup.c +1
-0@@ -295,6 +295,7 @@ void __init setup_arch(char **cmdline_p)#endif riscv_fill_hwcap (); +riscv_tlbflush_init (); }static int __init topology_init (void )arch/riscv/mm/tlbflush.c +88
-6@@ -1,11 +1,14 @@// SPDX-License-Identifier: GPL-2.0 +#define pr_fmt (fmt) "riscv: " fmt#include <linux/mm.h> #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> #include <asm/mmu_context.h> +static unsigned long tlb_flush_all_threshold__read_mostly =PTRS_PER_PTE ; +static inline void local_flush_tlb_all_asid (unsigned long asid) { __asm__ __volatile__ ("sfence.vma x0, %0"@@ -23,22 +26,110 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +static inline void riscv_sfence_inval_ir (void ) +{ +/* +* SFENCE.INVAL.IR +* 0001100 00001 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18100073" :::"memory" ); +} + +static inline void riscv_sfence_w_inval (void ) +{ +/* +* SFENCE.W.INVAL +* 0001100 00000 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18000073" :::"memory" ); +} + +static inline void riscv_sinval_vma_asid (unsigned long vma,unsigned long asid) +{ +/* +* rs1 = a0 (VMA) +* rs2 = a1 (asid) +* SINVAL.VMA a0, a1 +* 0001011 01011 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +"add a1, %1, zero\n" +".word 0x16B50073\n" + ::"r" (vma),"r" (asid) + :"a0" ,"a1" ,"memory" ); +} + +static inline void riscv_sinval_vma (unsigned long vma) +{ +/* +* rs1 = a0 (VMA) +* rs2 = 0 +* SINVAL.VMA a0 +* 0001011 00000 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +".word 0x16050073\n" + ::"r" (vma) :"a0" ,"memory" ); +} +static inline void local_flush_tlb_range (unsigned long start,unsigned long size,unsigned long stride) { -if (size <= stride) -local_flush_tlb_page (start); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all (); + } }static inline void local_flush_tlb_range_asid (unsigned long start,unsigned long size,unsigned long stride,unsigned long asid) { -if (size <= stride) -local_flush_tlb_page_asid (start, asid); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma_asid (start, asid); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page_asid (start, asid);arch/riscv/mm/tlbflush.c static inline void local_flush_tlb_page_asid(unsigned long addr, · line 132
Quoted 10 lines
arch/riscv/mm/tlbflush.c +9
-0+ start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all_asid (asid); + }Sorry to dig up an old post, but svinval came up and I started looking at this again.
Quoted 8 lines
There's some other issues with the code, but at a higher level it's not really clear this is a useful thing to do: splitting up sfence.vma makes sense, but if there's no operations between the sfence.w.inval and sinval.vma (or sinval.vma and sfence.inval.ir) then we're not giving the HW anything else to do concurrently with the flushes and thus I don't see how this would improve performance -- if anything we're just emitting more instructions to do the samething, which would be bad for performance.
Actually this approach is similar to ARM with addition of only two
instructions: sfence.w.inval and sfence.inval.ir and it is also described in the non normative text in the priv spec ch.7.
Quoted 9 lines
So I think if we're going to use these we really need to also split up the TLB flush operations, so we can give something for the HW to do currently with the flushing. That's be a pretty big change to our TLB model, though: essentially we're going from two phases (write the page tables, then flush) to at least three phases (write the page tables, start the flush, finish the flush) or even four (if we want to insert work between both
sfence.w.inval->sinval.vmaandsinval.vma->sfence.inval.ir).
I think the extension is just to allow for a more efficient TLB flushing operation in the hardware and no change in the software TLB model is expected.
Besides, the extension would be disabled by default and only get enabled on platforms that enable it in DT.
Quoted 25 lines
Not sure if I'm just misunderstanding the performance characteristics,
though. Maybe I'm over-thinking things and sfence.vma is heavy-weight
enough that implementations are flushing the pipeline for even the page-based flavors and thus sfence.vma-based loops are very slow?Do you have any benchmarks for the Svinval bits here (which are mixed in with some non-global flushing, that's a different optimization that needs to be split out)?
Quoted 12 lines
arch/riscv/mm/tlbflush.c +5
-0}static void __ipi_flush_tlb_all (void *info)@@ -149,3 +240,16 @@ void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); }#endif + +DEFINE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +EXPORT_SYMBOL_GPL (riscv_flush_tlb_svinval); + +void riscv_tlbflush_init (void )
Quoted 8 lines
arch/riscv/mm/tlbflush.c void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, · line 255
Quoted 8 lines
arch/riscv/mm/tlbflush.c +8
-0+{ +if (riscv_isa_extension_available (NULL ,SVINVAL )) { +pr_info ("Svinval extension supported\n" ); +static_branch_enable (&riscv_flush_tlb_svinval); + }else { +static_branch_disable (&riscv_flush_tlb_svinval); + } +}
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Alexandre Ghiti
reviewerRe: [RFC PATCH v2 2/2] riscv: mm: use svinval instructions instead of sfence.vma
Quoted 216 lines · Mayuresh Chitale
Quoted 195 lines · Palmer Dabbelt
Quoted 181 lines · On Sun, 24 Apr 2022 02:02:16 PDT (-0700), [email protected] wrote:
When svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma:
sfence.w.inval
svinval.vma
.
.
svinval.vma
sfence.inval.irThe maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to
PTRS_PER_PTE. This is required to avoid soft lockups and the approach is similar to that used in arm64.Signed-off-by Mayuresh Chitale <[email protected]>--- arch/riscv/include/asm/tlbflush.h | 12 ++++ arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- 3 files changed, 123 insertions(+), 6 deletions(-)arch/riscv/include/asm/tlbflush.h +12
-0@@ -22,6 +22,18 @@ static inline void local_flush_tlb_page(unsigned long addr) {ALT_FLUSH_TLB_PAGE (__asm__ __volatile__ ("sfence.vma %0" : :"r" (addr) :"memory" )); } + +void riscv_tlbflush_init (void ); +void __riscv_sfence_w_inval (void ); +void __riscv_sfence_inval_ir (void ); +void __riscv_sinval_vma (unsigned long addr); +void __riscv_sinval_vma_asid (unsigned long addr,unsigned long asid); + +/* Check if we can use sinval for tlb flush */ +DECLARE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +#define riscv_use_flush_tlb_svinval () \ + static_branch_unlikely(&riscv_flush_tlb_svinval) +#else /* CONFIG_MMU */ #define local_flush_tlb_all () do { } while (0)#define local_flush_tlb_page (addr) do { } while (0)arch/riscv/kernel/setup.c +1
-0@@ -295,6 +295,7 @@ void __init setup_arch(char **cmdline_p)#endif riscv_fill_hwcap (); +riscv_tlbflush_init (); }static int __init topology_init (void )arch/riscv/mm/tlbflush.c +88
-6@@ -1,11 +1,14 @@// SPDX-License-Identifier: GPL-2.0 +#define pr_fmt (fmt) "riscv: " fmt#include <linux/mm.h> #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> #include <asm/mmu_context.h> +static unsigned long tlb_flush_all_threshold__read_mostly =PTRS_PER_PTE ; +static inline void local_flush_tlb_all_asid (unsigned long asid) { __asm__ __volatile__ ("sfence.vma x0, %0"@@ -23,22 +26,110 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +static inline void riscv_sfence_inval_ir (void ) +{ +/* +* SFENCE.INVAL.IR +* 0001100 00001 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18100073" :::"memory" ); +} + +static inline void riscv_sfence_w_inval (void ) +{ +/* +* SFENCE.W.INVAL +* 0001100 00000 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18000073" :::"memory" ); +} + +static inline void riscv_sinval_vma_asid (unsigned long vma,unsigned long asid) +{ +/* +* rs1 = a0 (VMA) +* rs2 = a1 (asid) +* SINVAL.VMA a0, a1 +* 0001011 01011 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +"add a1, %1, zero\n" +".word 0x16B50073\n" + ::"r" (vma),"r" (asid) + :"a0" ,"a1" ,"memory" ); +} + +static inline void riscv_sinval_vma (unsigned long vma) +{ +/* +* rs1 = a0 (VMA) +* rs2 = 0 +* SINVAL.VMA a0 +* 0001011 00000 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +".word 0x16050073\n" + ::"r" (vma) :"a0" ,"memory" ); +} +static inline void local_flush_tlb_range (unsigned long start,unsigned long size,unsigned long stride) { -if (size <= stride) -local_flush_tlb_page (start); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all (); + } }static inline void local_flush_tlb_range_asid (unsigned long start,unsigned long size,unsigned long stride,unsigned long asid) { -if (size <= stride) -local_flush_tlb_page_asid (start, asid); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma_asid (start, asid); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page_asid (start, asid);arch/riscv/mm/tlbflush.c static inline void local_flush_tlb_page_asid(unsigned long addr, · line 132
Quoted 10 lines
arch/riscv/mm/tlbflush.c +9
-0+ start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all_asid (asid); + }Sorry to dig up an old post, but svinval came up and I started looking at this again.
Quoted 8 lines
There's some other issues with the code, but at a higher level it's not really clear this is a useful thing to do: splitting up sfence.vma makes sense, but if there's no operations between the sfence.w.inval and sinval.vma (or sinval.vma and sfence.inval.ir) then we're not giving the HW anything else to do concurrently with the flushes and thus I don't see how this would improve performance -- if anything we're just emitting more instructions to do the samething, which would be bad for performance.
Actually this approach is similar to ARM with addition of only two
instructions: sfence.w.inval and sfence.inval.ir and it is also described in the non normative text in the priv spec ch.7.Quoted 8 lines
So I think if we're going to use these we really need to also split up the TLB flush operations, so we can give something for the HW to do currently with the flushing. That's be a pretty big change to our TLB model, though: essentially we're going from two phases (write the page tables, then flush) to at least three phases (write the page tables, start the flush, finish the flush) or even four (if we want to insert work between both
sfence.w.inval->sinval.vmaandsinval.vma->sfence.inval.ir).
Quoted 14 lines
I think the extension is just to allow for a more efficient TLB flushing operation in the hardware and no change in the software TLB model is expected.
Besides, the extension would be disabled by default and only get enabled on platforms that enable it in DT.Quoted 8 lines
Not sure if I'm just misunderstanding the performance characteristics,
though. Maybe I'm over-thinking things and sfence.vma is heavy-weight
enough that implementations are flushing the pipeline for even the page-based flavors and thus sfence.vma-based loops are very slow?Do you have any benchmarks for the Svinval bits here (which are mixed in with some non-global flushing, that's a different optimization that needs to be split out)?
Thanks for digging that up!
I have a patchset to optimize the TLB flushes (which also uses this concept of threshold, also present in x86) and I don't want to propose it upstream since I can't measure any performance benefits (which is very weird actually): did you actually benchmark this? If yes, I'd like to know how you did it :)
Thanks,
Alex
Quoted 17 lines
Quoted 17 lines
Quoted 17 lines
arch/riscv/mm/tlbflush.c +9
-0}static void __ipi_flush_tlb_all (void *info)@@ -149,3 +240,16 @@ void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); }#endif + +DEFINE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +EXPORT_SYMBOL_GPL (riscv_flush_tlb_svinval); + +void riscv_tlbflush_init (void ) +{ +if (riscv_isa_extension_available (NULL ,SVINVAL )) { +pr_info ("Svinval extension supported\n" ); +static_branch_enable (&riscv_flush_tlb_svinval);
Quoted 8 lines
Quoted 4 lines
arch/riscv/mm/tlbflush.c void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, · line 255
Quoted 4 lines
arch/riscv/mm/tlbflush.c +4
-0+ }else { +static_branch_disable (&riscv_flush_tlb_svinval); + } +}_______________________________________________
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Re: [RFC PATCH v2 2/2] riscv: mm: use svinval instructions instead of sfence.vma
Quoted 235 lines · Alexandre Ghiti
Quoted 216 lines · Mayuresh Chitale
Quoted 195 lines · Palmer Dabbelt
Quoted 181 lines · On Sun, 24 Apr 2022 02:02:16 PDT (-0700), [email protected] wrote:
When svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma:
sfence.w.inval
svinval.vma
.
.
svinval.vma
sfence.inval.irThe maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to
PTRS_PER_PTE. This is required to avoid soft lockups and the approach is similar to that used in arm64.Signed-off-by Mayuresh Chitale <[email protected]>--- arch/riscv/include/asm/tlbflush.h | 12 ++++ arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- 3 files changed, 123 insertions(+), 6 deletions(-)arch/riscv/include/asm/tlbflush.h +12
-0@@ -22,6 +22,18 @@ static inline void local_flush_tlb_page(unsigned long addr) {ALT_FLUSH_TLB_PAGE (__asm__ __volatile__ ("sfence.vma %0" : :"r" (addr) :"memory" )); } + +void riscv_tlbflush_init (void ); +void __riscv_sfence_w_inval (void ); +void __riscv_sfence_inval_ir (void ); +void __riscv_sinval_vma (unsigned long addr); +void __riscv_sinval_vma_asid (unsigned long addr,unsigned long asid); + +/* Check if we can use sinval for tlb flush */ +DECLARE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +#define riscv_use_flush_tlb_svinval () \ + static_branch_unlikely(&riscv_flush_tlb_svinval) +#else /* CONFIG_MMU */ #define local_flush_tlb_all () do { } while (0)#define local_flush_tlb_page (addr) do { } while (0)arch/riscv/kernel/setup.c +1
-0@@ -295,6 +295,7 @@ void __init setup_arch(char **cmdline_p)#endif riscv_fill_hwcap (); +riscv_tlbflush_init (); }static int __init topology_init (void )arch/riscv/mm/tlbflush.c +88
-6@@ -1,11 +1,14 @@// SPDX-License-Identifier: GPL-2.0 +#define pr_fmt (fmt) "riscv: " fmt#include <linux/mm.h> #include <linux/smp.h> #include <linux/sched.h> #include <asm/sbi.h> #include <asm/mmu_context.h> +static unsigned long tlb_flush_all_threshold__read_mostly =PTRS_PER_PTE ; +static inline void local_flush_tlb_all_asid (unsigned long asid) { __asm__ __volatile__ ("sfence.vma x0, %0"@@ -23,22 +26,110 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, : "memory"); } +static inline void riscv_sfence_inval_ir (void ) +{ +/* +* SFENCE.INVAL.IR +* 0001100 00001 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18100073" :::"memory" ); +} + +static inline void riscv_sfence_w_inval (void ) +{ +/* +* SFENCE.W.INVAL +* 0001100 00000 00000 000 00000 1110011 +*/ + asmvolatile (".word 0x18000073" :::"memory" ); +} + +static inline void riscv_sinval_vma_asid (unsigned long vma,unsigned long asid) +{ +/* +* rs1 = a0 (VMA) +* rs2 = a1 (asid) +* SINVAL.VMA a0, a1 +* 0001011 01011 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +"add a1, %1, zero\n" +".word 0x16B50073\n" + ::"r" (vma),"r" (asid) + :"a0" ,"a1" ,"memory" ); +} + +static inline void riscv_sinval_vma (unsigned long vma) +{ +/* +* rs1 = a0 (VMA) +* rs2 = 0 +* SINVAL.VMA a0 +* 0001011 00000 01010 000 00000 1110011 +*/ + asmvolatile ("srli a0, %0, 2\n" +".word 0x16050073\n" + ::"r" (vma) :"a0" ,"memory" ); +} +static inline void local_flush_tlb_range (unsigned long start,unsigned long size,unsigned long stride) { -if (size <= stride) -local_flush_tlb_page (start); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page (start); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all (); + } }static inline void local_flush_tlb_range_asid (unsigned long start,unsigned long size,unsigned long stride,unsigned long asid) { -if (size <= stride) -local_flush_tlb_page_asid (start, asid); -else +if ((size / stride) <= tlb_flush_all_threshold) { +if (riscv_use_flush_tlb_svinval ()) { +riscv_sfence_w_inval (); +while (size) { +riscv_sinval_vma_asid (start, asid); + start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } +riscv_sfence_inval_ir (); + }else { +while (size) { +local_flush_tlb_page_asid (start, asid);arch/riscv/mm/tlbflush.c static inline void local_flush_tlb_page_asid(unsigned long addr, · line 132
Quoted 10 lines
arch/riscv/mm/tlbflush.c +9
-0+ start += stride; +if (size > stride) + size -= stride; +else + size =0 ; + } + } + }else {local_flush_tlb_all_asid (asid); + }Sorry to dig up an old post, but svinval came up and I started looking at this again.
Quoted 8 lines
There's some other issues with the code, but at a higher level it's not really clear this is a useful thing to do: splitting up sfence.vma makes sense, but if there's no operations between the sfence.w.inval and sinval.vma (or sinval.vma and sfence.inval.ir) then we're not giving the HW anything else to do concurrently with the flushes and thus I don't see how this would improve performance -- if anything we're just emitting more instructions to do the samething, which would be bad for performance.
Actually this approach is similar to ARM with addition of only two
instructions: sfence.w.inval and sfence.inval.ir and it is also described in the non normative text in the priv spec ch.7.Quoted 8 lines
So I think if we're going to use these we really need to also split up the TLB flush operations, so we can give something for the HW to do currently with the flushing. That's be a pretty big change to our TLB model, though: essentially we're going from two phases (write the page tables, then flush) to at least three phases (write the page tables, start the flush, finish the flush) or even four (if we want to insert work between both
sfence.w.inval->sinval.vmaandsinval.vma->sfence.inval.ir).Quoted 14 lines
I think the extension is just to allow for a more efficient TLB flushing operation in the hardware and no change in the software TLB model is expected.
Besides, the extension would be disabled by default and only get enabled on platforms that enable it in DT.Quoted 8 lines
Not sure if I'm just misunderstanding the performance characteristics,
though. Maybe I'm over-thinking things and sfence.vma is heavy-weight
enough that implementations are flushing the pipeline for even the page-based flavors and thus sfence.vma-based loops are very slow?Do you have any benchmarks for the Svinval bits here (which are mixed in with some non-global flushing, that's a different optimization that needs to be split out)?
Quoted 7 lines
Thanks for digging that up!
I have a patchset to optimize the TLB flushes (which also uses this concept of threshold, also present in x86) and I don't want to propose it upstream since I can't measure any performance benefits (which is very weird actually): did you actually benchmark this? If yes, I'd like to know how you did it :)
I couldn't run any benchmark as such. I just used a few tests from stress-ng and the kernel selftests.
Quoted 31 lines
Thanks,
Alex
Quoted 25 lines
Quoted 13 lines
Quoted 13 lines
arch/riscv/mm/tlbflush.c +5
-0}static void __ipi_flush_tlb_all (void *info)@@ -149,3 +240,16 @@ void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); }#endif + +DEFINE_STATIC_KEY_FALSE (riscv_flush_tlb_svinval); +EXPORT_SYMBOL_GPL (riscv_flush_tlb_svinval); + +void riscv_tlbflush_init (void )Quoted 8 lines
arch/riscv/mm/tlbflush.c void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, · line 255
Quoted 8 lines
arch/riscv/mm/tlbflush.c +8
-0+{ +if (riscv_isa_extension_available (NULL ,SVINVAL )) { +pr_info ("Svinval extension supported\n" ); +static_branch_enable (&riscv_flush_tlb_svinval); + }else { +static_branch_disable (&riscv_flush_tlb_svinval); + } +}_______________________________________________
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Palmer Dabbelt
maintainerQuoted 5 lines · On Sun, 24 Apr 2022 02:02:14 PDT (-0700), [email protected] wrote:
This patch adds support for the Svinval extension as defined in the Risc V Privileged specification. This patchset depends on:
https://patchwork.kernel.org/project/linux-riscv/list/?series=632984
IIRC Marc still has some unresolved feedback on that one, for the IRQ bits?
Quoted 14 lines
The feature was tested with qemu from latest master branch with following additional patch:
https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00142.htmlChanges in V2:
- Rebased on 5.18-rc3
- updateriscv_fill_hwcapto probe Svinval extensionMayuresh Chitale (2):
riscv: enum for svinval extension
riscv: mm: use svinval instructions instead of sfence.vma
Quoted 7 lines
arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/tlbflush.h | 12 ++++ arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/tlbflush.c | 116 ++++++++++++++++++++++++++++-- 6 files changed, 126 insertions(+), 6 deletions(-)
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