RZN1 USB Host support
Subsystems (5)
v6 cover RZN1 USB Host support
Hi,
This series add support for the USB Host controllers available on RZN1 (r9a06g032) SOC.
These USB Host controllers are PCI OHCI/EHCI controllers located behind a bridge.
Regards,
Herve
Changes v2:
- Convert bindings to json-schema
- Update clocks description
- Remove unneeded '.compatible = "renesas,pci-r9a06g032"'
Changes v3:
- Remove the unneeded patch that calls clk_bulk_prepare_enable()
- Rework the device tree binding (conversion from .txt and RZ/N1 support)
- Use the RZ/N1 SOCs family only in the driver match compatible string.
- Enable PM and PM_GENERIC_DOMAIN for RZ/N1 and add the missing '#power-domain-cells' in sysctrl node.
Changes v4:
- Remove patches related to PM enable and #pwower-domain-cells as they will be handle out of this series.
- Add Bob's reviewed-by on patch 1
- Add Geert's reviewed by on patch 1 and 6
- Rename clocks and make the 'resets' property optional on RZ/N1 family
- Reword some commit logs and titles
- Fix dst node location (sort by node names or unit addresses)
- Fix the USB PHY node name
Changes v5:
- Rename clocks ("usb_" prefix removed)
- Add Geert's reviewed-by on patch 2, 3, 4 and 5
Changes v6:
- Include schema optionnal part (ie 'if:') in a 'allOf:' block
- Modify commit log on commit 2/6
Herve Codina (6):
dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for
r9a06g032
PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
ARM: dts: r9a06g032: Add internal PCI bridge node
ARM: dts: r9a06g032: Add USB PHY DT support
ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
.../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 -------- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 186 ++++++++++++++++++ arch/arm/boot/dts/r9a06g032.dtsi | 47 +++++ drivers/pci/controller/pci-rcar-gen2.c | 1 + 4 files changed, 234 insertions(+), 84 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
Signature · 1 line
2.35.1
PATCH v6 1/6 dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
Convert Renesas PCI bridge bindings documentation to json-schema.
--- .../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ---------- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 156 ++++++++++++++++++ 2 files changed, 156 insertions(+), 84 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt deleted +0 -84
@@ -1,84 +0,0 @@ -Renesas AHB to PCI bridge -------------------------- - -This is the bridge used internally to connect the USB controllers to the -AHB. There is one bridge instance per USB port connected to the internal -OHCI and EHCI controllers. - -Required properties: -- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC; - "renesas,pci-r8a7743" for the R8A7743 SoC; - "renesas,pci-r8a7744" for the R8A7744 SoC; - "renesas,pci-r8a7745" for the R8A7745 SoC; - "renesas,pci-r8a7790" for the R8A7790 SoC; - "renesas,pci-r8a7791" for the R8A7791 SoC; - "renesas,pci-r8a7793" for the R8A7793 SoC; - "renesas,pci-r8a7794" for the R8A7794 SoC; - "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: A list of physical regions to access the device: the first is - the operational registers for the OHCI/EHCI controllers and the - second is for the bridge configuration and control registers. -- interrupts: interrupt for the device. -- clocks: The reference to the device clock. -- bus-range: The PCI bus number range; as this is a single bus, the range - should be specified as the same value twice. -- #address-cells: must be 3. -- #size-cells: must be 2. -- #interrupt-cells: must be 1. -- interrupt-map: standard property used to define the mapping of the PCI - interrupts to the GIC interrupts. -- interrupt-map-mask: standard property that helps to define the interrupt - mapping. - -Optional properties: -- dma-ranges: a single range for the inbound memory region. If not supplied, - defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the - allowed combinations of address and size. - -Example SoC configuration: - - pci0: pci@ee090000 { - compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; - reg = <0x0 0xee090000 0x0 0xc00>, - <0x0 0xee080000 0x0 0x1100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - - bus-range = <0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupt-map-mask = <0xff00 0 0 0x7>; - interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH - 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; - - usb@1,0 { - reg = <0x800 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - - usb@2,0 { - reg = <0x1000 0 0 0 0>; - phys = <&usb0 0>; - phy-names = "usb"; - }; - }; - -Example board setup: - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -};
Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file +156 -0
156 lines not on this page · raw message
Signature · 1 line
2.35.1
PATCH v6 2/6 dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
In reply to Herve CodinaAdd internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of one.
The 'resets' property for the RZ/N1 family is not required.
--- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 50 +++++++++++++++---- 1 file changed, 40 insertions(+), 10 deletions(-)
Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +40 -10
@@ -15,9 +15,6 @@ description: | AHB. There is one bridge instance per USB port connected to the internal OHCI and EHCI controllers. -allOf: - - $ref: /schemas/pci/pci-bus.yaml# - properties: compatible: oneOf:
@@ -32,6 +29,10 @@ properties: - renesas,pci-r8a7793 # R-Car M2-N - renesas,pci-r8a7794 # R-Car E2 - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 + - items: + - enum: + - renesas,pci-r9a06g032 # RZ/N1D + - const: renesas,pci-rzn1 # RZ/N1 reg: items:
@@ -41,13 +42,9 @@ properties: interrupts: maxItems: 1 - clocks: - items: - - description: Device clock + clocks: true - clock-names: - items: - - const: pclk + clock-names: true resets: maxItems: 1
@@ -106,13 +103,46 @@ required: - interrupt-map - interrupt-map-mask - clocks - - resets - power-domains - bus-range - "#address-cells" - "#size-cells" - "#interrupt-cells" +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,pci-rzn1 + then: + properties: + clocks: + items: + - description: Internal bus clock (AHB) for HOST + - description: Internal bus clock (AHB) Power Management + - description: PCI clock for USB subsystem + clock-names: + items: + - const: hclkh + - const: hclkpm + - const: pciclk + required: + - clock-names + else: + properties: + clocks: + items: + - description: Device clock + clock-names: + items: + - const: pclk + required: + - resets + unevaluatedProperties: false examples:
Signature · 1 line
2.35.1
Re: [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
Quoted 6 lines · Herve Codina
Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of one.
Quoted 7 lines
The 'resets' property for the RZ/N1 family is not required.
Signed-off-by Herve Codina <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>--- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 50 +++++++++++++++---- 1 file changed, 40 insertions(+), 10 deletions(-)
PATCH v6 3/6 PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
In reply to Herve CodinaAdd the Renesas RZ/N1 SOCs family support to the Renesas R-Car Gen2 PCI bridge driver.
The Renesas RZ/N1 SOCs internal PCI bridge is compatible with the one available in the R-Car Gen2 family.
Tested with the RZ/N1D (R9A06G032) SOC.
--- drivers/pci/controller/pci-rcar-gen2.c | 1 + 1 file changed, 1 insertion(+)
drivers/pci/controller/pci-rcar-gen2.c +1 -0
@@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = { { .compatible = "renesas,pci-r8a7791", }, { .compatible = "renesas,pci-r8a7794", }, { .compatible = "renesas,pci-rcar-gen2", }, + { .compatible = "renesas,pci-rzn1", }, { }, };
Signature · 1 line
2.35.1
Re: [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
Quoted 6 lines · Herve Codina
Add the Renesas RZ/N1 SOCs family support to the Renesas R-Car Gen2 PCI bridge driver.
The Renesas RZ/N1 SOCs internal PCI bridge is compatible with the one available in the R-Car Gen2 family.
Quoted 7 lines
Tested with the RZ/N1D (R9A06G032) SOC.
Signed-off-by Herve Codina <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>--- drivers/pci/controller/pci-rcar-gen2.c | 1 + 1 file changed, 1 insertion(+)
PATCH v6 4/6 ARM: dts: r9a06g032: Add internal PCI bridge node
In reply to Herve CodinaAdd the device node for the r9a06g032 internal PCI bridge device.
--- arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
arch/arm/boot/dts/r9a06g032.dtsi +29 -0
@@ -94,6 +94,35 @@ sysctrl: system-controller@4000c000 { clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; }; + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclkh", "hclkpm", "pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + }; + uart0: serial@40060000 { compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; reg = <0x40060000 0x400>;
Signature · 1 line
2.35.1
PATCH v6 5/6 ARM: dts: r9a06g032: Add USB PHY DT support
In reply to Herve CodinaDefine the r9a06g032 generic part of the USB PHY device node.
--- arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
arch/arm/boot/dts/r9a06g032.dtsi +6 -0
@@ -255,4 +255,10 @@ timer { <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; };
Signature · 1 line
2.35.1
PATCH v6 6/6 ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
In reply to Herve CodinaDescribe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device.
--- arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/boot/dts/r9a06g032.dtsi +12 -0
@@ -121,6 +121,18 @@ pci_usb: pci@40030000 { interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; }; uart0: serial@40060000 {
Signature · 1 line
2.35.1
Hi Hervé,
Quoted 5 lines · Herve Codina
This series add support for the USB Host controllers available on RZN1 (r9a06g032) SOC.
These USB Host controllers are PCI OHCI/EHCI controllers located behind a bridge.
Thanks for your series!
Quoted 8 lines
Herve Codina (6):
dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support forr9a06g032PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
ARM: dts: r9a06g032: Add internal PCI bridge node
ARM: dts: r9a06g032: Add USB PHY DT support
ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
As I had applied v5 of the last 3 patches to renesas-devel, and they are already present in soc/for-next, there is no need to resend them.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 20 lines · On Fri, 20 May 2022 14:12:10 +0200 Geert Uytterhoeven <[email protected]>…
Hi Hervé,
Quoted 5 lines · Herve Codina
This series add support for the USB Host controllers available on RZN1 (r9a06g032) SOC.
These USB Host controllers are PCI OHCI/EHCI controllers located behind a bridge.
Thanks for your series!
Quoted 8 lines
Herve Codina (6):
dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support forr9a06g032PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
ARM: dts: r9a06g032: Add internal PCI bridge node
ARM: dts: r9a06g032: Add USB PHY DT support
ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
Quoted 2 lines
As I had applied v5 of the last 3 patches to renesas-devel, and they are already present in soc/for-next, there is no need to resend them.
Thanks. I note that for the next version of this series if needed.
Regards,
Hervé
Signature · 3 lines
Hervé Codina, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Quoted 41 lines · Herve Codina
Hi,
This series add support for the USB Host controllers available on RZN1 (r9a06g032) SOC.
These USB Host controllers are PCI OHCI/EHCI controllers located behind a bridge.
Regards,
HerveChanges v2:
- Convert bindings to json-schema
- Update clocks description
- Remove unneeded '.compatible = "renesas,pci-r9a06g032"'Changes v3:
- Remove the unneeded patch that callsclk_bulk_prepare_enable()
- Rework the device tree binding (conversion from .txt and RZ/N1 support)
- Use the RZ/N1 SOCs family only in the driver match compatible string.
- Enable PM andPM_GENERIC_DOMAINfor RZ/N1 and add the missing '#power-domain-cells' in sysctrl node.Changes v4:
- Remove patches related to PM enable and #pwower-domain-cells as they will be handle out of this series.
- Add Bob's reviewed-by on patch 1
- Add Geert's reviewed by on patch 1 and 6
- Rename clocks and make the 'resets' property optional on RZ/N1 family
- Reword some commit logs and titles
- Fix dst node location (sort by node names or unit addresses)
- Fix the USB PHY node nameChanges v5:
- Rename clocks ("usb_" prefix removed)
- Add Geert's reviewed-by on patch 2, 3, 4 and 5Changes v6:
- Include schema optionnal part (ie 'if:') in a 'allOf:' block
- Modify commit log on commit 2/6
Quoted 5 lines
Herve Codina (6):
dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support forr9a06g032PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
Applied the first three patches (above) to pci/ctrl/rcar-gen2 for v5.20, thank you!
Quoted 15 lines
ARM: dts: r9a06g032: Add internal PCI bridge node
ARM: dts: r9a06g032: Add USB PHY DT support
ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY.../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 -------- .../bindings/pci/renesas,pci-rcar-gen2.yaml | 186 ++++++++++++++++++ arch/arm/boot/dts/r9a06g032.dtsi | 47 +++++ drivers/pci/controller/pci-rcar-gen2.c | 1 + 4 files changed, 234 insertions(+), 84 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yamlSignature · 1 line
2.35.1
Quoted 42 lines · Bjorn Helgaas
Quoted 41 lines · Herve Codina
Hi,
This series add support for the USB Host controllers available on RZN1 (r9a06g032) SOC.
These USB Host controllers are PCI OHCI/EHCI controllers located behind a bridge.
Regards,
HerveChanges v2:
- Convert bindings to json-schema
- Update clocks description
- Remove unneeded '.compatible = "renesas,pci-r9a06g032"'Changes v3:
- Remove the unneeded patch that callsclk_bulk_prepare_enable()
- Rework the device tree binding (conversion from .txt and RZ/N1 support)
- Use the RZ/N1 SOCs family only in the driver match compatible string.
- Enable PM andPM_GENERIC_DOMAINfor RZ/N1 and add the missing '#power-domain-cells' in sysctrl node.Changes v4:
- Remove patches related to PM enable and #pwower-domain-cells as they will be handle out of this series.
- Add Bob's reviewed-by on patch 1
- Add Geert's reviewed by on patch 1 and 6
- Rename clocks and make the 'resets' property optional on RZ/N1 family
- Reword some commit logs and titles
- Fix dst node location (sort by node names or unit addresses)
- Fix the USB PHY node nameChanges v5:
- Rename clocks ("usb_" prefix removed)
- Add Geert's reviewed-by on patch 2, 3, 4 and 5Changes v6:
- Include schema optionnal part (ie 'if:') in a 'allOf:' block
- Modify commit log on commit 2/6
Quoted 8 lines
Quoted 5 lines
Herve Codina (6):
dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support forr9a06g032PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
Applied the first three patches (above) to pci/ctrl/rcar-gen2 for v5.20, thank you!
Oh, just noticed there's no ack from Marek or Yoshihiro, the maintainers of drivers/pci/controller/pci-rcar-gen2.c. Let me know if you object! If you can ack it, I will amend the commits to reflect that.
Bjorn