Introduce Nuvoton Arbel NPCM8XX BMC SoC

Add a compatible string for Nuvoton BMC NPCM845 watchdog.

Signed-off-by Tomer Maimon <[email protected]>

Acked-by Krzysztof Kozlowski <[email protected]>

---
  .../devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt          | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt +2 -1

index 9059f54dc023..866a958b8a2b 100644
@@ -6,7 +6,8 @@ expiry.
 
  Required properties:
  - compatible      : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
-                    "nuvoton,wpcm450-wdt" for WPCM450 (Hermon).
+                    "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
+                    "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
  - reg             : Offset and length of the register set for the device.
  - interrupts      : Contain the timer interrupt with flags for
                      falling edge.

Add binding for the Arbel BMC NPCM8XX Clock controller.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../bindings/clock/nuvoton,npcm845-clk.yaml   | 49 +++++++++++++++++++
 .../dt-bindings/clock/nuvoton,npcm845-clk.h   | 49 +++++++++++++++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm845-clk.h

Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml new file +23 -0

new file mode 100644
index 000000000000..3d4fddc090ca
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM8XX Clock Controller Binding
+
+maintainers:
+  - Tomer Maimon <[email protected]>
+
+description: |
+  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
+  generates and supplies clocks to all modules within the BMC.
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,npcm845-clk
+
+  reg:
+    maxItems: 1
+

Quoted 43 lines · Tomer Maimon

Add binding for the Arbel BMC NPCM8XX Clock controller.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../bindings/clock/nuvoton,npcm845-clk.yaml   | 49 +++++++++++++++++++
 .../dt-bindings/clock/nuvoton,npcm845-clk.h   | 49 +++++++++++++++++++
 2 files changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm845-clk.h

Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml new file +27 -0

new file mode 100644
index 000000000000..3d4fddc090ca
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM8XX Clock Controller Binding
+
+maintainers:
+  - Tomer Maimon <[email protected]>
+
+description: |
+  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
+  generates and supplies clocks to all modules within the BMC.
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,npcm845-clk
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full

Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml line 33

Quoted 6 lines

Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml new file +6 -0

+      list of NPCM8XX clock IDs.
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"

You fixed one comment and ignore second. The same was with v3.

This is still no. Implement all the comments you received. I have to double check your patchsets every time because I cannot trust that you implemented what I asked for.

Best regards,
Krzysztof

Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller which generates and supplies clocks to all modules within the BMC.

Signed-off-by Tomer Maimon <[email protected]>

---
  drivers/clk/Kconfig       |   6 +
  drivers/clk/Makefile      |   1 +
  drivers/clk/clk-npcm8xx.c | 594 ++++++++++++++++++++++++++++++++++++++
  3 files changed, 601 insertions(+)

create mode 100644 drivers/clk/clk-npcm8xx.c

drivers/clk/clk-npcm8xx.c new file +30 -0

+static int npcm8xx_clk_probe(struct platform_device *pdev)
+{
+	struct clk_hw_onecell_data *npcm8xx_clk_data;
+	struct device *dev = &pdev->dev;
+	void __iomem *clk_base;
+	struct clk_hw *hw;
+	int i;
+
+	npcm8xx_clk_data = devm_kzalloc(dev, struct_size(npcm8xx_clk_data, hws,
+							 NPCM8XX_NUM_CLOCKS),
+					GFP_KERNEL);
+	if (!npcm8xx_clk_data)
+		return -ENOMEM;
+
+	clk_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(clk_base))
+		return PTR_ERR(clk_base);
+
+	npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
+
+	for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
+		npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+	/* Reference 25MHz clock */
+	hw = clk_hw_register_fixed_rate(dev, "refclk", NULL, 0, NPCM8XX_REF_CLK);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK] = hw;
+
+	/* Register plls */

drivers/clk/clk-npcm8xx.c new file +78 -0

+		}
+
+		if (pll_data->onecell_idx >= 0)
+			npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
+	}
+
+	/* Register fixed dividers */
+	hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL1_DIV2,
+					       NPCM8XX_CLK_S_PLL1, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		dev_err(dev, "npcm8xx_clk: Can't register fixed div\n");
+		goto unregister_refclk;
+	}
+
+	hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL2_DIV2,
+					       NPCM8XX_CLK_S_PLL2, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		dev_err(dev, "npcm8xx_clk: Can't register pll div2\n");
+		goto unregister_refclk;
+	}
+
+	hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PRE_CLK,
+					       NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		dev_err(dev, "npcm8xx_clk: Can't register ckclk div2\n");
+		goto unregister_refclk;
+	}
+
+	hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_AXI,
+					       NPCM8XX_CLK_S_TH, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		dev_err(dev, "npcm8xx_clk: Can't register axi div2\n");
+		goto unregister_refclk;
+	}
+
+	hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_ATB,
+					       NPCM8XX_CLK_S_AXI, 0, 1, 2);
+	if (IS_ERR(hw)) {
+		dev_err(dev, "npcm8xx_clk: Can't register atb div2\n");
+		goto unregister_refclk;
+	}
+
+	/* Register clock dividers specified in npcm8xx_divs */
+	for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
+		const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
+
+		hw = devm_clk_hw_register_divider(dev, div_data->name,
+						  div_data->parent_name,
+						  div_data->flags,
+						  clk_base + div_data->reg,
+						  div_data->shift,
+						  div_data->width,
+						  div_data->clk_divider_flags,
+						  &npcm8xx_clk_lock);
+		if (IS_ERR(hw)) {
+			dev_err(dev, "npcm8xx_clk: Can't register div table\n");
+			goto unregister_refclk;
+		}
+
+		if (div_data->onecell_idx >= 0)
+			npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
+	}
+
+	/* Register muxes */
+	for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
+		const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
+
+		hw = clk_hw_register_mux_table(dev, mux_data->name,
+					       mux_data->parent_names,
+					       mux_data->num_parents,
+					       mux_data->flags,
+					       clk_base + NPCM8XX_CLKSEL,
+					       mux_data->shift,
+					       mux_data->mask, 0,
+					       mux_data->table,
+					       &npcm8xx_clk_lock);
+
+		if (IS_ERR(hw)) {

drivers/clk/clk-npcm8xx.c new file +21 -0

+
+static const struct of_device_id npcm8xx_clk_dt_ids[] = {
+	{ .compatible = "nuvoton,npcm845-clk", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, npcm8xx_clk_dt_ids);
+
+static struct platform_driver npcm8xx_clk_driver = {
+	.probe  = npcm8xx_clk_probe,
+	.driver = {
+		.name = "npcm8xx_clk",
+		.of_match_table = npcm8xx_clk_dt_ids,
+	},
+};
+
+static int __init npcm8xx_clk_driver_init(void)
+{
+	return platform_driver_register(&npcm8xx_clk_driver);
+}
+arch_initcall(npcm8xx_clk_driver_init);
+

Quoted 11 lines · Tomer Maimon

Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller which generates and supplies clocks to all modules within the BMC.

Signed-off-by Tomer Maimon <[email protected]>

---
  drivers/clk/Kconfig       |   6 +
  drivers/clk/Makefile      |   1 +
  drivers/clk/clk-npcm8xx.c | 594 ++++++++++++++++++++++++++++++++++++++
  3 files changed, 601 insertions(+)

create mode 100644 drivers/clk/clk-npcm8xx.c

[...]

Quoted 30 lines

drivers/clk/clk-npcm8xx.c new file +30 -0

+static int npcm8xx_clk_probe(struct platform_device *pdev)
+{
+     struct clk_hw_onecell_data *npcm8xx_clk_data;
+     struct device *dev = &pdev->dev;
+     void __iomem *clk_base;
+     struct clk_hw *hw;
+     int i;
+
+     npcm8xx_clk_data = devm_kzalloc(dev, struct_size(npcm8xx_clk_data, hws,
+                                                      NPCM8XX_NUM_CLOCKS),
+                                     GFP_KERNEL);
+     if (!npcm8xx_clk_data)
+             return -ENOMEM;
+
+     clk_base = devm_platform_ioremap_resource(pdev, 0);
+     if (IS_ERR(clk_base))
+             return PTR_ERR(clk_base);
+
+     npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
+
+     for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
+             npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+     /* Reference 25MHz clock */
+     hw = clk_hw_register_fixed_rate(dev, "refclk", NULL, 0, NPCM8XX_REF_CLK);
+     if (IS_ERR(hw))
+             return PTR_ERR(hw);
+     npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK] = hw;
+
+     /* Register plls */

drivers/clk/clk-npcm8xx.c line 475

Quoted 10 lines

drivers/clk/clk-npcm8xx.c new file +10 -0

+     for (i = 0; i < ARRAY_SIZE(npcm8xx_plls); i++) {
+             const struct npcm8xx_clk_pll_data *pll_data = &npcm8xx_plls[i];
+
+             hw = npcm8xx_clk_register_pll(dev, clk_base + pll_data->reg,
+                                           pll_data->name,
+                                           pll_data->parent_name,
+                                           pll_data->flags);
+             if (IS_ERR(hw)) {
+                     dev_err(dev, "npcm8xx_clk: Can't register pll\n");
+                     goto unregister_refclk;

goto err_mux_clk?

(so that we unregister what has already been registered in the loop ; and unregister_refclk becomes useless)

Quoted 83 lines

drivers/clk/clk-npcm8xx.c new file +82 -0

+             }
+
+             if (pll_data->onecell_idx >= 0)
+                     npcm8xx_clk_data->hws[pll_data->onecell_idx] = hw;
+     }
+
+     /* Register fixed dividers */
+     hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL1_DIV2,
+                                            NPCM8XX_CLK_S_PLL1, 0, 1, 2);
+     if (IS_ERR(hw)) {
+             dev_err(dev, "npcm8xx_clk: Can't register fixed div\n");
+             goto unregister_refclk;
+     }
+
+     hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PLL2_DIV2,
+                                            NPCM8XX_CLK_S_PLL2, 0, 1, 2);
+     if (IS_ERR(hw)) {
+             dev_err(dev, "npcm8xx_clk: Can't register pll div2\n");
+             goto unregister_refclk;
+     }
+
+     hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_PRE_CLK,
+                                            NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2);
+     if (IS_ERR(hw)) {
+             dev_err(dev, "npcm8xx_clk: Can't register ckclk div2\n");
+             goto unregister_refclk;
+     }
+
+     hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_AXI,
+                                            NPCM8XX_CLK_S_TH, 0, 1, 2);
+     if (IS_ERR(hw)) {
+             dev_err(dev, "npcm8xx_clk: Can't register axi div2\n");
+             goto unregister_refclk;
+     }
+
+     hw = devm_clk_hw_register_fixed_factor(dev, NPCM8XX_CLK_S_ATB,
+                                            NPCM8XX_CLK_S_AXI, 0, 1, 2);
+     if (IS_ERR(hw)) {
+             dev_err(dev, "npcm8xx_clk: Can't register atb div2\n");
+             goto unregister_refclk;
+     }
+
+     /* Register clock dividers specified in npcm8xx_divs */
+     for (i = 0; i < ARRAY_SIZE(npcm8xx_divs); i++) {
+             const struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
+
+             hw = devm_clk_hw_register_divider(dev, div_data->name,
+                                               div_data->parent_name,
+                                               div_data->flags,
+                                               clk_base + div_data->reg,
+                                               div_data->shift,
+                                               div_data->width,
+                                               div_data->clk_divider_flags,
+                                               &npcm8xx_clk_lock);
+             if (IS_ERR(hw)) {
+                     dev_err(dev, "npcm8xx_clk: Can't register div table\n");
+                     goto unregister_refclk;
+             }
+
+             if (div_data->onecell_idx >= 0)
+                     npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
+     }
+
+     /* Register muxes */
+     for (i = 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) {
+             const struct npcm8xx_clk_mux_data *mux_data = &npcm8xx_muxes[i];
+
+             hw = clk_hw_register_mux_table(dev, mux_data->name,
+                                            mux_data->parent_names,
+                                            mux_data->num_parents,
+                                            mux_data->flags,
+                                            clk_base + NPCM8XX_CLKSEL,
+                                            mux_data->shift,
+                                            mux_data->mask, 0,
+                                            mux_data->table,
+                                            &npcm8xx_clk_lock);
+
+             if (IS_ERR(hw)) {
+                     dev_err(dev, "npcm8xx_clk: Can't register mux\n");
+                     goto err_mux_clk;
+             }
+

drivers/clk/clk-npcm8xx.c line 563

Quoted 6 lines

drivers/clk/clk-npcm8xx.c new file +6 -0

+             if (mux_data->onecell_idx >= 0)
+                     npcm8xx_clk_data->hws[mux_data->onecell_idx] = hw;
+     }
+
+     return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+                                        npcm8xx_clk_data);

If this fails, I think we should also "goto err_mux_clk;"

drivers/clk/clk-npcm8xx.c line 573

Quoted 11 lines

drivers/clk/clk-npcm8xx.c new file +10 -0

+
+err_mux_clk:
+     while (i--) {
+             if (npcm8xx_muxes[i].onecell_idx >= 0)
+                     clk_hw_unregister_mux(npcm8xx_clk_data->hws[npcm8xx_muxes[i].onecell_idx]);
+     }
+unregister_refclk:
+     clk_hw_unregister(npcm8xx_clk_data->hws[NPCM8XX_CLK_REFCLK]);
+     return PTR_ERR(hw);
+}

Does a .remove() function is needed to match this error handling path? (or use devm_add_action_or_reset())?

CJ

Quoted 13 lines

drivers/clk/clk-npcm8xx.c new file +13 -0

+
+static const struct of_device_id npcm8xx_clk_dt_ids[] = {
+     { .compatible = "nuvoton,npcm845-clk", },
+     { }
+};
+MODULE_DEVICE_TABLE(of, npcm8xx_clk_dt_ids);
+
+static struct platform_driver npcm8xx_clk_driver = {
+     .probe  = npcm8xx_clk_probe,
+     .driver = {
+             .name = "npcm8xx_clk",
+             .of_match_table = npcm8xx_clk_dt_ids,
+     },

drivers/clk/clk-npcm8xx.c line 594

Quoted 8 lines

drivers/clk/clk-npcm8xx.c new file +8 -0

+};
+
+static int __init npcm8xx_clk_driver_init(void)
+{
+     return platform_driver_register(&npcm8xx_clk_driver);
+}
+arch_initcall(npcm8xx_clk_driver_init);
+

Describe syscon property that handles general control registers (GCR) in Nuvoton BMC NPCM reset driver.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../devicetree/bindings/reset/nuvoton,npcm750-reset.yaml    | 6 ++++++
 1 file changed, 6 insertions(+)