KVM RISC-V Conditional Operations
Subsystems (5)
cover KVM RISC-V Conditional Operations
This series extends KVM RISC-V to allow Guest/VM discover and use conditional operations related ISA extensions (namely XVentanaCondOps and Zicond).
To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1 branch at: https://github.com/avpatel/kvmtool.git
These patches are based upon the latest riscv_kvm_queue and can also be found in the riscv_kvm_condops_v1 branch at:
https://github.com/avpatel/linux.git
Anup Patel (7):
RISC-V: Detect XVentanaCondOps from ISA string
RISC-V: Detect Zicond from ISA string
RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM
RISC-V: KVM: Allow Zicond extension for Guest/VM
KVM: riscv: selftests: Add senvcfg register to get-reg-list test
KVM: riscv: selftests: Add smstateen registers to get-reg-list test
KVM: riscv: selftests: Add condops extensions to get-reg-list test
.../devicetree/bindings/riscv/extensions.yaml | 13 ++++++ arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/uapi/asm/kvm.h | 2 + arch/riscv/kernel/cpufeature.c | 2 + arch/riscv/kvm/vcpu_onereg.c | 4 ++ .../selftests/kvm/riscv/get-reg-list.c | 41 +++++++++++++++++++ 6 files changed, 64 insertions(+)
Signature · 1 line
2.34.1
PATCH 1/7 RISC-V: Detect XVentanaCondOps from ISA string
The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension.
Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI.
--- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 9 insertions(+)
Documentation/devicetree/bindings/riscv/extensions.yaml +7 -0
@@ -171,6 +171,13 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: xventanacondops + description: | + The Ventana specific XVentanaCondOps extension for conditional + arithmetic and conditional-select/move operations defined by the + Ventana custom extensions specification v1.0.1 (or higher) at + https://github.com/ventanamicro/ventana-custom-extensions/releases. + - const: zba description: | The standard Zba bit-manipulation extension for address generation
arch/riscv/include/asm/hwcap.h +1 -0
@@ -59,6 +59,7 @@#define RISCV_ISA_EXT_ZIFENCEI 41#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_XVENTANACONDOPS 44#define RISCV_ISA_EXT_MAX 64
arch/riscv/kernel/cpufeature.c +1 -0
@@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (svinval,RISCV_ISA_EXT_SVINVAL ),__RISCV_ISA_EXT_DATA (svnapot,RISCV_ISA_EXT_SVNAPOT ),__RISCV_ISA_EXT_DATA (svpbmt,RISCV_ISA_EXT_SVPBMT ), + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS), };const size_t riscv_isa_ext_count =ARRAY_SIZE (riscv_isa_ext);
Signature · 1 line
2.34.1
Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
Hey Anup,
Quoted 20 lines · Anup Patel
The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension.
Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI.
Signed-off-by Anup Patel <[email protected]>--- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 9 insertions(+)Documentation/devicetree/bindings/riscv/extensions.yaml +0
-0
Documentation/devicetree/bindings/riscv/extensions.yaml properties: · line 180
Quoted 10 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +7
-0@@ -171,6 +171,13 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: xventanacondops + description: | + The Ventana specific XVentanaCondOps extension for conditional + arithmetic and conditional-select/move operations defined by the + Ventana custom extensions specification v1.0.1 (or higher) at + https://github.com/ventanamicro/ventana-custom-extensions/releases. +
For this and the next patch, the binding change needs to be split out from the code. checkpatch should've complained about it.
Quoted 20 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +0
-0- const: zba description: | The standard Zba bit-manipulation extension for address generationarch/riscv/include/asm/hwcap.h +1
-0@@ -59,6 +59,7 @@#define RISCV_ISA_EXT_ZIFENCEI 41#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_XVENTANACONDOPS 44#define RISCV_ISA_EXT_MAX 64arch/riscv/kernel/cpufeature.c +0
-0
arch/riscv/kernel/cpufeature.c const struct riscv_isa_ext_data riscv_isa_ext[] = { · line 185
Quoted 4 lines
arch/riscv/kernel/cpufeature.c +1
-0@@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (svinval,RISCV_ISA_EXT_SVINVAL ),__RISCV_ISA_EXT_DATA (svnapot,RISCV_ISA_EXT_SVNAPOT ),__RISCV_ISA_EXT_DATA (svpbmt,RISCV_ISA_EXT_SVPBMT ), + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS),
I've been banging on for a bit about people doing weird stuff to detect their vendor extensions, so nice to see it being done properly :)
Cheers,
Conor.
Quoted 6 lines
arch/riscv/kernel/cpufeature.c +0
-0};const size_t riscv_isa_ext_count =ARRAY_SIZE (riscv_isa_ext);Signature · 1 line
2.34.1
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 228 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/kvm-riscv/attachments/20230919/5c16f9ee/attachment.sig>
Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
Quoted 27 lines · On Tue, Sep 19, 2023 at 12:56?PM Conor Dooley <[email protected]> wrote:
Hey Anup,
Quoted 23 lines · Anup Patel
The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension.
Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI.
Signed-off-by Anup Patel <[email protected]>--- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 9 insertions(+)Documentation/devicetree/bindings/riscv/extensions.yaml +0
-0@@ -171,6 +171,13 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification.
Quoted 10 lines
Documentation/devicetree/bindings/riscv/extensions.yaml properties: · line 180
Quoted 7 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +7
-0+ - const: xventanacondops + description: | + The Ventana specific XVentanaCondOps extension for conditional + arithmetic and conditional-select/move operations defined by the + Ventana custom extensions specification v1.0.1 (or higher) at + https://github.com/ventanamicro/ventana-custom-extensions/releases. +For this and the next patch, the binding change needs to be split out from the code. checkpatch should've complained about it.
Okay, I will split this patch.
Quoted 30 lines
Quoted 21 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +0
-0- const: zba description: | The standard Zba bit-manipulation extension for address generationarch/riscv/include/asm/hwcap.h +1
-0@@ -59,6 +59,7 @@#define RISCV_ISA_EXT_ZIFENCEI 41#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_XVENTANACONDOPS 44#define RISCV_ISA_EXT_MAX 64arch/riscv/kernel/cpufeature.c +0
-0arch/riscv/kernel/cpufeature.c const struct riscv_isa_ext_data riscv_isa_ext[] = { · line 185
Quoted 4 lines
arch/riscv/kernel/cpufeature.c +1
-0@@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (svinval,RISCV_ISA_EXT_SVINVAL ),__RISCV_ISA_EXT_DATA (svnapot,RISCV_ISA_EXT_SVNAPOT ),__RISCV_ISA_EXT_DATA (svpbmt,RISCV_ISA_EXT_SVPBMT ), + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS),I've been banging on for a bit about people doing weird stuff to detect their vendor extensions, so nice to see it being done properly :)
Quoted 9 lines
Cheers,
Conor.Quoted 6 lines
arch/riscv/kernel/cpufeature.c +0
-1};const size_t riscv_isa_ext_count =ARRAY_SIZE (riscv_isa_ext); --2.34.1
Regards,
Anup
Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
In reply to Anup PatelQuoted 60 lines · Anup Patel
The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension.
Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI.
Signed-off-by Anup Patel <[email protected]>--- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 9 insertions(+)Documentation/devicetree/bindings/riscv/extensions.yaml +7
-0@@ -171,6 +171,13 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: xventanacondops + description: | + The Ventana specific XVentanaCondOps extension for conditional + arithmetic and conditional-select/move operations defined by the + Ventana custom extensions specification v1.0.1 (or higher) at + https://github.com/ventanamicro/ventana-custom-extensions/releases. + - const: zba description: | The standard Zba bit-manipulation extension for address generationarch/riscv/include/asm/hwcap.h +1
-0@@ -59,6 +59,7 @@#define RISCV_ISA_EXT_ZIFENCEI 41#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_XVENTANACONDOPS 44#define RISCV_ISA_EXT_MAX 64arch/riscv/kernel/cpufeature.c +1
-0@@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (svinval,RISCV_ISA_EXT_SVINVAL ),__RISCV_ISA_EXT_DATA (svnapot,RISCV_ISA_EXT_SVNAPOT ),__RISCV_ISA_EXT_DATA (svpbmt,RISCV_ISA_EXT_SVPBMT ), + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS), };const size_t riscv_isa_ext_count =ARRAY_SIZE (riscv_isa_ext);Signature · 1 line
2.34.1
Besides Conor's comment about splitting the patch,
Thanks,
drew
Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
In reply to Anup PatelQuoted 7 lines · Anup Patel
The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension.
Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI.
Umm, I though Linux/riscv would never support vendor specific extensions?
Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
Quoted 7 lines · On Mon, Oct 2, 2023 at 11:57?AM Christoph Hellwig <[email protected]> wrote:
Quoted 5 lines · Anup Patel
The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension.
Quoted 6 lines
Quoted 2 lines
Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI.
Umm, I though Linux/riscv would never support vendor specific extensions?
We already have few T-Head specific extensions so Linux RISC-V does allow vendor extensions.
Regards,
Anup
Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string
Quoted 5 lines · Anup Patel
Quoted 2 lines
extensions?
We already have few T-Head specific extensions so Linux RISC-V does allow vendor extensions.
Only for kernel internal operation and to actually boot the chip. IMHO still the wrong tradeoff, but very different from actually user visible extensions that will lead to fragmentation of the ecoysystem.
PATCH 2/7 RISC-V: Detect Zicond from ISA string
In reply to Anup PatelThe RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through DT or ACPI.
--- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 8 insertions(+)
Documentation/devicetree/bindings/riscv/extensions.yaml +6 -0
@@ -225,6 +225,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 8fb6694 + ("Update Gemfile") of riscv-zicond. + - const: zicsr description: | The standard Zicsr extension for control and status register
arch/riscv/include/asm/hwcap.h +1 -0
@@ -60,6 +60,7 @@#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43#define RISCV_ISA_EXT_XVENTANACONDOPS 44 +#define RISCV_ISA_EXT_ZICOND 45#define RISCV_ISA_EXT_MAX 64
arch/riscv/kernel/cpufeature.c +1 -0
@@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (zba,RISCV_ISA_EXT_ZBA ),__RISCV_ISA_EXT_DATA (zbb,RISCV_ISA_EXT_ZBB ),__RISCV_ISA_EXT_DATA (zbs,RISCV_ISA_EXT_ZBS ), +__RISCV_ISA_EXT_DATA (zicond,RISCV_ISA_EXT_ZICOND ),__RISCV_ISA_EXT_DATA (smaia,RISCV_ISA_EXT_SMAIA ),__RISCV_ISA_EXT_DATA (smstateen,RISCV_ISA_EXT_SMSTATEEN ), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
Signature · 1 line
2.34.1
Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
Quoted 9 lines · Anup Patel
The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through DT or ACPI.
Signed-off-by Anup Patel <[email protected]>
Same applies here w.r.t. splitting in two.
Thanks,
Conor.
Quoted 50 lines
--- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 8 insertions(+)Documentation/devicetree/bindings/riscv/extensions.yaml +6
-0@@ -225,6 +225,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 8fb6694 + ("Update Gemfile") of riscv-zicond. + - const: zicsr description: | The standard Zicsr extension for control and status registerarch/riscv/include/asm/hwcap.h +1
-0@@ -60,6 +60,7 @@#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43#define RISCV_ISA_EXT_XVENTANACONDOPS 44 +#define RISCV_ISA_EXT_ZICOND 45#define RISCV_ISA_EXT_MAX 64arch/riscv/kernel/cpufeature.c +1
-0@@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (zba,RISCV_ISA_EXT_ZBA ),__RISCV_ISA_EXT_DATA (zbb,RISCV_ISA_EXT_ZBB ),__RISCV_ISA_EXT_DATA (zbs,RISCV_ISA_EXT_ZBS ), +__RISCV_ISA_EXT_DATA (zicond,RISCV_ISA_EXT_ZICOND ),__RISCV_ISA_EXT_DATA (smaia,RISCV_ISA_EXT_SMAIA ),__RISCV_ISA_EXT_DATA (smstateen,RISCV_ISA_EXT_SMSTATEEN ), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),Signature · 1 line
2.34.1
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 228 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/kvm-riscv/attachments/20230919/22e7ef05/attachment.sig>
Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
Quoted 7 lines · On Tue, Sep 19, 2023 at 12:57?PM Conor Dooley <[email protected]> wrote:
Quoted 5 lines · Anup Patel
The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension.
Quoted 6 lines
Quoted 4 lines
Let us detect Zicond extension from ISA string available through DT or ACPI.
Signed-off-by Anup Patel <[email protected]>Same applies here w.r.t. splitting in two.
Okay, I will update.
Regards,
Anup
Quoted 54 lines
Thanks,
Conor.Quoted 50 lines
--- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 8 insertions(+)Documentation/devicetree/bindings/riscv/extensions.yaml +6
-0@@ -225,6 +225,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 8fb6694 + ("Update Gemfile") of riscv-zicond. + - const: zicsr description: | The standard Zicsr extension for control and status registerarch/riscv/include/asm/hwcap.h +1
-0@@ -60,6 +60,7 @@#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43#define RISCV_ISA_EXT_XVENTANACONDOPS 44 +#define RISCV_ISA_EXT_ZICOND 45#define RISCV_ISA_EXT_MAX 64arch/riscv/kernel/cpufeature.c +1
-1@@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (zba,RISCV_ISA_EXT_ZBA ),__RISCV_ISA_EXT_DATA (zbb,RISCV_ISA_EXT_ZBB ),__RISCV_ISA_EXT_DATA (zbs,RISCV_ISA_EXT_ZBS ), +__RISCV_ISA_EXT_DATA (zicond,RISCV_ISA_EXT_ZICOND ),__RISCV_ISA_EXT_DATA (smaia,RISCV_ISA_EXT_SMAIA ),__RISCV_ISA_EXT_DATA (smstateen,RISCV_ISA_EXT_SMSTATEEN ), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), --2.34.1
Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
In reply to Anup PatelQuoted 20 lines · Anup Patel
The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through DT or ACPI.
Signed-off-by Anup Patel <[email protected]>--- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 8 insertions(+)Documentation/devicetree/bindings/riscv/extensions.yaml +0
-0
Documentation/devicetree/bindings/riscv/extensions.yaml properties: · line 232
Quoted 8 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +5
-0@@ -225,6 +225,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 8fb6694 + ("Update Gemfile") of riscv-zicond.
As of yesterday, v1.0 of the spec points at commit 95cf1f9 ("Add changes requested by Ved during signoff")
Quoted 21 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +1
-0+ - const: zicsr description: | The standard Zicsr extension for control and status registerarch/riscv/include/asm/hwcap.h +1
-0@@ -60,6 +60,7 @@#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43#define RISCV_ISA_EXT_XVENTANACONDOPS 44 +#define RISCV_ISA_EXT_ZICOND 45#define RISCV_ISA_EXT_MAX 64arch/riscv/kernel/cpufeature.c +0
-0
arch/riscv/kernel/cpufeature.c const struct riscv_isa_ext_data riscv_isa_ext[] = { · line 177
Quoted 4 lines
arch/riscv/kernel/cpufeature.c +1
-0@@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (zba,RISCV_ISA_EXT_ZBA ),__RISCV_ISA_EXT_DATA (zbb,RISCV_ISA_EXT_ZBB ),__RISCV_ISA_EXT_DATA (zbs,RISCV_ISA_EXT_ZBS ), + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
Zi extensions come before Zb extensions.
Quoted 6 lines
arch/riscv/kernel/cpufeature.c +0
-0__RISCV_ISA_EXT_DATA (smaia,RISCV_ISA_EXT_SMAIA ),__RISCV_ISA_EXT_DATA (smstateen,RISCV_ISA_EXT_SMSTATEEN ), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),Signature · 1 line
2.34.1
Thanks,
drew
Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string
Quoted 25 lines · On Wed, Sep 20, 2023 at 1:14?PM Andrew Jones <[email protected]> wrote:
Quoted 23 lines · Anup Patel
The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension.
Let us detect Zicond extension from ISA string available through DT or ACPI.
Signed-off-by Anup Patel <[email protected]>--- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 8 insertions(+)Documentation/devicetree/bindings/riscv/extensions.yaml +0
-0@@ -225,6 +225,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification.
Quoted 8 lines
Documentation/devicetree/bindings/riscv/extensions.yaml properties: · line 232
Quoted 5 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +5
-0+ - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 8fb6694 + ("Update Gemfile") of riscv-zicond.As of yesterday, v1.0 of the spec points at commit 95cf1f9 ("Add changes requested by Ved during signoff")
Okay, I will update.
Quoted 17 lines
Quoted 17 lines
Documentation/devicetree/bindings/riscv/extensions.yaml +1
-0+ - const: zicsr description: | The standard Zicsr extension for control and status registerarch/riscv/include/asm/hwcap.h +1
-0@@ -60,6 +60,7 @@#define RISCV_ISA_EXT_ZIHPM 42#define RISCV_ISA_EXT_SMSTATEEN 43#define RISCV_ISA_EXT_XVENTANACONDOPS 44 +#define RISCV_ISA_EXT_ZICOND 45#define RISCV_ISA_EXT_MAX 64
Quoted 11 lines
arch/riscv/kernel/cpufeature.c const struct riscv_isa_ext_data riscv_isa_ext[] = { · line 177
Quoted 9 lines
arch/riscv/kernel/cpufeature.c +1
-0@@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {__RISCV_ISA_EXT_DATA (zba,RISCV_ISA_EXT_ZBA ),__RISCV_ISA_EXT_DATA (zbb,RISCV_ISA_EXT_ZBB ),__RISCV_ISA_EXT_DATA (zbs,RISCV_ISA_EXT_ZBS ), + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),Zi extensions come before Zb extensions.
Okay, I will update.
Quoted 10 lines
Quoted 7 lines
arch/riscv/kernel/cpufeature.c +0
-1__RISCV_ISA_EXT_DATA (smaia,RISCV_ISA_EXT_SMAIA ),__RISCV_ISA_EXT_DATA (smstateen,RISCV_ISA_EXT_SMSTATEEN ), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), --2.34.1
Thanks,
drew
Regards,
Anup
PATCH 3/7 RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM
In reply to Anup PatelWe extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable XVentanaCondOps extension for Guest/VM.
--- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+)
arch/riscv/include/uapi/asm/kvm.h +1 -0
@@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID {KVM_RISCV_ISA_EXT_ZIFENCEI ,KVM_RISCV_ISA_EXT_ZIHPM ,KVM_RISCV_ISA_EXT_SMSTATEEN , +KVM_RISCV_ISA_EXT_XVENTANACONDOPS , KVM_RISCV_ISA_EXT_MAX, };
arch/riscv/kvm/vcpu_onereg.c +2 -0
@@ -40,6 +40,7 @@ static const unsigned long kvm_isa_ext_arr[] = {KVM_ISA_EXT_ARR (SVINVAL ),KVM_ISA_EXT_ARR (SVNAPOT ),KVM_ISA_EXT_ARR (SVPBMT ), +KVM_ISA_EXT_ARR (XVENTANACONDOPS ),KVM_ISA_EXT_ARR (ZBA ),KVM_ISA_EXT_ARR (ZBB ), KVM_ISA_EXT_ARR(ZBS),
@@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)case KVM_RISCV_ISA_EXT_SSTC :case KVM_RISCV_ISA_EXT_SVINVAL :case KVM_RISCV_ISA_EXT_SVNAPOT : +case KVM_RISCV_ISA_EXT_XVENTANACONDOPS :case KVM_RISCV_ISA_EXT_ZBA :case KVM_RISCV_ISA_EXT_ZBB :case KVM_RISCV_ISA_EXT_ZBS :
Signature · 1 line
2.34.1
Re: [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM
Quoted 45 lines · Anup Patel
We extend the KVM ISA extension
ONE_REGinterface to allow KVM user space to detect and enable XVentanaCondOps extension for Guest/VM.Signed-off-by Anup Patel <[email protected]>--- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+)arch/riscv/include/uapi/asm/kvm.h +1
-0@@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID {KVM_RISCV_ISA_EXT_ZIFENCEI ,KVM_RISCV_ISA_EXT_ZIHPM ,KVM_RISCV_ISA_EXT_SMSTATEEN , +KVM_RISCV_ISA_EXT_XVENTANACONDOPS , KVM_RISCV_ISA_EXT_MAX, };arch/riscv/kvm/vcpu_onereg.c +2
-0@@ -40,6 +40,7 @@ static const unsigned long kvm_isa_ext_arr[] = {KVM_ISA_EXT_ARR (SVINVAL ),KVM_ISA_EXT_ARR (SVNAPOT ),KVM_ISA_EXT_ARR (SVPBMT ), +KVM_ISA_EXT_ARR (XVENTANACONDOPS ),KVM_ISA_EXT_ARR (ZBA ),KVM_ISA_EXT_ARR (ZBB ), KVM_ISA_EXT_ARR(ZBS),@@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)case KVM_RISCV_ISA_EXT_SSTC :case KVM_RISCV_ISA_EXT_SVINVAL :case KVM_RISCV_ISA_EXT_SVNAPOT : +case KVM_RISCV_ISA_EXT_XVENTANACONDOPS :case KVM_RISCV_ISA_EXT_ZBA :case KVM_RISCV_ISA_EXT_ZBB :case KVM_RISCV_ISA_EXT_ZBS :Signature · 1 line
2.34.1
PATCH 4/7 RISC-V: KVM: Allow Zicond extension for Guest/VM
In reply to Anup PatelWe extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zicond extension for Guest/VM.
--- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+)
arch/riscv/include/uapi/asm/kvm.h +1 -0
@@ -139,6 +139,7 @@ enum KVM_RISCV_ISA_EXT_ID {KVM_RISCV_ISA_EXT_ZIHPM ,KVM_RISCV_ISA_EXT_SMSTATEEN ,KVM_RISCV_ISA_EXT_XVENTANACONDOPS , +KVM_RISCV_ISA_EXT_ZICOND , KVM_RISCV_ISA_EXT_MAX, };
arch/riscv/kvm/vcpu_onereg.c +2 -0
@@ -47,6 +47,7 @@ static const unsigned long kvm_isa_ext_arr[] = {KVM_ISA_EXT_ARR (ZICBOM ),KVM_ISA_EXT_ARR (ZICBOZ ),KVM_ISA_EXT_ARR (ZICNTR ), +KVM_ISA_EXT_ARR (ZICOND ),KVM_ISA_EXT_ARR (ZICSR ),KVM_ISA_EXT_ARR (ZIFENCEI ), KVM_ISA_EXT_ARR(ZIHINTPAUSE),
@@ -95,6 +96,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)case KVM_RISCV_ISA_EXT_ZBB :case KVM_RISCV_ISA_EXT_ZBS :case KVM_RISCV_ISA_EXT_ZICNTR : +case KVM_RISCV_ISA_EXT_ZICOND :case KVM_RISCV_ISA_EXT_ZICSR :case KVM_RISCV_ISA_EXT_ZIFENCEI :case KVM_RISCV_ISA_EXT_ZIHINTPAUSE :
Signature · 1 line
2.34.1
Re: [PATCH 4/7] RISC-V: KVM: Allow Zicond extension for Guest/VM
Quoted 44 lines · Anup Patel
We extend the KVM ISA extension
ONE_REGinterface to allow KVM user space to detect and enable Zicond extension for Guest/VM.Signed-off-by Anup Patel <[email protected]>--- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+)arch/riscv/include/uapi/asm/kvm.h +1
-0@@ -139,6 +139,7 @@ enum KVM_RISCV_ISA_EXT_ID {KVM_RISCV_ISA_EXT_ZIHPM ,KVM_RISCV_ISA_EXT_SMSTATEEN ,KVM_RISCV_ISA_EXT_XVENTANACONDOPS , +KVM_RISCV_ISA_EXT_ZICOND , KVM_RISCV_ISA_EXT_MAX, };arch/riscv/kvm/vcpu_onereg.c +2
-0@@ -47,6 +47,7 @@ static const unsigned long kvm_isa_ext_arr[] = {KVM_ISA_EXT_ARR (ZICBOM ),KVM_ISA_EXT_ARR (ZICBOZ ),KVM_ISA_EXT_ARR (ZICNTR ), +KVM_ISA_EXT_ARR (ZICOND ),KVM_ISA_EXT_ARR (ZICSR ),KVM_ISA_EXT_ARR (ZIFENCEI ), KVM_ISA_EXT_ARR(ZIHINTPAUSE),@@ -95,6 +96,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)case KVM_RISCV_ISA_EXT_ZBB :case KVM_RISCV_ISA_EXT_ZBS :case KVM_RISCV_ISA_EXT_ZICNTR : +case KVM_RISCV_ISA_EXT_ZICOND :case KVM_RISCV_ISA_EXT_ZICSR :case KVM_RISCV_ISA_EXT_ZIFENCEI :case KVM_RISCV_ISA_EXT_ZIHINTPAUSE :Signature · 1 line
2.34.1
PATCH 5/7 KVM: riscv: selftests: Add senvcfg register to get-reg-list test
In reply to Anup PatelWe have a new senvcfg register in the general CSR ONE_REG interface so let us add it to get-reg-list test.
--- tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+)
tools/testing/selftests/kvm/riscv/get-reg-list.c +3 -0
@@ -209,6 +209,8 @@ static const char *general_csr_id_to_str(__u64 reg_off)return RISCV_CSR_GENERAL (satp);case KVM_REG_RISCV_CSR_REG (scounteren):return RISCV_CSR_GENERAL (scounteren); +case KVM_REG_RISCV_CSR_REG (senvcfg): +return RISCV_CSR_GENERAL (senvcfg); }TEST_FAIL ("Unknown general csr reg: 0x%llx" , reg_off);
@@ -532,6 +534,7 @@ static __u64 base_regs[] = {KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (sip),KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (satp),KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (scounteren), +KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (senvcfg),KVM_REG_RISCV |KVM_REG_SIZE_U64 |KVM_REG_RISCV_TIMER |KVM_REG_RISCV_TIMER_REG (frequency),KVM_REG_RISCV |KVM_REG_SIZE_U64 |KVM_REG_RISCV_TIMER |KVM_REG_RISCV_TIMER_REG (time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
Signature · 1 line
2.34.1
Re: [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test
Quoted 32 lines · Anup Patel
We have a new senvcfg register in the general CSR
ONE_REGinterface so let us add it to get-reg-list test.Signed-off-by Anup Patel <[email protected]>--- tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+)tools/testing/selftests/kvm/riscv/get-reg-list.c +3
-0@@ -209,6 +209,8 @@ static const char *general_csr_id_to_str(__u64 reg_off)return RISCV_CSR_GENERAL (satp);case KVM_REG_RISCV_CSR_REG (scounteren):return RISCV_CSR_GENERAL (scounteren); +case KVM_REG_RISCV_CSR_REG (senvcfg): +return RISCV_CSR_GENERAL (senvcfg); }TEST_FAIL ("Unknown general csr reg: 0x%llx" , reg_off);@@ -532,6 +534,7 @@ static __u64 base_regs[] = {KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (sip),KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (satp),KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (scounteren), +KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_GENERAL |KVM_REG_RISCV_CSR_REG (senvcfg),KVM_REG_RISCV |KVM_REG_SIZE_U64 |KVM_REG_RISCV_TIMER |KVM_REG_RISCV_TIMER_REG (frequency),KVM_REG_RISCV |KVM_REG_SIZE_U64 |KVM_REG_RISCV_TIMER |KVM_REG_RISCV_TIMER_REG (time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),Signature · 1 line
2.34.1
PATCH 6/7 KVM: riscv: selftests: Add smstateen registers to get-reg-list test
In reply to Anup PatelWe have a new smstateen registers as separate sub-type of CSR ONE_REG interface so let us add these registers to get-reg-list test.
--- .../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+)
tools/testing/selftests/kvm/riscv/get-reg-list.c +34 -0
@@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZICSR :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIFENCEI :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIHPM : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_SMSTATEEN :return true;/* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_AIA |KVM_REG_RISCV_CSR_AIA_REG (siselect):
@@ -184,6 +185,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id) "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"#define RISCV_CSR_AIA (csr) \ "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_SMSTATEEN (csr) \ + "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"static const char *general_csr_id_to_str (__u64 reg_off) {
@@ -241,6 +244,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off)return NULL ; } +static const char *smstateen_csr_id_to_str (__u64 reg_off) +{ +/* reg_off is the offset into struct kvm_riscv_smstateen_csr */ +switch (reg_off) { +case KVM_REG_RISCV_CSR_SMSTATEEN_REG (sstateen0): +return RISCV_CSR_SMSTATEEN (sstateen0); + } + +TEST_FAIL ("Unknown smstateen csr reg: 0x%llx" , reg_off); +return NULL ; +} +static const char *csr_id_to_str (const char *prefix,__u64 id) {__u64 reg_off = id & ~(REG_MASK |KVM_REG_RISCV_CSR );
@@ -253,6 +268,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)return general_csr_id_to_str (reg_off);case KVM_REG_RISCV_CSR_AIA :return aia_csr_id_to_str (reg_off); +case KVM_REG_RISCV_CSR_SMSTATEEN : +return smstateen_csr_id_to_str (reg_off); }TEST_FAIL ("%s: Unknown csr subtype: 0x%llx" , prefix, reg_subtype);
@@ -342,6 +359,7 @@ static const char *isa_ext_id_to_str(__u64 id)"KVM_RISCV_ISA_EXT_ZICSR" ,"KVM_RISCV_ISA_EXT_ZIFENCEI" ,"KVM_RISCV_ISA_EXT_ZIHPM" , + "KVM_RISCV_ISA_EXT_SMSTATEEN", };if (reg_off >=ARRAY_SIZE (kvm_isa_ext_reg_name)) {
@@ -629,6 +647,11 @@ static __u64 aia_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA, }; +static __u64 smstateen_regs[] = { +KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_SMSTATEEN |KVM_REG_RISCV_CSR_SMSTATEEN_REG (sstateen0), +KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_SMSTATEEN , +}; +static __u64 fp_f_regs[] = {KVM_REG_RISCV |KVM_REG_SIZE_U32 |KVM_REG_RISCV_FP_F |KVM_REG_RISCV_FP_F_REG (f[0 ]),KVM_REG_RISCV |KVM_REG_SIZE_U32 |KVM_REG_RISCV_FP_F |KVM_REG_RISCV_FP_F_REG (f[1 ]),
@@ -736,6 +759,8 @@ static __u64 fp_d_regs[] = { {"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}#define AIA_REGS_SUBLIST \ {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),} +#define SMSTATEEN_REGS_SUBLIST \ + {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}#define FP_F_REGS_SUBLIST \ {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \ .regs_n = ARRAY_SIZE(fp_f_regs),}
@@ -863,6 +888,14 @@ static struct vcpu_reg_list aia_config = { }, }; +static struct vcpu_reg_list smstateen_config = { + .sublists = { +BASE_SUBLIST , +SMSTATEEN_REGS_SUBLIST , + {0 }, + }, +}; +static struct vcpu_reg_list fp_f_config = { .sublists = {BASE_SUBLIST ,
@@ -895,6 +928,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &zifencei_config, &zihpm_config, &aia_config, + &smstateen_config, &fp_f_config, &fp_d_config, };
Signature · 1 line
2.34.1
Re: [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers to get-reg-list test
Quoted 58 lines · Anup Patel
We have a new smstateen registers as separate sub-type of CSR
ONE_REGinterface so let us add these registers to get-reg-list test.Signed-off-by Anup Patel <[email protected]>--- .../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+)tools/testing/selftests/kvm/riscv/get-reg-list.c +17
-0@@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZICSR :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIFENCEI :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIHPM : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_SMSTATEEN :return true;/* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_AIA |KVM_REG_RISCV_CSR_AIA_REG (siselect):@@ -184,6 +185,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id) "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"#define RISCV_CSR_AIA (csr) \ "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_SMSTATEEN (csr) \ + "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"static const char *general_csr_id_to_str (__u64 reg_off) {@@ -241,6 +244,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off)return NULL ; } +static const char *smstateen_csr_id_to_str (__u64 reg_off) +{ +/* reg_off is the offset into struct kvm_riscv_smstateen_csr */ +switch (reg_off) { +case KVM_REG_RISCV_CSR_SMSTATEEN_REG (sstateen0): +return RISCV_CSR_SMSTATEEN (sstateen0); + } + +TEST_FAIL ("Unknown smstateen csr reg: 0x%llx" , reg_off); +return NULL ; +} +static const char *csr_id_to_str (const char *prefix,__u64 id) {__u64 reg_off = id & ~(REG_MASK |KVM_REG_RISCV_CSR );@@ -253,6 +268,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id)return general_csr_id_to_str (reg_off);case KVM_REG_RISCV_CSR_AIA :return aia_csr_id_to_str (reg_off); +case KVM_REG_RISCV_CSR_SMSTATEEN : +return smstateen_csr_id_to_str (reg_off); }TEST_FAIL ("%s: Unknown csr subtype: 0x%llx" , prefix, reg_subtype);
tools/testing/selftests/kvm/riscv/get-reg-list.c static const char *isa_ext_id_to_str(__u64 id) · line 362
Quoted 4 lines
tools/testing/selftests/kvm/riscv/get-reg-list.c +1
-0@@ -342,6 +359,7 @@ static const char *isa_ext_id_to_str(__u64 id)"KVM_RISCV_ISA_EXT_ZICSR" ,"KVM_RISCV_ISA_EXT_ZIFENCEI" ,"KVM_RISCV_ISA_EXT_ZIHPM" , + "KVM_RISCV_ISA_EXT_SMSTATEEN",
If we merge [1] first, then this would be added in alphabetical order.
[1] https://lore.kernel.org/all/20230817162344.17076-6-ajones at ventanamicro.com/
Quoted 50 lines
tools/testing/selftests/kvm/riscv/get-reg-list.c +16
-0};if (reg_off >=ARRAY_SIZE (kvm_isa_ext_reg_name)) {@@ -629,6 +647,11 @@ static __u64 aia_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA, }; +static __u64 smstateen_regs[] = { +KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_SMSTATEEN |KVM_REG_RISCV_CSR_SMSTATEEN_REG (sstateen0), +KVM_REG_RISCV |KVM_REG_SIZE_ULONG |KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_SMSTATEEN , +}; +static __u64 fp_f_regs[] = {KVM_REG_RISCV |KVM_REG_SIZE_U32 |KVM_REG_RISCV_FP_F |KVM_REG_RISCV_FP_F_REG (f[0 ]),KVM_REG_RISCV |KVM_REG_SIZE_U32 |KVM_REG_RISCV_FP_F |KVM_REG_RISCV_FP_F_REG (f[1 ]),@@ -736,6 +759,8 @@ static __u64 fp_d_regs[] = { {"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}#define AIA_REGS_SUBLIST \ {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),} +#define SMSTATEEN_REGS_SUBLIST \ + {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}#define FP_F_REGS_SUBLIST \ {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \ .regs_n = ARRAY_SIZE(fp_f_regs),}@@ -863,6 +888,14 @@ static struct vcpu_reg_list aia_config = { }, }; +static struct vcpu_reg_list smstateen_config = { + .sublists = { +BASE_SUBLIST , +SMSTATEEN_REGS_SUBLIST , + {0 }, + }, +}; +static struct vcpu_reg_list fp_f_config = { .sublists = {BASE_SUBLIST ,@@ -895,6 +928,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &zifencei_config, &zihpm_config, &aia_config, + &smstateen_config, &fp_f_config, &fp_d_config, };Signature · 1 line
2.34.1
Thanks,
drew
PATCH 7/7 KVM: riscv: selftests: Add condops extensions to get-reg-list test
In reply to Anup PatelWe have a new conditional operations related ISA extensions so let us add these extensions to get-reg-list test.
--- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+)
tools/testing/selftests/kvm/riscv/get-reg-list.c +4 -0
@@ -50,6 +50,8 @@ bool filter_reg(__u64 reg)case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIFENCEI :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIHPM :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_SMSTATEEN : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_XVENTANACONDOPS : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZICOND :return true;/* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_AIA |KVM_REG_RISCV_CSR_AIA_REG (siselect):
@@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id)"KVM_RISCV_ISA_EXT_ZIFENCEI" ,"KVM_RISCV_ISA_EXT_ZIHPM" ,"KVM_RISCV_ISA_EXT_SMSTATEEN" , +"KVM_RISCV_ISA_EXT_XVENTANACONDOPS" , + "KVM_RISCV_ISA_EXT_ZICOND", };if (reg_off >=ARRAY_SIZE (kvm_isa_ext_reg_name)) {
Signature · 1 line
2.34.1
Re: [PATCH 7/7] KVM: riscv: selftests: Add condops extensions to get-reg-list test
Quoted 33 lines · Anup Patel
We have a new conditional operations related ISA extensions so let us add these extensions to get-reg-list test.
Signed-off-by Anup Patel <[email protected]>--- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+)tools/testing/selftests/kvm/riscv/get-reg-list.c +4
-0@@ -50,6 +50,8 @@ bool filter_reg(__u64 reg)case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIFENCEI :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIHPM :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_SMSTATEEN : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_XVENTANACONDOPS : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZICOND :return true;/* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_AIA |KVM_REG_RISCV_CSR_AIA_REG (siselect):@@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id)"KVM_RISCV_ISA_EXT_ZIFENCEI" ,"KVM_RISCV_ISA_EXT_ZIHPM" ,"KVM_RISCV_ISA_EXT_SMSTATEEN" , +"KVM_RISCV_ISA_EXT_XVENTANACONDOPS" , + "KVM_RISCV_ISA_EXT_ZICOND", };if (reg_off >=ARRAY_SIZE (kvm_isa_ext_reg_name)) {Signature · 1 line
2.34.1
Don't we want to add test configs for these?
Thanks,
drew
Re: [PATCH 7/7] KVM: riscv: selftests: Add condops extensions to get-reg-list test
Quoted 31 lines · On Wed, Sep 20, 2023 at 1:48?PM Andrew Jones <[email protected]> wrote:
Quoted 29 lines · Anup Patel
We have a new conditional operations related ISA extensions so let us add these extensions to get-reg-list test.
Signed-off-by Anup Patel <[email protected]>--- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+)tools/testing/selftests/kvm/riscv/get-reg-list.c +4
-0@@ -50,6 +50,8 @@ bool filter_reg(__u64 reg)case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIFENCEI :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZIHPM :case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_SMSTATEEN : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_XVENTANACONDOPS : +case KVM_REG_RISCV_ISA_EXT |KVM_RISCV_ISA_EXT_ZICOND :return true;/* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR |KVM_REG_RISCV_CSR_AIA |KVM_REG_RISCV_CSR_AIA_REG (siselect):@@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id)"KVM_RISCV_ISA_EXT_ZIFENCEI" ,"KVM_RISCV_ISA_EXT_ZIHPM" ,"KVM_RISCV_ISA_EXT_SMSTATEEN" , +"KVM_RISCV_ISA_EXT_XVENTANACONDOPS" , + "KVM_RISCV_ISA_EXT_ZICOND", };
Quoted 6 lines
Quoted 4 lines
tools/testing/selftests/kvm/riscv/get-reg-list.c +0
-1if (reg_off >=ARRAY_SIZE (kvm_isa_ext_reg_name)) { --2.34.1
Don't we want to add test configs for these?
Okay, I will update.
Regards,
Anup