Device Tree support for SH7751 based board
Subsystems (15)
Yoshinori Sato
maintainerv8 cover Device Tree support for SH7751 based board
This is an updated version of something I wrote about 7 years ago. Minimum support for R2D-plus and LANDISK.
I think R2D-1 will work if you add AX88796 to dts.
And board-specific functions and SCI's SPI functions are not supported.
You can get it working with qemu found here.
https://gitlab.com/yoshinori.sato/qemu/-/tree/landisk
v8 changes.
- rebase v6.10-rc1
- sh/Konfig: Keep compatibility for non-DT.
- renesas,sh7750-cpg.yaml: cleanup.
- smi,sm501.yaml: rewrite register definition.
- sm501.c: remove unneeded changes.
- renesas,sh7751-irl-ext.yaml: fix intetrupt-cells.
- renesas,sh7751-pci.yaml: remove duplicate.
- clk-divider.c: cleanup.
- clk-gate.c: cleanup.
- sh_tmu.c: cleanup.
- pci-sh7751.c: cleanup.
v7 changes.
- sh/kernel/setup.c: fix kernel parameter handling.
- clk-sh7750.c: cleanup.
- sh_tmu.c: cleanup.
- irq-renesas-sh7751.c: IPR definition move to code.
- irq-renesas-sh7751irl.c: update register definition.
- pci-sh7751.c: Register initialization fix.
- sm501 and sm501fb: Re-design Device Tree properties.
v6 changes.
- pci-sh7751: merge register define.
- pci-sh7751: use 'dma-ranges' property.
- pci-sh7751: rename general PCI properties.
- sm501 and sm501fb: Re-design Device Tree properties.
- sh/kernel/setup: cleanup command line setup.
- irq-sh7751.c: some cleanup.
v5 changes.
- pci-sh7751: revert header changes. and some fix in previuous driver.
- sh/kernel/iomap.c: Use SH io functions.
- sm501 and sm501fb: re-write DT support.
v4 changes.
- cpg-sh7750: use clk-divider and clk-gate.
- pci-sh7751: unified header files to old PCI driver.
- irq-renesas-sh7751: IPR registers direct mapping.
- irq-renesas-sh7751irl: useful register bit mapping.
- sm501 and sm501fb: re-write dt parser.
- j2_minus: fix build error.
- dt-binding schema: fix some errors.
- *.dts: cleanup.
v3 changes.
- Rewrite clk drivers.
- Added sh_tmu to OF support.
- Cleanup PCI stuff.
- Update sm501 and sm501fb OF support.
- Update devicetree and documents.
v2 changes.
- Rebasing v6,6-rc1
- re-write irqchip driver.
- Add binding documents.
- Cleanup review comment.
Yoshinori Sato (36):
sh: passing FDT address to kernel startup.
sh: Kconfig unified OF supported targets.
sh: Enable OF support for build and configuration.
dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y
sh: kernel/setup Update DT support.
sh: Fix COMMON_CLK support in CONFIG_OF=y.
clocksource: sh_tmu: CLOCKSOURCE support.
dt-binding: Add compatible SH7750 SoC
sh: Common PCI Framework driver support.
pci: pci-sh7751: Add SH7751 PCI driver
dt-bindings: pci: pci-sh7751: Add SH7751 PCI
dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
clk: Compatible with narrow registers
clk: renesas: Add SH7750/7751 CPG Driver
irqchip: Add SH7751 INTC driver
dt-bindings: interrupt-controller: renesas,sh7751-intc: Add
json-schema
irqchip: SH7751 external interrupt encoder with enable gate.
dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add
json-schema
serial: sh-sci: fix SH4 OF support.
dt-bindings: serial: renesas,scif: Add scif-sh7751.
dt-bindings: display: smi,sm501: SMI SM501 binding json-schema
mfd: sm501: Convert platform_data to OF property
dt-binding: sh: cpus: Add SH CPUs json-schema
dt-bindings: vendor-prefixes: Add iodata
dt-bindings: ata: ata-generic: Add new targets
dt-bindings: soc: renesas: sh: Add SH7751 based target
sh: SH7751R SoC Internal peripheral definition dtsi.
sh: add RTS7751R2D Plus DTS
sh: Add IO DATA LANDISK dts
sh: Add IO DATA USL-5P dts
sh: j2_mimas_v2.dts update
sh: Add dtbs target support.
sh: RTS7751R2D Plus OF defconfig
sh: LANDISK OF defconfig
sh: j2_defconfig: update
.../devicetree/bindings/ata/ata-generic.yaml | 2 + .../bindings/clock/renesas,sh7750-cpg.yaml | 107 ++++ .../bindings/display/smi,sm501.yaml | 443 ++++++++++++++++ .../renesas,sh7751-intc.yaml | 53 ++ .../renesas,sh7751-irl-ext.yaml | 57 +++ .../bindings/pci/renesas,sh7751-pci.yaml | 75 +++ .../bindings/serial/renesas,scif.yaml | 1 + .../devicetree/bindings/sh/cpus.yaml | 63 +++ .../devicetree/bindings/soc/renesas/sh.yaml | 27 + .../bindings/timer/renesas,tmu.yaml | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/sh/Kconfig | 11 +- arch/sh/boards/Kconfig | 23 +- arch/sh/boards/of-generic.c | 28 +- arch/sh/boot/compressed/head_32.S | 5 +- arch/sh/boot/dts/Makefile | 5 + arch/sh/boot/dts/j2_mimas_v2.dts | 2 +- arch/sh/boot/dts/landisk.dts | 77 +++ arch/sh/boot/dts/rts7751r2dplus.dts | 172 +++++++ arch/sh/boot/dts/sh7751r.dtsi | 105 ++++ arch/sh/boot/dts/usl-5p.dts | 85 ++++ arch/sh/configs/j2_defconfig | 11 +- arch/sh/configs/landisk-of_defconfig | 102 ++++ arch/sh/configs/rts7751r2dplus-of_defconfig | 77 +++ arch/sh/drivers/Makefile | 2 + arch/sh/include/asm/io.h | 8 + arch/sh/include/asm/irq.h | 10 +- arch/sh/include/asm/pci.h | 4 + arch/sh/kernel/cpu/Makefile | 6 +- arch/sh/kernel/cpu/irq/imask.c | 17 + arch/sh/kernel/cpu/sh4/Makefile | 3 + arch/sh/kernel/iomap.c | 18 + arch/sh/kernel/setup.c | 31 +- arch/sh/kernel/time.c | 12 + drivers/clk/clk-divider.c | 41 +- drivers/clk/clk-gate.c | 49 +- drivers/clk/renesas/Kconfig | 13 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-sh7750.c | 480 ++++++++++++++++++ drivers/clocksource/sh_tmu.c | 198 +++++--- drivers/irqchip/Kconfig | 15 + drivers/irqchip/Makefile | 3 + drivers/irqchip/irq-renesas-sh7751.c | 282 ++++++++++ drivers/irqchip/irq-renesas-sh7751irl.c | 221 ++++++++ drivers/mfd/sm501.c | 238 +++++++++ drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 335 ++++++++++++ drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 +- drivers/video/fbdev/sm501fb.c | 87 ++++ include/dt-bindings/clock/sh7750-cpg.h | 26 + .../renesas,sh7751-intc.h | 19 + include/linux/clk-provider.h | 20 +- include/linux/sh_intc.h | 7 +- 55 files changed, 3539 insertions(+), 160 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml create mode 100644 arch/sh/boot/dts/landisk.dts create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts create mode 100644 arch/sh/boot/dts/sh7751r.dtsi create mode 100644 arch/sh/boot/dts/usl-5p.dts create mode 100644 arch/sh/configs/landisk-of_defconfig create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig create mode 100644 drivers/clk/renesas/clk-sh7750.c create mode 100644 drivers/irqchip/irq-renesas-sh7751.c create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c create mode 100644 drivers/pci/controller/pci-sh7751.c create mode 100644 include/dt-bindings/clock/sh7750-cpg.h create mode 100644 include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 1/36 sh: passing FDT address to kernel startup.
R4 is caller saved in SH ABI.
Save it so it doesn't get corrupted until it's needed for initialization.
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
--- arch/sh/boot/compressed/head_32.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
arch/sh/boot/compressed/head_32.S +3 -2
@@ -15,7 +15,8 @@ startup: /* Load initial status register */ mov.l init_sr, r1 ldc r1, sr - + /* Save FDT address */ + mov r4, r13 /* Move myself to proper location if necessary */ mova 1f, r0 mov.l 1f, r2
@@ -84,7 +85,7 @@ l1: /* Jump to the start of the decompressed kernel */ mov.l kernel_start_addr, r0 jmp @r0 - nop + mov r13, r4 .align 2 bss_start_addr:
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 2/36 sh: Kconfig unified OF supported targets.
In reply to Yoshinori SatoTargets that support OF should be treated as one board.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/Kconfig | 1 + arch/sh/boards/Kconfig | 23 +++++++++++++---------- 2 files changed, 14 insertions(+), 10 deletions(-)
arch/sh/Kconfig +1 -0
@@ -711,6 +711,7 @@ config ROMIMAGE_MMCIF choice prompt "Kernel command line" default CMDLINE_OVERWRITE + depends on !OF || USE_BUILTIN_DTB help Setting this option allows the kernel command line arguments to be set.
arch/sh/boards/Kconfig +13 -10
@@ -19,16 +19,9 @@ config SH_DEVICE_TREE select TIMER_OF select COMMON_CLK select GENERIC_CALIBRATE_DELAY - -config SH_JCORE_SOC - bool "J-Core SoC" - select SH_DEVICE_TREE - select CLKSRC_JCORE_PIT - select JCORE_AIC - depends on CPU_J2 - help - Select this option to include drivers core components of the - J-Core SoC, including interrupt controllers and timers. + select GENERIC_IRQ_CHIP + select SYS_SUPPORTS_PCI + select GENERIC_PCI_IOMAP if PCI config SH_SOLUTION_ENGINE bool "SolutionEngine"
@@ -293,6 +286,7 @@ config SH_LANDISK bool "LANDISK" depends on CPU_SUBTYPE_SH7751R select HAVE_PCI + select SYS_SUPPORTS_PCI help I-O DATA DEVICE, INC. "LANDISK Series" support.
@@ -369,6 +363,15 @@ config SH_APSH4AD0A help Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. +config SH_OF_BOARD + bool "General Open Firmware boards" + select SH_DEVICE_TREE + select CLKSRC_JCORE_PIT if CPU_J2 + select JCORE_AIC if CPU_J2 + select HAVE_PCI if CPU_SUBTYPE_SH7751R + help + This board means general OF supported targets. + source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig"
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 3/36 sh: Enable OF support for build and configuration.
In reply to Yoshinori SatoIRQ, CLK and PCI will be migrated to a common driver framework. So if OF, disable the SH specific drivers.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/Kconfig | 11 ++++++----- arch/sh/drivers/Makefile | 2 ++ arch/sh/kernel/cpu/Makefile | 9 +++++++-- arch/sh/kernel/cpu/sh4/Makefile | 3 +++ 4 files changed, 18 insertions(+), 7 deletions(-)
arch/sh/Kconfig +6 -5
@@ -66,10 +66,10 @@ config SUPERH select MODULES_USE_ELF_RELA select NEED_SG_DMA_LENGTH select NO_DMA if !MMU && !DMA_COHERENT - select NO_GENERIC_PCI_IOPORT_MAP if PCI + select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE select OLD_SIGACTION select OLD_SIGSUSPEND - select PCI_DOMAINS if PCI + select PCI_DOMAINS if PCI && !SH_DEVICE_TREE select PERF_EVENTS select PERF_USE_VMALLOC select RTC_LIB
@@ -154,7 +154,7 @@ menu "System type" # config CPU_SH2 bool - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE config CPU_SH2A bool
@@ -180,7 +180,7 @@ config CPU_SH4 select CPU_HAS_INTEVT select CPU_HAS_SR_RB select CPU_HAS_FPU if !CPU_SH4AL_DSP - select SH_INTC + select SH_INTC if !SH_DEVICE_TREE select SYS_SUPPORTS_SH_TMU config CPU_SH4A
@@ -523,6 +523,7 @@ config SH_PCLK_FREQ config SH_CLK_CPG def_bool y + depends on !COMMON_CLK config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG
@@ -667,7 +668,7 @@ config BUILTIN_DTB_SOURCE kernel. config ZERO_PAGE_OFFSET - hex + hex "Zero page offset" default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ SH_7751_SOLUTION_ENGINE default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
arch/sh/drivers/Makefile +2 -0
@@ -5,6 +5,8 @@ obj-y += dma/ platform_early.o +ifndef CONFIG_SH_DEVICE_TREE obj-$(CONFIG_PCI) += pci/ +endif obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT) += heartbeat.o
arch/sh/kernel/cpu/Makefile +7 -2
@@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/ # Common interfaces. obj-$(CONFIG_SH_ADC) += adc.o +ifndef CONFIG_COMMON_CLK +obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o - -obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o +endif +ifndef CONFIG_GENERIC_IRQ_CHIP +obj-y += irq/ +endif +obj-y += init.o fpu.o pfc.o proc.o
arch/sh/kernel/cpu/sh4/Makefile +3 -0
@@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o +ifndef CONFIG_SH_DEVICE_TREE # CPU subtype setup obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o
@@ -29,5 +30,7 @@ ifndef CONFIG_CPU_SH4A clock-$(CONFIG_CPU_SH4) := clock-sh4.o endif +endif # CONFIG_SH_DEVICE_TREE + obj-y += $(clock-y) obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 4/36 dt-bindings: interrupt-controller: Add header for Renesas SH3/4 INTC.
In reply to Yoshinori SatoRenesas SH7751 Interrupt controller priority register define.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../renesas,sh7751-intc.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h
include/dt-bindings/interrupt-controller/renesas,sh7751-intc.h new file +19 -0
@@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +* +* SH3/4 INTC IPR register offsets (Address / bits) +*/ + +#ifndef __DT_BINDINGS_RENESAS_SH7751_INTC +#define __DT_BINDINGS_RENESAS_SH7751_INTC + +#define IPRA 0 +#define IPRB 4 +#define IPRC 8 +#define IPRD 12 +#define INTPRI00 256 +#define IPR_B12 12 +#define IPR_B8 8 +#define IPR_B4 4 +#define IPR_B0 0 + +#endif
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 5/36 sh: GENERIC_IRQ_CHIP support for CONFIG_OF=y
In reply to Yoshinori SatoRemove unused function prototype.
Add helper update_sr_imask. use for SH7751 irq driver. Add stub intc_finalize.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/include/asm/io.h | 2 ++ arch/sh/include/asm/irq.h | 10 ++++++++-- arch/sh/kernel/cpu/Makefile | 5 +---- arch/sh/kernel/cpu/irq/imask.c | 17 +++++++++++++++++ include/linux/sh_intc.h | 7 ++++++- 5 files changed, 34 insertions(+), 7 deletions(-)
arch/sh/include/asm/io.h +2 -0
@@ -121,7 +121,9 @@ __BUILD_MEMORY_STRING(__raw_, q, u64)#define ioport_map ioport_map#define ioport_unmap ioport_unmap +#ifndef CONFIG_SH_DEVICE_TREE #define pci_iounmap pci_iounmap +#endif #define ioread8 ioread8#define ioread16 ioread16
arch/sh/include/asm/irq.h +8 -2
@@ -16,8 +16,8 @@/* * Simple Mask Register Support */ -extern void make_maskreg_irq (unsigned int irq); -extern unsigned short *irq_mask_register; + +void update_sr_imask (unsigned int irq,bool enable);/* * PINT IRQs
@@ -54,4 +54,10 @@ extern void irq_finish(unsigned int irq);#include <asm-generic/irq.h> +/* SH3/4 INTC stuff */ +/* IRL level 0 - 15 */ +#define NR_IRL 15 +/* IRL0 -> IRQ16 */ +#define IRL_BASE_IRQ 16 +#endif /* __ASM_SH_IRQ_H */
arch/sh/kernel/cpu/Makefile +1 -4
@@ -20,7 +20,4 @@ ifndef CONFIG_COMMON_CLK obj-y += clock.o obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o endif -ifndef CONFIG_GENERIC_IRQ_CHIP -obj-y += irq/ -endif -obj-y += init.o fpu.o pfc.o proc.o +obj-y += init.o fpu.o pfc.o proc.o irq/
arch/sh/kernel/cpu/irq/imask.c +17 -0
@@ -51,6 +51,7 @@ static inline void set_interrupt_registers(int ip) : "t"); } +#ifndef CONFIG_GENERIC_IRQ_CHIP static void mask_imask_irq (struct irq_data *data) {unsigned int irq = data->irq;
@@ -83,3 +84,19 @@ void make_imask_irq(unsigned int irq)irq_set_chip_and_handler_name (irq, &imask_irq_chip, handle_level_irq, "level"); } +#else +void update_sr_imask (unsigned int irq,bool enable) +{ +if (enable) { +set_bit (irq, imask_mask); + interrupt_priority =IMASK_PRIORITY - +find_first_bit (imask_mask,IMASK_PRIORITY ); + }else { +clear_bit (irq, imask_mask); +if (interrupt_priority <IMASK_PRIORITY - irq) + interrupt_priority =IMASK_PRIORITY - irq; + } +set_interrupt_registers (interrupt_priority); +} +EXPORT_SYMBOL (update_sr_imask); +#endif
include/linux/sh_intc.h +6 -1
@@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = { \int register_intc_controller (struct intc_desc *desc);int intc_set_priority (unsigned int irq,unsigned int prio);int intc_irq_lookup (const char *chipname,intc_enum enum_id); +#ifndef CONFIG_SH_DEVICE_TREE void intc_finalize (void ); - +#else +static inline void intc_finalize (void ) +{ +} +#endif #ifdef CONFIG_INTC_USERIMASK int register_intc_userimask (unsigned long addr);#else
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 6/36 sh: kernel/setup Update DT support.
In reply to Yoshinori SatoFix extrnal fdt initialize and bootargs.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/Kconfig | 1 - arch/sh/kernel/setup.c | 31 ++++++++++++++++++++----------- 2 files changed, 20 insertions(+), 12 deletions(-)
arch/sh/Kconfig +0 -1
@@ -712,7 +712,6 @@ config ROMIMAGE_MMCIF choice prompt "Kernel command line" default CMDLINE_OVERWRITE - depends on !OF || USE_BUILTIN_DTB help Setting this option allows the kernel command line arguments to be set.
arch/sh/kernel/setup.c +20 -11
@@ -30,6 +30,7 @@#include <linux/memblock.h> #include <linux/of.h> #include <linux/of_fdt.h> +#include <linux/libfdt.h> #include <linux/uaccess.h> #include <uapi/linux/mount.h> #include <asm/io.h>
@@ -269,8 +270,22 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)void __init setup_arch (char **cmdline_p) { +#if defined(CONFIG_OF ) && defined(CONFIG_OF_EARLY_FLATTREE ) +if (IS_ENABLED (CONFIG_USE_BUILTIN_DTB )) { +/* Relocate Embedded DTB */ +unflatten_and_copy_device_tree (); + }else if (initial_boot_params) { +/* Reserve external DTB area */ +memblock_reserve (__pa (initial_boot_params), +fdt_totalsize (initial_boot_params)); +unflatten_device_tree (); + } +/* copy from /chosen/bootargs */ +strscpy (command_line, boot_command_line,COMMAND_LINE_SIZE ); +#endif enable_mmu (); +#ifndef CONFIG_OF ROOT_DEV =old_decode_dev (ORIG_ROOT_DEV ); printk(KERN_NOTICE "Boot params:\n"
@@ -299,14 +314,16 @@ void __init setup_arch(char **cmdline_p) bss_resource.start =virt_to_phys (__bss_start); bss_resource.end =virt_to_phys (__bss_stop)-1 ; +#endif #ifdef CONFIG_CMDLINE_OVERWRITE strscpy (command_line,CONFIG_CMDLINE ,sizeof (command_line)); -#else -strscpy (command_line,COMMAND_LINE ,sizeof (command_line)); +#elif !defined(CONFIG_OF ) || defined(CONFIG_USE_BUILTIN_DTB ) +if (*COMMAND_LINE ) +strscpy (command_line,COMMAND_LINE ,sizeof (command_line)); +#endif #ifdef CONFIG_CMDLINE_EXTEND strlcat (command_line," " ,sizeof (command_line));strlcat (command_line,CONFIG_CMDLINE ,sizeof (command_line)); -#endif #endif /* Save unparsed command line copy for /proc/cmdline */
@@ -322,14 +339,6 @@ void __init setup_arch(char **cmdline_p)/* Let earlyprintk output early console messages */ sh_early_platform_driver_probe ("earlyprintk" ,1 ,1 ); -#ifdef CONFIG_OF_EARLY_FLATTREE -#ifdef CONFIG_USE_BUILTIN_DTB -unflatten_and_copy_device_tree (); -#else -unflatten_device_tree (); -#endif -#endif -paging_init ();/* Perform the machine specific initialisation */
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 7/36 sh: Fix COMMON_CLK support in CONFIG_OF=y.
In reply to Yoshinori SatoInitialize the clock and timer using the COMMON_CLK procedure. sh's earlytimer mechanism doesn't work properly in OF, so timer initialization is delayed.
If CONFIG_OF=y, perform the general timer initialization procedure.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boards/of-generic.c | 28 ++++------------------------ arch/sh/kernel/time.c | 12 ++++++++++++ 2 files changed, 16 insertions(+), 24 deletions(-)
arch/sh/boards/of-generic.c +4 -24
@@ -8,6 +8,7 @@#include <linux/of.h> #include <linux/of_clk.h> #include <linux/of_fdt.h> +#include <linux/of_platform.h> #include <linux/clocksource.h> #include <linux/irqchip.h>
@@ -100,16 +101,7 @@ static void sh_of_smp_probe(void)#endif -static void noop (void ) -{ -} - -static int noopi (void ) -{ -return 0 ; -} - -static void __init sh_of_mem_reserve (void ) +static void __init sh_of_mem_init (void ) {early_init_fdt_reserve_self ();early_init_fdt_scan_reserved_mem ();
@@ -142,25 +134,13 @@ static void __init sh_of_init_irq(void)irqchip_init (); } -static int __init sh_of_clk_init (void ) -{ -#ifdef CONFIG_COMMON_CLK -/* Disabled pending move to COMMON_CLK framework. */ -pr_info ("SH generic board support: scanning for clk providers\n" ); -of_clk_init (NULL ); -#endif -return 0 ; -} - static struct sh_machine_vector __initmv sh_of_generic_mv = { .mv_setup = sh_of_setup, .mv_name ="devicetree" ,/* replaced by DT root's model */ .mv_irq_demux = sh_of_irq_demux, .mv_init_irq = sh_of_init_irq, - .mv_clk_init = sh_of_clk_init, - .mv_mode_pins = noopi, - .mv_mem_init = noop, - .mv_mem_reserve = sh_of_mem_reserve, + .mv_mode_pins = generic_mode_pins, + .mv_mem_init = sh_of_mem_init, };struct sh_clk_ops ;
arch/sh/kernel/time.c +12 -0
@@ -19,7 +19,9 @@#include <asm/clock.h> #include <asm/rtc.h> #include <asm/platform_early.h> +#include <linux/of_clk.h> +#ifndef CONFIG_SH_DEVICE_TREE static void __init sh_late_time_init (void ) {/*
@@ -43,3 +45,13 @@ void __init time_init(void) late_time_init = sh_late_time_init; } +#else +/* CONFIG_SH_DEVICE_TREE */ +void __init time_init (void ) +{ +pr_info ("SH generic board support: scanning for clk providers\n" ); + +of_clk_init (NULL ); +timer_probe (); +} +#endif
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 8/36 clocksource: sh_tmu: CLOCKSOURCE support.
In reply to Yoshinori SatoAllows initialization as CLOCKSOURCE.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/clocksource/sh_tmu.c | 198 +++++++++++++++++++++++------------ 1 file changed, 132 insertions(+), 66 deletions(-)
drivers/clocksource/sh_tmu.c +132 -66
@@ -17,6 +17,8 @@#include <linux/irq.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h>
@@ -51,6 +53,7 @@ struct sh_tmu_channel {struct sh_tmu_device {struct platform_device *pdev; +struct device_node *np;void __iomem *mapbase;struct clk *clk;
@@ -65,6 +68,7 @@ struct sh_tmu_device {bool has_clockevent;bool has_clocksource; +const char *name; };#define TSTR -1/* shared register */
@@ -148,8 +152,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)/* enable clock */ ret =clk_enable (ch->tmu->clk);if (ret) { -dev_err (&ch->tmu->pdev->dev,"ch%u: cannot enable clock\n" , - ch->index); +pr_err ("%s ch%u: cannot enable clock\n" , + ch->tmu->name, ch->index);return ret; }
@@ -174,9 +178,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch)if (ch->enable_count++ >0 )return 0 ; -pm_runtime_get_sync (&ch->tmu->pdev->dev); -dev_pm_syscore_device (&ch->tmu->pdev->dev, true); - +if (ch->tmu->pdev) { +pm_runtime_get_sync (&ch->tmu->pdev->dev); +dev_pm_syscore_device (&ch->tmu->pdev->dev, true); + }return __sh_tmu_enable (ch); }
@@ -202,8 +207,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch)__sh_tmu_disable (ch); -dev_pm_syscore_device (&ch->tmu->pdev->dev, false); -pm_runtime_put (&ch->tmu->pdev->dev); +if (ch->tmu->pdev) { +dev_pm_syscore_device (&ch->tmu->pdev->dev, false); +pm_runtime_put (&ch->tmu->pdev->dev); + } } static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
@@ -245,7 +252,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)return IRQ_HANDLED ; } -static struct sh_tmu_channel *cs_to_sh_tmu (struct clocksource *cs) +static inline struct sh_tmu_channel *cs_to_sh_tmu (struct clocksource *cs) { return container_of(cs, struct sh_tmu_channel, cs); }
@@ -292,7 +299,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource *cs)if (--ch->enable_count ==0 ) {__sh_tmu_disable (ch); -dev_pm_genpd_suspend (&ch->tmu->pdev->dev); +if (ch->tmu->pdev) +dev_pm_genpd_suspend (&ch->tmu->pdev->dev); } }
@@ -304,7 +312,8 @@ static void sh_tmu_clocksource_resume(struct clocksource *cs)return ;if (ch->enable_count++ ==0 ) { -dev_pm_genpd_resume (&ch->tmu->pdev->dev); +if (ch->tmu->pdev) +dev_pm_genpd_resume (&ch->tmu->pdev->dev);__sh_tmu_enable (ch); } }
@@ -324,14 +333,14 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, cs->mask =CLOCKSOURCE_MASK (32 ); cs->flags =CLOCK_SOURCE_IS_CONTINUOUS ; -dev_info (&ch->tmu->pdev->dev,"ch%u: used as clock source\n" , - ch->index); +pr_info ("%s ch%u: used as clock source\n" , + ch->tmu->name, ch->index);clocksource_register_hz (cs, ch->tmu->rate);return 0 ; } -static struct sh_tmu_channel *ced_to_sh_tmu (struct clock_event_device *ced) +static inline struct sh_tmu_channel *ced_to_sh_tmu (struct clock_event_device *ced) { return container_of(ced, struct sh_tmu_channel, ced); }
@@ -364,8 +373,8 @@ static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,if (clockevent_state_oneshot (ced) ||clockevent_state_periodic (ced))sh_tmu_disable (ch); -dev_info (&ch->tmu->pdev->dev,"ch%u: used for %s clock events\n" , - ch->index, periodic ?"periodic" :"oneshot" ); +pr_info ("%s ch%u: used for %s clock events\n" , + ch->tmu->name, ch->index, periodic ?"periodic" :"oneshot" );sh_tmu_clock_event_start (ch, periodic);return 0 ; }
@@ -417,20 +426,22 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, ced->set_state_shutdown = sh_tmu_clock_event_shutdown; ced->set_state_periodic = sh_tmu_clock_event_set_periodic; ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; - ced->suspend = sh_tmu_clock_event_suspend; - ced->resume = sh_tmu_clock_event_resume; +if (ch->tmu->pdev) { + ced->suspend = sh_tmu_clock_event_suspend; + ced->resume = sh_tmu_clock_event_resume; + } -dev_info (&ch->tmu->pdev->dev,"ch%u: used for clock events\n" , - ch->index); +pr_info ("%s ch%u: used for clock events\n" , + ch->tmu->name, ch->index);clockevents_config_and_register (ced, ch->tmu->rate,0x300 ,0xffffffff ); ret =request_irq (ch->irq, sh_tmu_interrupt,IRQF_TIMER |IRQF_IRQPOLL |IRQF_NOBALANCING , -dev_name (&ch->tmu->pdev->dev), ch); + ch->tmu->name, ch);if (ret) { -dev_err (&ch->tmu->pdev->dev,"ch%u: failed to request irq %d\n" , - ch->index, ch->irq); +pr_err ("%s ch%u: failed to request irq %d\n" , + ch->tmu->name, ch->index, ch->irq);return ; } }
@@ -465,28 +476,36 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,else ch->base = tmu->mapbase +8 + ch->index *12 ; - ch->irq =platform_get_irq (tmu->pdev, index); +if (tmu->np) + ch->irq =of_irq_get (tmu->np, index); +else if (tmu->pdev) + ch->irq =platform_get_irq (tmu->pdev, index); +if (ch->irq <0 )return ch->irq; ch->cs_enabled = false; ch->enable_count =0 ; -return sh_tmu_register (ch,dev_name (&tmu->pdev->dev), - clockevent, clocksource); +return sh_tmu_register (ch, tmu->name, clockevent, clocksource); }static int sh_tmu_map_memory (struct sh_tmu_device *tmu) {struct resource *res; - res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); -if (!res) { -dev_err (&tmu->pdev->dev,"failed to get I/O memory\n" ); -return -ENXIO ; +if (tmu->pdev) { + res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); +if (!res) { +pr_err ("sh_tmu failed to get I/O memory\n" ); +return -ENXIO ; + } + + tmu->mapbase =ioremap (res->start,resource_size (res)); } +if (tmu->np) + tmu->mapbase =of_iomap (tmu->np,0 ); - tmu->mapbase =ioremap (res->start,resource_size (res));if (tmu->mapbase ==NULL )return -ENXIO ;
@@ -495,53 +514,25 @@ static int sh_tmu_map_memory(struct sh_tmu_device *tmu)static int sh_tmu_parse_dt (struct sh_tmu_device *tmu) { -struct device_node *np = tmu->pdev->dev.of_node; - tmu->model =SH_TMU ; tmu->num_channels =3 ; -of_property_read_u32 (np,"#renesas,channels" , &tmu->num_channels); +of_property_read_u32 (tmu->np,"#renesas,channels" , &tmu->num_channels);if (tmu->num_channels !=2 && tmu->num_channels !=3 ) { -dev_err (&tmu->pdev->dev,"invalid number of channels %u\n" , - tmu->num_channels); +pr_err ("%s: invalid number of channels %u\n" , + tmu->name, tmu->num_channels);return -EINVAL ; }return 0 ; } -static int sh_tmu_setup (struct sh_tmu_device *tmu,struct platform_device *pdev) +static int sh_tmu_setup (struct sh_tmu_device *tmu) {unsigned int i;int ret; - tmu->pdev = pdev; - -raw_spin_lock_init (&tmu->lock); - -if (IS_ENABLED (CONFIG_OF ) && pdev->dev.of_node) { - ret =sh_tmu_parse_dt (tmu); -if (ret <0 ) -return ret; - }else if (pdev->dev.platform_data) { -const struct platform_device_id *id = pdev->id_entry; -struct sh_timer_config *cfg = pdev->dev.platform_data; - - tmu->model = id->driver_data; - tmu->num_channels =hweight8 (cfg->channels_mask); - }else { -dev_err (&tmu->pdev->dev,"missing platform data\n" ); -return -ENXIO ; - } - -/* Get hold of clock. */ - tmu->clk =clk_get (&tmu->pdev->dev,"fck" ); -if (IS_ERR (tmu->clk)) { -dev_err (&tmu->pdev->dev,"cannot get clock\n" ); -return PTR_ERR (tmu->clk); - } - ret =clk_prepare (tmu->clk);if (ret <0 ) goto err_clk_put;
@@ -557,7 +548,7 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)/* Map the memory resource. */ ret =sh_tmu_map_memory (tmu);if (ret <0 ) { -dev_err (&tmu->pdev->dev,"failed to remap I/O memory\n" ); +pr_err ("%s: failed to remap I/O memory\n" , tmu->name); goto err_clk_unprepare; }
@@ -580,8 +571,6 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) goto err_unmap; } -platform_set_drvdata (pdev, tmu); -return 0 ; err_unmap:
@@ -594,6 +583,40 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)return ret; } +static int sh_tmu_setup_pdev (struct sh_tmu_device *tmu,struct platform_device *pdev) +{ +int ret; + + tmu->pdev = pdev; + +raw_spin_lock_init (&tmu->lock); + +if (IS_ENABLED (CONFIG_OF ) && pdev->dev.of_node) { + tmu->np = pdev->dev.of_node; + ret =sh_tmu_parse_dt (tmu); +if (ret <0 ) +return ret; + }else if (pdev->dev.platform_data) { +const struct platform_device_id *id = pdev->id_entry; +struct sh_timer_config *cfg = pdev->dev.platform_data; + + tmu->model = id->driver_data; + tmu->num_channels =hweight8 (cfg->channels_mask); + }else { +dev_err (&tmu->pdev->dev,"missing platform data\n" ); +return -ENXIO ; + } + + tmu->name =dev_name (&pdev->dev); + tmu->clk =clk_get (&tmu->pdev->dev,"fck" ); +if (IS_ERR (tmu->clk)) { +dev_err (&tmu->pdev->dev,"cannot get clock\n" ); +return PTR_ERR (tmu->clk); + } + +return sh_tmu_setup (tmu); +} +static int sh_tmu_probe (struct platform_device *pdev) {struct sh_tmu_device *tmu =platform_get_drvdata (pdev);
@@ -613,12 +636,13 @@ static int sh_tmu_probe(struct platform_device *pdev)if (tmu ==NULL )return -ENOMEM ; - ret =sh_tmu_setup (tmu, pdev); + ret =sh_tmu_setup_pdev (tmu, pdev);if (ret) {kfree (tmu);pm_runtime_idle (&pdev->dev);return ret; } +platform_set_drvdata (pdev, tmu);if (is_sh_early_platform_device (pdev))return 0 ;
@@ -632,6 +656,47 @@ static int sh_tmu_probe(struct platform_device *pdev)return 0 ; } +static int sh_tmu_setup_of (struct sh_tmu_device *tmu,struct device_node *np) +{ +int ret; + + tmu->np = np; +raw_spin_lock_init (&tmu->lock); + + ret =sh_tmu_parse_dt (tmu); +if (ret <0 ) +return ret; + + tmu->clk =of_clk_get (np,0 ); + tmu->name =of_node_full_name (np); + +if (IS_ERR (tmu->clk)) { +pr_err ("%pOF: cannot get clock\n" , np); +return PTR_ERR (tmu->clk); + } + +return sh_tmu_setup (tmu); +} + +static int __init sh_tmu_of_register (struct device_node *np) +{ +struct sh_tmu_device *tmu; +int ret; + + tmu =kzalloc (sizeof (*tmu),GFP_KERNEL ); +if (tmu ==NULL ) +return -ENOMEM ; + + ret =sh_tmu_setup_of (tmu, np); +if (ret) { +kfree (tmu); +pr_warn ("%pOF: Timer register failed (%d)" , np, ret); + }else +of_node_set_flag (np,OF_POPULATED ); + +return ret; +} +static const struct platform_device_id sh_tmu_id_table[] = { {"sh-tmu" ,SH_TMU }, {"sh-tmu-sh3" ,SH_TMU_SH3 },
@@ -665,6 +730,7 @@ static void __exit sh_tmu_exit(void)platform_driver_unregister (&sh_tmu_device_driver); } +TIMER_OF_DECLARE (sh_tmu,"renesas,tmu" , sh_tmu_of_register);#ifdef CONFIG_SUPERH sh_early_platform_init ("earlytimer" , &sh_tmu_device_driver);#endif
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v8 08/36] clocksource: sh_tmu: CLOCKSOURCE support.
Quoted 1 line · Yoshinori Sato
Allows initialization as CLOCKSOURCE.
...
drivers/clocksource/sh_tmu.c static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, · line 377
Quoted 4 lines
drivers/clocksource/sh_tmu.c +2
-2-dev_info (&ch->tmu->pdev->dev,"ch%u: used for %s clock events\n" , - ch->index, periodic ?"periodic" :"oneshot" ); +pr_info ("%s ch%u: used for %s clock events\n" , + ch->tmu->name, ch->index, periodic ?"periodic" :"oneshot" );
This is a step back change. We should use dev_*() if we have a device available. And I believe this is the case (at least for the previous boards), no?
...
drivers/clocksource/sh_tmu.c static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, · line 482
Quoted 5 lines
drivers/clocksource/sh_tmu.c +4
-1- ch->irq =platform_get_irq (tmu->pdev, index); +if (tmu->np) + ch->irq =of_irq_get (tmu->np, index); +else if (tmu->pdev) + ch->irq =platform_get_irq (tmu->pdev, index);
I found these changes counterproductive. Instead better to have up to three files to cover:
- the common code (library)
- the platform device support
- the pure OF support.
...
drivers/clocksource/sh_tmu.c static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, · line 504
Quoted 12 lines
drivers/clocksource/sh_tmu.c +8
-4- res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); -if (!res) { -dev_err (&tmu->pdev->dev,"failed to get I/O memory\n" ); -return -ENXIO ; +if (tmu->pdev) { + res =platform_get_resource (tmu->pdev,IORESOURCE_MEM ,0 ); +if (!res) { +pr_err ("sh_tmu failed to get I/O memory\n" ); +return -ENXIO ; + } + + tmu->mapbase =ioremap (res->start,resource_size (res));
devm_platform_ioremap_resource() should be good to have. Again, consider proper splitting.
drivers/clocksource/sh_tmu.c static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, · line 507
Quoted 3 lines
drivers/clocksource/sh_tmu.c +2
-0} +if (tmu->np) + tmu->mapbase =of_iomap (tmu->np,0 );
So, how many boards are non-OF compatible? Maybe makes sense to move them to OF and drop these platform code entirely from everywhere?
...
drivers/clocksource/sh_tmu.c static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) · line 611
Quoted 2 lines
drivers/clocksource/sh_tmu.c +2
-0+ tmu->name =dev_name (&pdev->dev); + tmu->clk =clk_get (&tmu->pdev->dev,"fck" );
devm_ approach can help a lot in case of platform device code.
drivers/clocksource/sh_tmu.c static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) · line 614
Quoted 3 lines
drivers/clocksource/sh_tmu.c +3
-0+if (IS_ERR (tmu->clk)) { +dev_err (&tmu->pdev->dev,"cannot get clock\n" ); +return PTR_ERR (tmu->clk);
return dev_err_probe() ?
Quoted 1 line
(quoted diff) +1
-0+ }
Signature · 2 lines
With Best Regards, Andy Shevchenko
Yoshinori Sato
maintainerPATCH v8 9/36 dt-binding: Add compatible SH7750 SoC
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Acked-by Rob Herring <[email protected]>
--- Documentation/devicetree/bindings/timer/renesas,tmu.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/timer/renesas,tmu.yaml +2 -0
@@ -40,6 +40,7 @@ properties: - renesas,tmu-r8a779f0 # R-Car S4-8 - renesas,tmu-r8a779g0 # R-Car V4H - renesas,tmu-r8a779h0 # R-Car V4M + - renesas,tmu-sh7750 # SH7750 - const: renesas,tmu reg:
@@ -97,6 +98,7 @@ if: - renesas,tmu-r8a7740 - renesas,tmu-r8a7778 - renesas,tmu-r8a7779 + - renesas,tmu-sh7750 then: required: - resets
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 10/36 sh: Common PCI Framework driver support.
In reply to Yoshinori SatoAdd New OF based PCI Host driver.
This driver conflicts some point in legacy PCI driver. To resolve the conflict, I made some changes to the legacy driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/include/asm/io.h | 6 ++++++ arch/sh/include/asm/pci.h | 4 ++++ arch/sh/kernel/iomap.c | 18 ++++++++++++++++++ 3 files changed, 28 insertions(+)
arch/sh/include/asm/io.h +6 -0
@@ -20,6 +20,7 @@#include <asm/page.h> #include <linux/pgtable.h> #include <asm-generic/iomap.h> +#include <linux/ioport.h> #define __IO_PREFIX generic#include <asm/io_generic.h>
@@ -310,4 +311,9 @@ unsigned long long poke_real_address_q(unsigned long long addr,int valid_phys_addr_range (phys_addr_t addr,size_t size);int valid_mmap_phys_addr_range (unsigned long pfn,size_t size); +#if defined(CONFIG_PCI ) && !defined(CONFIG_GENERIC_IOMAP ) +#define pci_remap_iospace pci_remap_iospace +int pci_remap_iospace (const struct resource *res,phys_addr_t phys_addr); +#endif +#endif /* __ASM_SH_IO_H */
arch/sh/include/asm/pci.h +4 -0
@@ -2,6 +2,7 @@#ifndef __ASM_SH_PCI_H#define __ASM_SH_PCI_H +#ifndef CONFIG_SH_DEVICE_TREE /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)return hose->need_domain_info; } +#else /* CONFIG_SH_DEVICE_TREE */ +#include <asm-generic/pci.h> +#endif #endif /* __ASM_SH_PCI_H */
arch/sh/kernel/iomap.c +18 -0
@@ -160,3 +160,21 @@ void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)mmio_outsl (addr, src, count); }EXPORT_SYMBOL (iowrite32_rep); + +#if defined(pci_remap_iospace) +int pci_remap_iospace (const struct resource *res,phys_addr_t phys_addr) +{ +unsigned long vaddr = res->start; + +if (!(res->flags &IORESOURCE_IO )) +return -EINVAL ; + +if (res->end >IO_SPACE_LIMIT ) +return -EINVAL ; + +__set_io_port_base (phys_addr); +return vmap_page_range (vaddr, vaddr +resource_size (res), phys_addr, +pgprot_device (PAGE_KERNEL )); +} +EXPORT_SYMBOL (pci_remap_iospace); +#endif
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 11/36 pci: pci-sh7751: Add SH7751 PCI driver
In reply to Yoshinori SatoRenesas SH7751 CPU Internal PCI Controller driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-sh7751.c | 335 ++++++++++++++++++++++++++++ 3 files changed, 345 insertions(+) create mode 100644 drivers/pci/controller/pci-sh7751.c
drivers/pci/controller/Kconfig +9 -0
@@ -353,6 +353,15 @@ config PCIE_XILINX_CPM Say 'Y' here if you want kernel support for the Xilinx Versal CPM host bridge. +config PCI_SH7751 + bool "Renesas SH7751 PCI controller" + depends on OF + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST + select PCI_HOST_COMMON + help + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI + Host Bridge driver. + source "drivers/pci/controller/cadence/Kconfig" source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig"
drivers/pci/controller/Makefile +1 -0
@@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o +obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/
drivers/pci/controller/pci-sh7751.c new file +335 -0
335 lines not on this page · raw message
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 12/36 dt-bindings: pci: pci-sh7751: Add SH7751 PCI
In reply to Yoshinori SatoRenesas SH7751 PCI Controller json-schema.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../bindings/pci/renesas,sh7751-pci.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml
Documentation/devicetree/bindings/pci/renesas,sh7751-pci.yaml new file +75 -0
@@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,sh7751-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 PCI Host controller + +maintainers: + - Yoshinori Sato <[email protected]> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: renesas,sh7751-pci + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: PCI Controller + - const: Bus State Controller + + interrupt-controller: true + + renesas,bus-arbit-round-robin: + $ref: /schemas/types.yaml#/definitions/flag + description: + Set DMA bus arbitration to round robin. + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-controller; + device_type = "pci"; + bus-range = <0 0>; + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x03000000 0 0xab000000 0xab000000 0 0x00000001>, + <0x02000000 0 0x0c000000 0x0c000000 0 0x04000000>, + <0x02000000 0 0xd0000000 0xd0000000 0 0x00000001>; + reg = <0xfe200000 0x0400>, + <0xff800000 0x0100>; + interrupt-map = <0x0000 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>; + interrupt-map-mask = <0x1800 0 0 7>; + };
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 13/36 dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
In reply to Yoshinori SatoSH7750 CPG Clock output define.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../bindings/clock/renesas,sh7750-cpg.yaml | 107 ++++++++++++++++++ include/dt-bindings/clock/sh7750-cpg.h | 26 +++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml create mode 100644 include/dt-bindings/clock/sh7750-cpg.h
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +107 -0
@@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7750/7751 Clock Pulse Generator (CPG) + +maintainers: + - Yoshinori Sato <[email protected]> + +description: + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It + includes PLLs, and variable ratio dividers. + + The CPG may also provide a Clock Domain for SoC devices, in combination with + the CPG Module Stop (MSTP) Clocks. + +properties: + compatible: + enum: + - renesas,sh7750-cpg # SH7750 + - renesas,sh7750s-cpg # SH775S + - renesas,sh7750r-cpg # SH7750R + - renesas,sh7751-cpg # SH7751 + - renesas,sh7751r-cpg # SH7751R + + reg: + minItems: 1 + maxItems: 2 + + reg-names: true + + clocks: + maxItems: 1 + + clock-names: + const: extal + + '#clock-cells': + const: 1 + + renesas,mode: + description: Board-specific settings of the MD[0-2] pins on SoC + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750-cpg + - renesas,sh7750s-cpg + then: + properties: + reg: + maxItems: 1 + reg-names: + items: + - const: FRQCR + + - if: + properties: + compatible: + contains: + enum: + - renesas,sh7750r-cpg + - renesas,sh7751-cpg + - renesas,sh7751r-cpg + then: + properties: + reg: + minItems: 2 + reg-names: + items: + - const: FRQCR + - const: CLKSTP00 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpg: clock-controller@ffc00000 { + compatible = "renesas,sh7751r-cpg"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + clocks = <&extal>; + clock-names = "extal"; + renesas,mode = <0>; + #clock-cells = <1>; + #power-domain-cells = <0>; + };
include/dt-bindings/clock/sh7750-cpg.h new file +26 -0
@@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +* +* Copyright 2023 Yoshinori Sato +*/ + +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__ +#define __DT_BINDINGS_CLOCK_SH7750_H__ + +#define SH7750_CPG_PLLOUT 0 + +#define SH7750_CPG_PCK 1 +#define SH7750_CPG_BCK 2 +#define SH7750_CPG_ICK 3 + +#define SH7750_MSTP_SCI 4 +#define SH7750_MSTP_RTC 5 +#define SH7750_MSTP_TMU012 6 +#define SH7750_MSTP_SCIF 7 +#define SH7750_MSTP_DMAC 8 +#define SH7750_MSTP_UBC 9 +#define SH7750_MSTP_SQ 10 +#define SH7750_CSTP_INTC 11 +#define SH7750_CSTP_TMU34 12 +#define SH7750_CSTP_PCIC 13 + +#endif
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v8 13/36] dt-bindings: clock: sh7750-cpg: Add renesas,sh7750-cpg header.
Hi Sato-san,
Thanks for the update!
Quoted 1 line · Yoshinori Sato
SH7750 CPG Clock output define.
(from my comments on v6 and v7) Please improve the patch description.
Quoted 6 lines
Signed-off-by Yoshinori Sato <[email protected]>Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +0
-0@@ -0,0 +1,107 @@
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml line 104
Quoted 10 lines
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +10
-0+examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpg: clock-controller@ffc00000 { + compatible = "renesas,sh7751r-cpg"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + clocks = <&extal>; + clock-names = "extal"; + renesas,mode = <0>;
Nit: please move "renesas,mode" last.
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml line 107
Quoted 3 lines
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml new file +3
-0+ #clock-cells = <1>; + #power-domain-cells = <0>; + };
Gr{oetje,eeting}s,
Geert
Signature · 5 lines
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Yoshinori Sato
maintainerPATCH v8 14/36 clk: Compatible with narrow registers
In reply to Yoshinori Satodivider and gate only support 32-bit registers.
Older hardware uses narrower registers, so I want to be able to handle 8-bit and 16-bit wide registers.
Seven clk_divider flags are used, and if I add flags for 8bit access and 16bit access, 8bit will not be enough, so I expanded it to u16.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/clk/clk-divider.c | 41 +++++++++++++++++++++--------- drivers/clk/clk-gate.c | 49 ++++++++++++++++++++++++++++++++---- include/linux/clk-provider.h | 20 ++++++++++++--- 3 files changed, 89 insertions(+), 21 deletions(-)
drivers/clk/clk-divider.c +29 -12
@@ -26,17 +26,34 @@* parent - fixed parent. No clk_set_parent support */ -static inline u32 clk_div_readl (struct clk_divider *divider) -{ +static inline u32 clk_div_read (struct clk_divider *divider) +{ +if (divider->flags &CLK_DIVIDER_REG_8BIT ) +return readb (divider->reg); +if (divider->flags &CLK_DIVIDER_REG_16BIT ) { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) { +return ioread16be (divider->reg); + }else { +return readw (divider->reg); + } + }if (divider->flags &CLK_DIVIDER_BIG_ENDIAN )return ioread32be (divider->reg);return readl (divider->reg); } -static inline void clk_div_writel (struct clk_divider *divider,u32 val) +static inline void clk_div_write (struct clk_divider *divider,u32 val) { -if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) +if (divider->flags &CLK_DIVIDER_REG_8BIT ) +writeb (val, divider->reg); +else if (divider->flags &CLK_DIVIDER_REG_16BIT ) { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) { +iowrite16be (val, divider->reg); + }else { +writew (val, divider->reg); + } + }else if (divider->flags &CLK_DIVIDER_BIG_ENDIAN )iowrite32be (val, divider->reg);else writel (val, divider->reg);
@@ -152,7 +169,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,struct clk_divider *divider =to_clk_divider (hw);unsigned int val; - val =clk_div_readl (divider) >> divider->shift; + val =clk_div_read (divider) >> divider->shift; val &=clk_div_mask (divider->width); return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -434,7 +451,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,if (divider->flags &CLK_DIVIDER_READ_ONLY ) {u32 val; - val =clk_div_readl (divider) >> divider->shift; + val =clk_div_read (divider) >> divider->shift; val &=clk_div_mask (divider->width); return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -455,7 +472,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw,if (divider->flags &CLK_DIVIDER_READ_ONLY ) {u32 val; - val =clk_div_readl (divider) >> divider->shift; + val =clk_div_read (divider) >> divider->shift; val &=clk_div_mask (divider->width); return divider_ro_determine_rate(hw, req, divider->table,
@@ -505,11 +522,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,if (divider->flags &CLK_DIVIDER_HIWORD_MASK ) { val =clk_div_mask (divider->width) << (divider->shift +16 ); }else { - val =clk_div_readl (divider); + val =clk_div_read (divider); val &= ~(clk_div_mask (divider->width) << divider->shift); } val |= (u32 )value << divider->shift; -clk_div_writel (divider, val); +clk_div_write (divider, val);if (divider->lock)spin_unlock_irqrestore (divider->lock, flags);
@@ -538,7 +555,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_divider *div;
@@ -610,7 +627,7 @@ EXPORT_SYMBOL_GPL(__clk_hw_register_divider);struct clk *clk_register_divider_table (struct device *dev,const char *name,const char *parent_name,unsigned long flags,void __iomem *reg,u8 shift,u8 width, -u8 clk_divider_flags,const struct clk_div_table *table, +u16 clk_divider_flags,const struct clk_div_table *table,spinlock_t *lock) {struct clk_hw *hw;
@@ -664,7 +681,7 @@ struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock) { struct clk_hw **ptr, *hw;
drivers/clk/clk-gate.c +44 -5
93 lines not on this page · raw message
include/linux/clk-provider.h +16 -4
@@ -508,6 +508,10 @@ void of_fixed_clk_setup(struct device_node *np);* CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. +* CLK_GATE_REG_8BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 8bit. +* CLK_GATE_REG_16BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_gate {struct clk_hw hw;
@@ -522,6 +526,8 @@ struct clk_gate {#define CLK_GATE_SET_TO_DISABLE BIT(0)#define CLK_GATE_HIWORD_MASK BIT(1)#define CLK_GATE_BIG_ENDIAN BIT(2) +#define CLK_GATE_REG_8BIT BIT(3) +#define CLK_GATE_REG_16BIT BIT(4)extern const struct clk_ops clk_gate_ops; struct clk_hw *__clk_hw_register_gate(struct device *dev,
@@ -675,13 +681,17 @@ struct clk_div_table {* CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. +* CLK_DIVIDER_REG_8BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 8bit. +* CLK_DIVIDER_REG_16BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_divider {struct clk_hw hw;void __iomem *reg;u8 shift;u8 width; -u8 flags; +u16 flags;const struct clk_div_table *table;spinlock_t *lock; };
@@ -697,6 +707,8 @@ struct clk_divider {#define CLK_DIVIDER_READ_ONLY BIT(5)#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)#define CLK_DIVIDER_BIG_ENDIAN BIT(7) +#define CLK_DIVIDER_REG_8BIT BIT(8) +#define CLK_DIVIDER_REG_16BIT BIT(9)extern const struct clk_ops clk_divider_ops;extern const struct clk_ops clk_divider_ro_ops;
@@ -726,18 +738,18 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock);struct clk_hw *__devm_clk_hw_register_divider (struct device *dev,struct device_node *np,const char *name,const char *parent_name,const struct clk_hw *parent_hw,const struct clk_parent_data *parent_data,unsigned long flags, -void __iomem *reg,u8 shift,u8 width,u8 clk_divider_flags, +void __iomem *reg,u8 shift,u8 width,u16 clk_divider_flags,const struct clk_div_table *table,spinlock_t *lock);struct clk *clk_register_divider_table (struct device *dev,const char *name,const char *parent_name,unsigned long flags,void __iomem *reg,u8 shift,u8 width, -u8 clk_divider_flags,const struct clk_div_table *table, +u16 clk_divider_flags,const struct clk_div_table *table,spinlock_t *lock);/** * clk_register_divider - register a divider clock with the clock framework
Signature · 1 line
2.39.2
Stephen Boyd
maintainerRe: [DO NOT MERGE v8 14/36] clk: Compatible with narrow registers
Quoting Yoshinori Sato (2024-05-29 01:01:00)
Quoted 19 lines
divider and gate only support 32-bit registers.
Older hardware uses narrower registers, so I want to be able to handle 8-bit and 16-bit wide registers.Seven
clk_dividerflags are used, and if I add flags for 8bit access and 16bit access, 8bit will not be enough, so I expanded it to u16.Signed-off-by Yoshinori Sato <[email protected]>--- drivers/clk/clk-divider.c | 41 +++++++++++++++++++++--------- drivers/clk/clk-gate.c | 49 ++++++++++++++++++++++++++++++++---- include/linux/clk-provider.h | 20 ++++++++++++--- 3 files changed, 89 insertions(+), 21 deletions(-)drivers/clk/clk-divider.c +0
-0
drivers/clk/clk-divider.c line 29
Quoted 6 lines
drivers/clk/clk-divider.c +1
-2@@ -26,17 +26,34 @@* parent - fixed parent. No clk_set_parent support */ -static inline u32 clk_div_readl (struct clk_divider *divider) -{ +static inline u32 clk_div_read (struct clk_divider *divider)
Please don't change the name. The 'l' is for the return type, u32, which is not changed.
Quoted 8 lines
drivers/clk/clk-divider.c +8
-0+{ +if (divider->flags &CLK_DIVIDER_REG_8BIT ) +return readb (divider->reg); +if (divider->flags &CLK_DIVIDER_REG_16BIT ) { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) { +return ioread16be (divider->reg); + }else { +return readw (divider->reg);
drivers/clk/clk-divider.c line 46
Quoted 10 lines
drivers/clk/clk-divider.c +3
-1+ } + }if (divider->flags &CLK_DIVIDER_BIG_ENDIAN )return ioread32be (divider->reg);return readl (divider->reg); } -static inline void clk_div_writel (struct clk_divider *divider,u32 val) +static inline void clk_div_write (struct clk_divider *divider,u32 val)
Same comment.
Quoted 30 lines
drivers/clk/clk-divider.c +9
-1{ -if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) +if (divider->flags &CLK_DIVIDER_REG_8BIT ) +writeb (val, divider->reg); +else if (divider->flags &CLK_DIVIDER_REG_16BIT ) { +if (divider->flags &CLK_DIVIDER_BIG_ENDIAN ) { +iowrite16be (val, divider->reg); + }else { +writew (val, divider->reg); + } + }else if (divider->flags &CLK_DIVIDER_BIG_ENDIAN )iowrite32be (val, divider->reg);else writel (val, divider->reg);include/linux/clk-provider.h +4
-0@@ -508,6 +508,10 @@ void of_fixed_clk_setup(struct device_node *np);* CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. +* CLK_GATE_REG_8BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 8bit. +* CLK_GATE_REG_16BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_gate {struct clk_hw hw;
include/linux/clk-provider.h struct clk_gate { · line 530
Quoted 5 lines
include/linux/clk-provider.h +2
-0@@ -522,6 +526,8 @@ struct clk_gate {#define CLK_GATE_SET_TO_DISABLE BIT(0)#define CLK_GATE_HIWORD_MASK BIT(1)#define CLK_GATE_BIG_ENDIAN BIT(2) +#define CLK_GATE_REG_8BIT BIT(3) +#define CLK_GATE_REG_16BIT BIT(4)
Please add kunit tests for the gate at least.
Quoted 32 lines
include/linux/clk-provider.h +7
-1extern const struct clk_ops clk_gate_ops; struct clk_hw *__clk_hw_register_gate(struct device *dev,@@ -675,13 +681,17 @@ struct clk_div_table {* CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. +* CLK_DIVIDER_REG_8BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 8bit. +* CLK_DIVIDER_REG_16BIT - by default 32bit register accesses are used for +* the gate register. Setting this flag makes the register accesses 16bit. */ struct clk_divider {struct clk_hw hw;void __iomem *reg;u8 shift;u8 width; -u8 flags; +u16 flags;const struct clk_div_table *table;spinlock_t *lock; };@@ -697,6 +707,8 @@ struct clk_divider {#define CLK_DIVIDER_READ_ONLY BIT(5)#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)#define CLK_DIVIDER_BIG_ENDIAN BIT(7) +#define CLK_DIVIDER_REG_8BIT BIT(8) +#define CLK_DIVIDER_REG_16BIT BIT(9)extern const struct clk_ops clk_divider_ops;extern const struct clk_ops clk_divider_ro_ops;
include/linux/clk-provider.h struct clk_hw *__clk_hw_register_divider(struct device *dev, · line 741
Quoted 5 lines
include/linux/clk-provider.h +1
-1@@ -726,18 +738,18 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags,
Let's just make this unsigned long for the flags. We don't need to specify a strict size like this for the callers.
include/linux/clk-provider.h struct clk_hw *__clk_hw_register_divider(struct device *dev, · line 747
Quoted 7 lines
include/linux/clk-provider.h +1
-1const struct clk_div_table *table, spinlock_t *lock); struct clk_hw *__devm_clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, const struct clk_parent_data *parent_data, unsigned long flags, - void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, + void __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags,
Same here.
include/linux/clk-provider.h struct clk_hw *__clk_hw_register_divider(struct device *dev, · line 752
Quoted 6 lines
include/linux/clk-provider.h +1
-1const struct clk_div_table *table, spinlock_t *lock); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags, const struct clk_div_table *table, + u16 clk_divider_flags, const struct clk_div_table *table,
Same here. Preferably do that in another patch too.
Yoshinori Sato
maintainerPATCH v8 15/36 clk: renesas: Add SH7750/7751 CPG Driver
In reply to Yoshinori SatoRenesas SH7750 and SH7751 series CPG driver. This driver supported frequency control and clock gating.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/clk/renesas/Kconfig | 13 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/clk-sh7750.c | 480 +++++++++++++++++++++++++++++++ 3 files changed, 491 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/renesas/clk-sh7750.c
drivers/clk/renesas/Kconfig +10 -3
@@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 config CLK_RENESAS - bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS - default y if ARCH_RENESAS + bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS && !SUPERH + default y if ARCH_RENESAS || SUPERH select CLK_EMEV2 if ARCH_EMEV2 select CLK_RZA1 if ARCH_R7S72100 select CLK_R7S9210 if ARCH_R7S9210
@@ -41,6 +41,9 @@ config CLK_RENESAS select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_SH73A0 if ARCH_SH73A0 + select CLK_SH7750 if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ + CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751 || \ + CPU_SUBTYPE_SH7751R if CLK_RENESAS
@@ -198,7 +201,6 @@ config CLK_SH73A0 select CLK_RENESAS_CPG_MSTP select CLK_RENESAS_DIV6 - # Family config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" if COMPILE_TEST
@@ -228,6 +230,11 @@ config CLK_RZG2L bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_SH7750 + bool "Renesas SH7750/7751 family clock support" if COMPILE_TEST + help + This is a driver for SH7750 / SH7751 CPG. + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST
drivers/clk/renesas/Makefile +1 -0
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o +obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o # Family obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
drivers/clk/renesas/clk-sh7750.c new file +480 -0
480 lines not on this page · raw message
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 16/36 irqchip: Add SH7751 INTC driver
In reply to Yoshinori SatoRenesas SH7751 Internal interrupt controller driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-sh7751.c | 282 +++++++++++++++++++++++++++ 3 files changed, 291 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
drivers/irqchip/Kconfig +8 -0
@@ -715,4 +715,12 @@ config SUNPLUS_SP7021_INTC chained controller, routing all interrupt source in P-Chip to the primary controller on C-Chip. +config RENESAS_SH7751_INTC + bool "Renesas SH7751 Interrupt Controller" + depends on SH_DEVICE_TREE || COMPILE_TEST + select IRQ_DOMAIN_HIERARCHY + help + Support for the Renesas SH7751 On-chip interrupt controller. + And external interrupt encoder for some targets. + endmenu
drivers/irqchip/Makefile +1 -0
@@ -124,3 +124,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o +obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
drivers/irqchip/irq-renesas-sh7751.c new file +282 -0
282 lines not on this page · raw message
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 17/36 dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema
In reply to Yoshinori SatoRenesas SH7751 INTC json-schema.
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Rob Herring <[email protected]>
--- .../renesas,sh7751-intc.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml new file +53 -0
@@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 Interrupt Controller + +maintainers: + - Yoshinori Sato <[email protected]> + +properties: + compatible: + items: + - const: renesas,sh7751-intc + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + reg: + maxItems: 2 + + reg-names: + items: + - const: ICR + - const: INTPRI00 + + renesas,icr-irlm: + $ref: /schemas/types.yaml#/definitions/flag + description: If true four independent interrupt requests mode (ICR.IRLM is 1). + +required: + - compatible + - reg + - reg-names + - '#interrupt-cells' + - interrupt-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/renesas,sh7751-intc.h> + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + reg = <0xffd00000 14>, <0xfe080000 128>; + reg-names = "ICR", "INTPRI00"; + #interrupt-cells = <1>; + interrupt-controller; + }; +...
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 18/36 irqchip: SH7751 external interrupt encoder with enable gate.
In reply to Yoshinori SatoSH7751 have 15 level external interrupt.
It is typically connected to the CPU through a priority encoder that can suppress requests.
This driver provides a way to control those hardware with irqchip.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-renesas-sh7751irl.c | 221 ++++++++++++++++++++++++ 3 files changed, 230 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
drivers/irqchip/Kconfig +7 -0
@@ -723,4 +723,11 @@ config RENESAS_SH7751_INTC Support for the Renesas SH7751 On-chip interrupt controller. And external interrupt encoder for some targets. +config RENESAS_SH7751IRL_INTC + bool "Renesas SH7751 based target IRL encoder support." + depends on RENESAS_SH7751_INTC + help + Support for External Interrupt encoder + on the some Renesas SH7751 based target. + endmenu
drivers/irqchip/Makefile +2 -0
@@ -125,3 +125,5 @@ obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o +obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o +
drivers/irqchip/irq-renesas-sh7751irl.c new file +221 -0
221 lines not on this page · raw message
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 19/36 dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema
In reply to Yoshinori SatoRenesas SH7751 external interrupt encoder json-schema.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../renesas,sh7751-irl-ext.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +57 -0
@@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 external interrupt encoder with enable regs. + +maintainers: + - Yoshinori Sato <[email protected]> + +description: + This is the generally used external interrupt encoder on SH7751 based boards. + +properties: + compatible: + items: + - const: renesas,sh7751-irl-ext + + reg: true + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + '#address-cells': + const: 0 + + renesas,set-to-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Invert enable registers. Setting the bit to 0 enables interrupts. + + renesas,enable-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + IRQ enable register bit mapping + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - renesas,enable-reg + +additionalProperties: false + +examples: + - | + r2dintc: interrupt-controller@a4000000 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>; + };
Signature · 1 line
2.39.2
Rob Herring
maintainerRe: [DO NOT MERGE v8 19/36] dt-bindings: interrupt-controller: renesas,sh7751-irl-ext: Add json-schema
Quoted 24 lines · Yoshinori Sato
Renesas SH7751 external interrupt encoder json-schema.
Signed-off-by Yoshinori Sato <[email protected]>--- .../renesas,sh7751-irl-ext.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yamlDocumentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +10
-0@@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH7751 external interrupt encoder with enable regs. + +maintainers: + - Yoshinori Sato <[email protected]>
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 20
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +10
-0+ +description: + This is the generally used external interrupt encoder on SH7751 based boards. + +properties: + compatible: + items: + - const: renesas,sh7751-irl-ext + + reg: true
Needs to define how many and what they are.
Quoted 6 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +6
-0+ + interrupt-controller: true + + '#interrupt-cells': + const: 2 +
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 36
Quoted 10 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +10
-0+ '#address-cells': + const: 0 + + renesas,set-to-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Invert enable registers. Setting the bit to 0 enables interrupts. + + renesas,enable-reg: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: |
Don't need '|'.
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml line 37
Quoted 1 line
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +1
-0+ IRQ enable register bit mapping
This needs a better description and constraints? Number of entries in the array or values of the entries.
Quoted 23 lines
Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml new file +20
-0+ +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - renesas,enable-reg + +additionalProperties: false + +examples: + - | + r2dintc: interrupt-controller@a4000000 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>; + };Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 20/36 serial: sh-sci: fix SH4 OF support.
In reply to Yoshinori Sato- Separated RZ's earlycon initialization from normal SCIF.
- fix earlyprintk hung (NULL pointer reference).
- fix SERIAL_SH_SCI_EARLYCON enablement
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
--- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/tty/serial/Kconfig +1 -1
@@ -664,7 +664,7 @@ config SERIAL_SH_SCI_EARLYCON depends on SERIAL_SH_SCI=y select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON - default ARCH_RENESAS + default ARCH_RENESAS || SUPERH config SERIAL_SH_SCI_DMA bool "DMA support" if EXPERT
drivers/tty/serial/sh-sci.c +3 -3
@@ -2723,7 +2723,7 @@ static int sci_remap_port(struct uart_port *port)if (port->membase)return 0 ; -if (port->dev->of_node || (port->flags &UPF_IOREMAP )) { +if (dev_of_node (port->dev) || (port->flags &UPF_IOREMAP )) { port->membase =ioremap (port->mapbase, sport->reg_size);if (unlikely (!port->membase)) {dev_err (port->dev,"can't remap port#%d\n" , port->line);
@@ -3551,8 +3551,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,OF_EARLYCON_DECLARE (sci,"renesas,sci" , sci_early_console_setup);OF_EARLYCON_DECLARE (scif,"renesas,scif" , scif_early_console_setup); -OF_EARLYCON_DECLARE (scif,"renesas,scif-r7s9210" , rzscifa_early_console_setup); -OF_EARLYCON_DECLARE (scif,"renesas,scif-r9a07g044" , rzscifa_early_console_setup); +OF_EARLYCON_DECLARE (rzscifa,"renesas,scif-r7s9210" , rzscifa_early_console_setup); +OF_EARLYCON_DECLARE (rzscifa,"renesas,scif-r9a07g044" , rzscifa_early_console_setup);OF_EARLYCON_DECLARE (scifa,"renesas,scifa" , scifa_early_console_setup);OF_EARLYCON_DECLARE (scifb,"renesas,scifb" , scifb_early_console_setup);OF_EARLYCON_DECLARE (hscif,"renesas,hscif" , hscif_early_console_setup);
Signature · 1 line
2.39.2
John Paul Adrian Glaubitz
maintainerRe: [DO NOT MERGE v8 20/36] serial: sh-sci: fix SH4 OF support.
Hi Yoshinori,
Quoted 3 lines · Yoshinori Sato
- Separated RZ's earlycon initialization from normal SCIF.
- fix earlyprintk hung (NULL pointer reference).
- fixSERIAL_SH_SCI_EARLYCONenablement
I feel like this could actually be split into three patches.
Adrian
Quoted 44 lines
Signed-off-by Yoshinori Sato <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>--- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/sh-sci.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-)drivers/tty/serial/Kconfig +1
-1@@ -664,7 +664,7 @@ config SERIAL_SH_SCI_EARLYCON depends on SERIAL_SH_SCI=y select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON - default ARCH_RENESAS + default ARCH_RENESAS || SUPERH config SERIAL_SH_SCI_DMA bool "DMA support" if EXPERTdrivers/tty/serial/sh-sci.c +3
-3@@ -2723,7 +2723,7 @@ static int sci_remap_port(struct uart_port *port)if (port->membase)return 0 ; -if (port->dev->of_node || (port->flags &UPF_IOREMAP )) { +if (dev_of_node (port->dev) || (port->flags &UPF_IOREMAP )) { port->membase =ioremap (port->mapbase, sport->reg_size);if (unlikely (!port->membase)) {dev_err (port->dev,"can't remap port#%d\n" , port->line);@@ -3551,8 +3551,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,OF_EARLYCON_DECLARE (sci,"renesas,sci" , sci_early_console_setup);OF_EARLYCON_DECLARE (scif,"renesas,scif" , scif_early_console_setup); -OF_EARLYCON_DECLARE (scif,"renesas,scif-r7s9210" , rzscifa_early_console_setup); -OF_EARLYCON_DECLARE (scif,"renesas,scif-r9a07g044" , rzscifa_early_console_setup); +OF_EARLYCON_DECLARE (rzscifa,"renesas,scif-r7s9210" , rzscifa_early_console_setup); +OF_EARLYCON_DECLARE (rzscifa,"renesas,scif-r9a07g044" , rzscifa_early_console_setup);OF_EARLYCON_DECLARE (scifa,"renesas,scifa" , scifa_early_console_setup);OF_EARLYCON_DECLARE (scifb,"renesas,scifb" , scifb_early_console_setup);OF_EARLYCON_DECLARE (hscif,"renesas,hscif" , hscif_early_console_setup);
Signature · 4 lines
.''`. John Paul Adrian Glaubitz : :' : Debian Developer `. `' Physicist `- GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
Yoshinori Sato
maintainerPATCH v8 21/36 dt-bindings: serial: renesas,scif: Add scif-sh7751.
In reply to Yoshinori SatoAdd Renesas SH7751 SCIF.
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
--- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/serial/renesas,scif.yaml +1 -0
@@ -18,6 +18,7 @@ properties: - items: - enum: - renesas,scif-r7s72100 # RZ/A1H + - renesas,scif-sh7751 # SH7751 - const: renesas,scif # generic SCIF compatible UART - items:
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v8 21/36] dt-bindings: serial: renesas,scif: Add scif-sh7751.
Quoted 8 lines · Yoshinori Sato
Add Renesas SH7751 SCIF.
Signed-off-by Yoshinori Sato <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>--- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+)
Yoshinori Sato
maintainerPATCH v8 22/36 dt-bindings: display: smi,sm501: SMI SM501 binding json-schema
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- .../bindings/display/smi,sm501.yaml | 443 ++++++++++++++++++ 1 file changed, 443 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml
Documentation/devicetree/bindings/display/smi,sm501.yaml new file +443 -0
@@ -0,0 +1,443 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/smi,sm501.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Motion SM501 Mobile Multimedia Companion Chip + +maintainers: + - Yoshinori Sato <[email protected]> + +description: + Silicon Motion Inc, SM501 Companion Chip. + +definitions: + fb-flag: + $ref: /schemas/types.yaml#/definitions/string-array + description: Display initialize flags. + items: + anyOf: + - const: use-init-done + - const: disable-at-exit + - const: use-hwcursor + - const: use-hwaccel + - const: panel-no-fpen + - const: panel-no-vbiasen + - const: panel-inv-fpen + - const: panel-inv-vbiasen + maxItems: 8 + +properties: + compatible: + const: + smi,sm501 + + reg: + maxItems: 2 + description: + First entry - System Configuration registers + Second entry - IO space (Display Controller register) + + interrupts: + description: SM501 interrupt to the cpu should be described here. + + clocks: + minItems: 2 + + clock-names: + items: + - const: mclk + - const: m1xclk + + mode: + $ref: /schemas/types.yaml#/definitions/string + description: Select a video mode + + edid: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Verbatim EDID data block describing attached display. + Data from the detailed timing descriptor will be used to + program the display controller. + + smi,little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on big endian systems, to set different foreign endian. + smi,big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: available on little endian systems, to set different foreign endian. + + smi,swap-fb-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: swap framebuffer byteorder. + + route-crt-panel: + $ref: /schemas/types.yaml#/definitions/flag + description: Panel output merge to CRT. + + crt: + type: object + description: CRT output control + properties: + smi,flags: + $ref: "#/definitions/fb-flag" + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + panel: + type: object + description: Panel output control + properties: + smi,flags: + $ref: "#/definitions/fb-flag" + + bpp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Color depth + + smi,devices: + $ref: /schemas/types.yaml#/definitions/string-array + description: Select SM501 device functions. + items: + anyOf: + - const: usb-host + - const: usb-slave + - const: ssp0 + - const: ssp1 + - const: uart0 + - const: uart1 + - const: fbaccel + - const: ac97 + - const: i2s + minItems: 1 + maxItems: 9 + + smi,misc-timing-ex: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - Extend bus holding time. + enum: + - none + - "16" + - "32" + - "48" + - "64" + - "80" + - "96" + - "112" + - "128" + - "144" + - "160" + - "176" + - "192" + - "208" + - "224" + - "240" + + smi,misc-timing-xc: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - Xscale clock input select. + enum: + - internal-pll + - hclk + - gpio30 + + smi,misc-timing-usb-current: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - USB host current detection. + enum: + - disable + - enable + + smi,misc-timing-ssm1: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - System SDRAM Clock Select for PW Mode 1. + enum: + - "288" + - divider + + smi,misc-timing-sm1: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - SDRAM clock divider for PW mode 1. + enum: + - "1" + - "2" + - "3" + - "4" + - "6" + - "8" + - "12" + - "16" + - "24" + - "32" + - "48" + - "64" + - "96" + - "128" + - "192" + - "384" + + smi,misc-timing-ssm0: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - System SDRAM Clock Select for PW Mode 0. + enum: + - "288" + - divider + + smi,misc-timing-sm0: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - SDRAM clock divider for PW mode 0. + enum: + - "1" + - "2" + - "3" + - "4" + - "6" + - "8" + - "12" + - "16" + - "24" + - "32" + - "48" + - "64" + - "96" + - "128" + - "192" + - "384" + + smi,misc-timing-deb: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - 96MHz PLL debug control + enum: + - input-reference + - output + + smi,misc-timing-a: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - ACPI Control. + enum: + - no-acpi + - acpi + + smi,misc-timing-divider: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - Output Frequency Selection for Second PLL. + enum: + - "336" + - "288" + - "240" + - "192" + + smi,misc-timing-u: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - USB Host mode. + enum: + - normal + - simulation + + smi,misc-timing-delay: + $ref: /schemas/types.yaml#/definitions/string + description: Miscellaneous Timing - Delay time to latch read data for external SDRAM memory controller. + enum: + - none + - "0.5" + - "1.0" + - "1.5" + - "2.0" + - "2.5" + + smi,misc-control-pad: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - PCI Pad drive strength. + enum: + - "24" + - "12" + - "8" + + smi,misc-control-usbclk: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - USB Clcok Select. + enum: + - xtal + - "96" + - "48" + + smi,misc-control-ssp: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - UART1/SSP1 Select. + enum: + - uart1 + - ssp1 + + smi,misc-control-lat: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - 8051 Latch Enable for Address. + enum: + - disable + - enable + + smi,misc-control-fp: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - Flat Panel Data Select. + enum: + - "18" + - "24" + + smi,misc-control-freq: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - Crystal frequency select. + enum: + - "24" + - "12" + + smi,misc-control-refresh: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - Internal memory refresh control + enum: + - "8" + - "16" + - "32" + - "64" + + smi,misc-control-hold: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - BUS Hold time. + enum: + - fifo-empty + - "8" + - "16" + - "24" + - "32" + + smi,misc-control-sh: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - Renesas SuperH ready polarity. + enum: + - active-low + - active-high + + smi,misc-control-ii: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - Interrupt inverting. + enum: + - normal + - inverted + + smi,misc-control-pll: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - PLL clock count. + enum: + - disable + - enable + + smi,misc-control-gap: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - DAC Band Gap Control. + const: "0" + + smi,misc-control-dac: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - DAC Power control. + enum: + - disable + - enable + + smi,misc-control-mc: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - USB slave controller. + enum: + - cpu + - "8051" + + smi,misc-control-bl: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - CPU Master burst length. + enum: + - "1" + - "8" + + smi,misc-control-usb: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - USB port select. + enum: + - master + - slave + + smi,misc-control-vr: + $ref: /schemas/types.yaml#/definitions/string + description: Micellaneous Control - NEC VR Memory map select. + enum: + - "0x1e00000" + - "0x3e00000" + + gpio: + type: object + description: GPIO pin control + additionalProperties: false + patternProperties: + "^pin-[0-9]+$": + $ref: /schemas/types.yaml#/definitions/string + enum: + - ioport + - function + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + + +examples: + - | + display@10000000 { + compatible = "smi,sm501"; + reg = <0x10000000 0x03e00000 + 0x13e00000 0x00200000>; + interrupt-parent = <&r2dintc>; + interrupts = <4 0>; + clocks = <&mclk &m1xclk>; + clock-names = "mclk", "m1xclk"; + mode = "640x480-16@60"; + smi,little-endian; + smi,devices = "usb-host", "uart0"; + smi,swap-fb-endian; + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60 + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd]; + + smi,misc-timing-ex = "16"; + smi,misc-timing-xc = "internal-pll"; + smi,misc-timing-usb-current = "disable"; + smi,misc-control-pad = "24"; + smi,misc-control-usbclk = "xtal"; + smi,misc-control-sh = "active-low"; + + gpio { + pin-0 = "ioport"; + pin-1 = "function"; + }; + + crt { + smi,flags = "use-init-done", + "disable-at-exit", + "use-hwcursor", + "use-hwaccel"; + }; + + panel { + bpp = <16>; + smi,flags = "use-init-done", + "disable-at-exit", + "use-hwcursor", + "use-hwaccel"; + }; + };
Signature · 1 line
2.39.2
Rob Herring (Arm)
maintainerRe: [DO NOT MERGE v8 22/36] dt-bindings: display: smi,sm501: SMI SM501 binding json-schema
Quoted 6 lines · Yoshinori Sato
Signed-off-by Yoshinori Sato <[email protected]>--- .../bindings/display/smi,sm501.yaml | 443 ++++++++++++++++++ 1 file changed, 443 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/smi,sm501.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/smi,sm501.yaml: crt: Missing additionalProperties/unevaluatedProperties constraint /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/smi,sm501.yaml: panel: Missing additionalProperties/unevaluatedProperties constraint
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Yoshinori Sato
maintainerPATCH v8 23/36 mfd: sm501: Convert platform_data to OF property
In reply to Yoshinori SatoVarious parameters of SM501 can be set using platform_data, so parameters cannot be passed in the DeviceTree target. Expands the parameters set in platform_data so that they can be specified using DeviceTree properties.
Signed-off-by Yoshinori Sato <[email protected]>
--- drivers/mfd/sm501.c | 238 ++++++++++++++++++++++++++++++++++ drivers/video/fbdev/sm501fb.c | 87 +++++++++++++ 2 files changed, 325 insertions(+)
drivers/mfd/sm501.c +238 -0
@@ -20,6 +20,7 @@#include <linux/gpio/driver.h> #include <linux/gpio/machine.h> #include <linux/slab.h> +#include <linux/clk.h> #include <linux/sm501.h> #include <linux/sm501-regs.h>
@@ -82,6 +83,16 @@ struct sm501_devdata {unsigned int rev; }; +struct sm501_config_props_uint { +char *name; +u32 shift; +}; + +struct sm501_config_props_flag { +char *clr_name; +char *set_name; +u32 bit; +};#define MHZ (1000 * 1000)
@@ -1370,6 +1381,227 @@ static int sm501_init_dev(struct sm501_devdata *sm)return 0 ; } +#define FIELD_WIDTH 4 +struct dt_values { +char *name; +unsigned int offset; +unsigned int width; +char *val[(1 <<FIELD_WIDTH ) +1 ]; +}; + +#define fld (_name, _offset, _width, ...) \ + { \ + .name = _name, \ + .offset = _offset, \ + .width = _width, \ + .val = { __VA_ARGS__, NULL}, \ + } + +static const struct dt_values misc_timing[] = { +fld ("ex" ,28 ,4 , +"none" ,"16" ,"32" ,"48" ,"64" ,"80" ,"96" ,"112" , +"128" ,"144" ,"160" ,"176" ,"192" ,"208" ,"224" ,"240" ), +fld ("xc" ,24 ,2 ,"internal-pll" ,"hclk" ,"gpio30" ), +fld ("us" ,23 ,1 ,"disable" ,"enable" ), +fld ("ssm1" ,20 ,1 ,"288" ,"divider" ), +fld ("sm1" ,16 ,4 , +"1" ,"2" ,"4" ,"8" ,"16" ,"32" ,"64" ,"128" , +"3" ,"6" ,"12" ,"24" ,"48" ,"96" ,"192" ,"384" ), +fld ("ssm0" ,12 ,1 ,"288" ,"divider" ), +fld ("sm0" ,8 ,4 , +"1" ,"2" ,"4" ,"8" ,"16" ,"32" ,"64" ,"128" , +"3" ,"6" ,"12" ,"24" ,"48" ,"96" ,"192" ,"384" ), +fld ("deb" ,7 ,1 ,"input-reference" ,"output" ), +fld ("a" ,6 ,1 ,"no-acpi" ,"acpi" ), +fld ("divider" ,4 ,2 ,"336" ,"288" ,"240" ,"192" ), +fld ("u" ,3 ,1 ,"normal" ,"simulation" ), +fld ("delay" ,0 ,3 ,"none" ,"0.5" ,"1.0" ,"1.5" ,"2.0" ,"2.5" ), + { .name =NULL }, +}; + +static const struct dt_values misc_control[] = { +fld ("pad" ,30 ,2 ,"24" ,"12" ,"8" ), +fld ("usbclk" ,28 ,2 ,"xtal" ,"96" ,"48" ), +fld ("ssp" ,27 ,1 ,"uart1" ,"ssp1" ), +fld ("lat" ,26 ,1 ,"disable" ,"enable" ), +fld ("fp" ,25 ,1 ,"18" ,"24" ), +fld ("freq" ,24 ,1 ,"24" ,"12" ), +fld ("refresh" ,21 ,2 ,"8" ,"16" ,"32" ,"64" ), +fld ("hold" ,18 ,3 ,"fifo-empty" ,"8" ,"16" ,"24" ,"32" ), +fld ("sh" ,17 ,1 ,"active-low" ,"active-high" ), +fld ("ii" ,16 ,1 ,"normal" ,"inverted" ), +fld ("pll" ,15 ,1 ,"disable" ,"enable" ), +fld ("gap" ,13 ,2 ,"0" ), +fld ("dac" ,12 ,1 ,"enable" ,"disable" ), +fld ("mc" ,11 ,1 ,"cpu" ,"8051" ), +fld ("bl" ,10 ,8 ,"1" ), +fld ("usb" ,9 ,1 ,"master" ,"slave" ), +fld ("vr" ,4 ,1 ,"0x1e00000" ,"0x3e00000" ), + { .name =NULL }, +}; + +/* Read configuration values */ +static void sm501_of_read_config (struct device *dev,struct device_node *np, +const char *prefix, +const struct dt_values *values, +struct sm501_reg_init *ret) +{ +const char *name; +const char *val; +unsigned int i; +char key[64 ]; +u32 shift; +u32 width; +u32 mask; + + ret->mask = ~0 ; + ret->set =0 ; + +while (values->name) { +snprintf (key,sizeof (key),"%s-%s" , prefix, values->name); + name = values->name; + shift = values->offset; + width = values->width; + +if (of_property_read_string (np, key, &val) ==0 ) { + mask = (1 << width) -1 ; + mask = ~(mask << shift); + ret->mask &= mask; + i =0 ; +while (values->val[i]) { +if (strcmp (val, values->val[i]) ==0 ) { + ret->set |= i << shift; +break ; + } + i++; + } + } + values++; + } +} + +static void sm501_of_read_gpio (struct device *dev,struct device_node *np, +struct sm501_reg_init *hi,struct sm501_reg_init *low) +{ +struct device_node *gpio_node; +struct property *prop; +unsigned int pin_no; +const char *s; +int mode; +u64 mask; +u64 set; + + mask = ~0 ; + set =0 ; + gpio_node =of_get_child_by_name (np,"gpio" ); +if (gpio_node) { +for (prop = gpio_node->properties; prop; prop = prop->next) { + mode =-1 ; +if (sscanf (prop->name,"pin-%u" , &pin_no) ==1 ) { +of_property_read_string (gpio_node, prop->name, &s); +if (strcmp (s,"ioport" )) { + mode =0 ; + }else if (strcmp (s,"function" )) { + mode =1 ; + } + } +if (mode >=0 ) { + mask &= ~(1 << pin_no); + set |= mode << pin_no; + } + } + } +/* Bit48 - 54 is reserved */ + mask &= ~0x007f000000000000UL ; + set &= ~0x007f000000000000UL ; + + hi->set = set >>32 ; + low->set = set &0xffffffff ; + hi->mask = mask >>32 ; + low->mask = mask &0xffffffff ; +} + +/* Read device functions */ +static u32 sm501_read_devices (struct device *dev,struct device_node *np) +{ +static const char *const funcname[] = { +"usb-host" ,"usb-slave" ,"ssp0" ,"ssp1" , +"uart0" ,"uart1" ,"fbaccel" ,"ac97" , +"i2s" , + }; +struct property *prop; +unsigned int i; +const char *s; +u32 ret =0 ; + +of_property_for_each_string (np,"smi,devices" , prop, s) { +for (i =0 ; i <ARRAY_SIZE (funcname); i++) { +if (strcmp (s, funcname[i]) ==0 ) { + ret |=1 << i; + goto next; + } + } +dev_warn (dev,"Unknown device function '%s'" , s); +next: + } +if (!ret) +dev_warn (dev,"devices not defined. disable all functions." ); +return ret; +} + +/* Build platform_data from OF property */ +struct plat_dt { +struct sm501_platdata plat; +struct sm501_initdata init; +}; + +static int mclk_get (struct device_node *np,int index,unsigned long *out) +{ +struct clk *clk; + + clk =of_clk_get (np,0 ); +if (IS_ERR (clk)) +return PTR_ERR (clk); + *out =clk_get_rate (clk); +clk_put (clk); +return 0 ; +} + +static int sm501_parse_dt (struct sm501_devdata *sm,struct device_node *np) +{ +struct sm501_platdata *plat; +struct plat_dt *dt_p; +int ret; + + dt_p =devm_kzalloc (sm->dev,sizeof (*dt_p),GFP_KERNEL ); +if (!dt_p) +return -ENOMEM ; + + plat = &dt_p->plat; + plat->init = &dt_p->init; + + plat->init->devices =sm501_read_devices (sm->dev, np); + + ret =mclk_get (np,0 , &plat->init->mclk); +if (ret && ret != -ENOENT ) +return ret; + ret =mclk_get (np,0 , &plat->init->m1xclk); +if (ret && ret != -ENOENT ) +return ret; + +sm501_of_read_config (sm->dev, np,"misc-timing" , + misc_timing, &plat->init->misc_timing); +sm501_of_read_config (sm->dev, np,"misc-control" , + misc_control, &plat->init->misc_control); +if (IS_ENABLED (CONFIG_MFD_SM501_GPIO )) { +sm501_of_read_gpio (sm->dev, np, + &plat->init->gpio_high, + &plat->init->gpio_low); + } + sm->platdata = plat; +return 0 ; +} +static int sm501_plat_probe (struct platform_device *dev) {struct sm501_devdata *sm;
@@ -1406,6 +1638,12 @@ static int sm501_plat_probe(struct platform_device *dev) goto err_res; } +if (IS_ENABLED (CONFIG_OF ) && dev->dev.of_node) { + ret =sm501_parse_dt (sm, dev->dev.of_node); +if (ret) + goto err_res; + } +platform_set_drvdata (dev, sm); sm->regs =ioremap (sm->io_res->start,resource_size (sm->io_res));
drivers/video/fbdev/sm501fb.c +87 -0
99 lines not on this page · raw message
Signature · 1 line
2.39.2
Lee Jones
maintainerRe: [DO NOT MERGE v8 23/36] mfd: sm501: Convert platform_data to OF property
Quoted 92 lines · Yoshinori Sato
Various parameters of SM501 can be set using
platform_data, so parameters cannot be passed in the DeviceTree target. Expands the parameters set inplatform_dataso that they can be specified using DeviceTree properties.Signed-off-by Yoshinori Sato <[email protected]>--- drivers/mfd/sm501.c | 238 ++++++++++++++++++++++++++++++++++ drivers/video/fbdev/sm501fb.c | 87 +++++++++++++ 2 files changed, 325 insertions(+)drivers/mfd/sm501.c +59
-0@@ -20,6 +20,7 @@#include <linux/gpio/driver.h> #include <linux/gpio/machine.h> #include <linux/slab.h> +#include <linux/clk.h> #include <linux/sm501.h> #include <linux/sm501-regs.h> @@ -82,6 +83,16 @@ struct sm501_devdata {unsigned int rev; }; +struct sm501_config_props_uint { +char *name; +u32 shift; +}; + +struct sm501_config_props_flag { +char *clr_name; +char *set_name; +u32 bit; +};#define MHZ (1000 * 1000)@@ -1370,6 +1381,227 @@ static int sm501_init_dev(struct sm501_devdata *sm)return 0 ; } +#define FIELD_WIDTH 4 +struct dt_values { +char *name; +unsigned int offset; +unsigned int width; +char *val[(1 <<FIELD_WIDTH ) +1 ]; +}; + +#define fld (_name, _offset, _width, ...) \ + { \ + .name = _name, \ + .offset = _offset, \ + .width = _width, \ + .val = { __VA_ARGS__, NULL}, \ + } + +static const struct dt_values misc_timing[] = { +fld ("ex" ,28 ,4 , +"none" ,"16" ,"32" ,"48" ,"64" ,"80" ,"96" ,"112" , +"128" ,"144" ,"160" ,"176" ,"192" ,"208" ,"224" ,"240" ), +fld ("xc" ,24 ,2 ,"internal-pll" ,"hclk" ,"gpio30" ), +fld ("us" ,23 ,1 ,"disable" ,"enable" ), +fld ("ssm1" ,20 ,1 ,"288" ,"divider" ), +fld ("sm1" ,16 ,4 , +"1" ,"2" ,"4" ,"8" ,"16" ,"32" ,"64" ,"128" , +"3" ,"6" ,"12" ,"24" ,"48" ,"96" ,"192" ,"384" ), +fld ("ssm0" ,12 ,1 ,"288" ,"divider" ), +fld ("sm0" ,8 ,4 , +"1" ,"2" ,"4" ,"8" ,"16" ,"32" ,"64" ,"128" , +"3" ,"6" ,"12" ,"24" ,"48" ,"96" ,"192" ,"384" ), +fld ("deb" ,7 ,1 ,"input-reference" ,"output" ), +fld ("a" ,6 ,1 ,"no-acpi" ,"acpi" ), +fld ("divider" ,4 ,2 ,"336" ,"288" ,"240" ,"192" ), +fld ("u" ,3 ,1 ,"normal" ,"simulation" ), +fld ("delay" ,0 ,3 ,"none" ,"0.5" ,"1.0" ,"1.5" ,"2.0" ,"2.5" ), + { .name =NULL }, +}; + +static const struct dt_values misc_control[] = { +fld ("pad" ,30 ,2 ,"24" ,"12" ,"8" ), +fld ("usbclk" ,28 ,2 ,"xtal" ,"96" ,"48" ), +fld ("ssp" ,27 ,1 ,"uart1" ,"ssp1" ), +fld ("lat" ,26 ,1 ,"disable" ,"enable" ), +fld ("fp" ,25 ,1 ,"18" ,"24" ), +fld ("freq" ,24 ,1 ,"24" ,"12" ), +fld ("refresh" ,21 ,2 ,"8" ,"16" ,"32" ,"64" ), +fld ("hold" ,18 ,3 ,"fifo-empty" ,"8" ,"16" ,"24" ,"32" ), +fld ("sh" ,17 ,1 ,"active-low" ,"active-high" ),
drivers/mfd/sm501.c static int sm501_init_dev(struct sm501_devdata *sm) · line 1441
Quoted 10 lines
drivers/mfd/sm501.c +10
-0+fld ("ii" ,16 ,1 ,"normal" ,"inverted" ), +fld ("pll" ,15 ,1 ,"disable" ,"enable" ), +fld ("gap" ,13 ,2 ,"0" ), +fld ("dac" ,12 ,1 ,"enable" ,"disable" ), +fld ("mc" ,11 ,1 ,"cpu" ,"8051" ), +fld ("bl" ,10 ,8 ,"1" ), +fld ("usb" ,9 ,1 ,"master" ,"slave" ), +fld ("vr" ,4 ,1 ,"0x1e00000" ,"0x3e00000" ), + { .name = NULL }, +};
I've been avoiding this set for a while now!
I appreciate the amount of work that you've put into this, but this is a bit of a disaster. It's a hell of lot of over-complex infrastructure just to pull out some values from DT.
Forgive me if I have this wrong, but it looks like you're defining various structs then populating static versions with hard-coded offsets into DT arrays! Then you have a bunch of hoop-jumpy functions to firstly parse the offset-structs, then conduct look-ups to pull the final value which in turn gets shifted into an encoded variable ready for to write out to the registers. Bonkers.
What does 'timing' even mean in this context? Clocks?
What other devices require this kind of handling? Why is this device so different from all other supported devices to date? Instead of attempting to shoehorn this into a 20 year old driver, why not reshape it to bring it into alignment with how we do things today?
E.g. handle all clocking from the clock driver, all display settings (including timing?) from the display driver, etc.
Signature · 1 line
Lee Jones [李琼斯]
Yoshinori Sato
maintainerPATCH v8 24/36 dt-binding: sh: cpus: Add SH CPUs json-schema
In reply to Yoshinori SatoRenesas SH series and compatible ISA CPUs.
Signed-off-by Yoshinori Sato <[email protected]>
--- .../devicetree/bindings/sh/cpus.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml
Documentation/devicetree/bindings/sh/cpus.yaml new file +63 -0
@@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sh/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH CPUs + +maintainers: + - Yoshinori Sato <[email protected]> + +description: |+ + Definition of CPU core with Renesas SuperH and compatible instruction set. + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,sh2a + - renesas,sh3 + - renesas,sh4 + - renesas,sh4a + - jcore,j2 + - const: renesas,sh2 + - const: renesas,sh2 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + + device_type: + const: cpu + +required: + - compatible + - reg + - device_type + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; +...
Signature · 1 line
2.39.2
Rob Herring (Arm)
maintainerRe: [DO NOT MERGE v8 24/36] dt-binding: sh: cpus: Add SH CPUs json-schema
Quoted 8 lines · Yoshinori Sato
Renesas SH series and compatible ISA CPUs.
Signed-off-by Yoshinori Sato <[email protected]>--- .../devicetree/bindings/sh/cpus.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/sh/cpus.example.dtb: cpu@0: 'clock-names', 'dcache-line-size', 'dcache-size', 'icache-line-size', 'icache-size' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/sh/cpus.yaml#
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Yoshinori Sato
maintainerPATCH v8 25/36 dt-bindings: vendor-prefixes: Add iodata
In reply to Yoshinori SatoAdd IO DATA DEVICE INC.
https://www.iodata.com/
Signed-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -716,6 +716,8 @@ patternProperties: description: Inventec "^inversepath,.*": description: Inverse Path + "^iodata,.*": + description: IO DATA DEVICE Inc. "^iom,.*": description: Iomega Corporation "^irondevice,.*":
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v8 25/36] dt-bindings: vendor-prefixes: Add iodata
Hey,
Quoted 5 lines · Yoshinori Sato
Add IO DATA DEVICE INC.
https://www.iodata.com/Signed-off-by Yoshinori Sato <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>
This one is missing an ack:
https://lore.kernel.org/all/20240109-frying-robin-e0f3e83966eb@spud/
Thanks,
Conor.
Quoted 20 lines
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/vendor-prefixes.yaml +2
-0@@ -716,6 +716,8 @@ patternProperties: description: Inventec "^inversepath,.*": description: Inverse Path + "^iodata,.*": + description: IO DATA DEVICE Inc. "^iom,.*": description: Iomega Corporation "^irondevice,.*":Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 26/36 dt-bindings: ata: ata-generic: Add new targets
In reply to Yoshinori SatoAdded new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ata
Each boards have simple IDE Interface. Use ATA generic driver.
Signed-off-by Yoshinori Sato <[email protected]>
--- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/ata/ata-generic.yaml +2 -0
@@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg:
Signature · 1 line
2.39.2
Re: [DO NOT MERGE v8 26/36] dt-bindings: ata: ata-generic: Add new targets
Hey,
Quoted 7 lines · Yoshinori Sato
Added new ata-generic target.
- iodata,usl-5p-ata
- renesas,rts7751r2d-ataEach boards have simple IDE Interface. Use ATA generic driver.
Signed-off-by Yoshinori Sato <[email protected]>
Why do you keep dropping tags? Damien and I acked this back in v6 and Krzysztof reminded you in v7:
https://lore.kernel.org/all/06fdb2cf7927681acf3099b826390ef75ba321af.1704788539.git.ysato@users.sourceforge.jp/
https://lore.kernel.org/all/53f85cc2e124d1c2e7394458b73293d797817d6d.1712207606.git.ysato@users.sourceforge.jp/
Dropping the tags just leads to wasted time re-reviewing patches that already got approved. I don't see any valid reason to drop them on a trivial patch like this :/ Please check back to previous revisions and make sure that you picked up applicable tags.
Thanks,
Conor.
Quoted 20 lines
--- Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/ata/ata-generic.yaml +2
-0@@ -18,6 +18,8 @@ properties: - enum: - arm,vexpress-cf - fsl,mpc8349emitx-pata + - iodata,usl-5p-ata + - renesas,rts7751r2d-ata - const: ata-generic reg:Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 27/36 dt-bindings: soc: renesas: sh: Add SH7751 based target
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
Reviewed-by Rob Herring <[email protected]>
--- .../devicetree/bindings/soc/renesas/sh.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml
Documentation/devicetree/bindings/soc/renesas/sh.yaml new file +27 -0
@@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH Platform + +maintainers: + - Yoshinori Sato <[email protected]> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: SH7751R based platform + items: + - enum: + - renesas,rts7751r2d # Renesas SH4 2D graphics board + - iodata,landisk # LANDISK HDL-U + - iodata,usl-5p # USL-5P + - const: renesas,sh7751r + +additionalProperties: true + +...
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 28/36 sh: SH7751R SoC Internal peripheral definition dtsi.
In reply to Yoshinori SatoSH7751R internal peripherals device tree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/sh7751r.dtsi | 105 ++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 arch/sh/boot/dts/sh7751r.dtsi
arch/sh/boot/dts/sh7751r.dtsi new file +105 -0
@@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SH7751R SoC + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sh7750-cpg.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; + + extal: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&shintc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&extal>; + clock-names = "extal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + }; + + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xffd00000 20>, <0xfe080000 128>; + reg-names = "ICR", "INTPRI00"; + }; + + /* sci0 is rarely used, so it is not defined here. */ + scif1: serial@ffe80000 { + compatible = "renesas,scif-sh7751", "renesas,scif"; + reg = <0xffe80000 0x100>; + interrupts = <0x700>, + <0x720>, + <0x760>, + <0x740>; + interrupt-names = "eri", "rxi", "txi", "bri"; + clocks = <&cpg SH7750_MSTP_SCIF>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */ + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-sh7750", "renesas,tmu"; + reg = <0xffd80000 12>; + interrupts = <0x400>, + <0x420>, + <0x440>, + <0x460>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg SH7750_MSTP_TMU012>; + clock-names = "fck"; + power-domains = <&cpg>; + #renesas,channels = <3>; + }; + + pcic: pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + bus-range = <0 0>; + reg = <0xfe200000 0x0400>, + <0xff800000 0x0100>; + status = "disabled"; + }; + }; +};
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 29/36 sh: add RTS7751R2D Plus DTS
In reply to Yoshinori SatoRenesas RTS7751R2D Plus devicetree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/rts7751r2dplus.dts | 172 ++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
arch/sh/boot/dts/rts7751r2dplus.dts new file +172 -0
@@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Renesas RTS7751R2D Plus + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "sh7751r.dtsi" + +/ { + model = "Renesas RTS7715R2D Plus"; + compatible = "renesas,rts7751r2d", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + r2dintc: interrupt-controller@a4000000 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xa4000000 0x02>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + /* + * b15: 12 - TP + * b14: 9 - PCI INTA + * b13: 10 - PCI INTB + * b12: 3 - PCI INTC + * b11: 0 - PCI INTD + * b10: 4 - SM501 + * b9: 1 - CF IDE + * b8: 2 - CF CD + * b7: 8 - SDCARD + * b6: 5 - KEY + * b5: 6 - RTC ALARM + * b4: 7 - RTC T + * b3: unassigned + * b2: unassigned + * b1: unassigned + * b0: 11 -EXT + */ + renesas,enable-reg = <12 9 10 3 0 4 1 2 8 5 6 7 15 15 15 11>; + }; + + sm501: display@10000000 { + compatible = "smi,sm501"; + reg = <0x10000000 0x03e00000 + 0x13e00000 0x00200000>; + interrupt-parent = <&r2dintc>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + mode = "640x480-16@60"; + smi,little-endian; + smi,devices = "usb-host", "uart0"; + smi,swap-fb-endian; + #gpio-cells = <2>; + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00 + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60 + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd]; + + smi,misc-timing-ex = "16"; + smi,misc-timing-xc = "internal-pll"; + smi,misc-timing-usb-current = "disable"; + smi,misc-control-pad = "24"; + smi,misc-control-usbclk = "xtal"; + smi,misc-control-sh = "active-low"; + + gpio { + pin-0 = "ioport"; + pin-1 = "function"; + }; + + crt { + smi,flags = "use-init-done", + "disable-at-exit", + "use-hwcursor", + "use-hwaccel"; + }; + + panel { + bpp = <16>; + smi,flags = "use-init-done", + "disable-at-exit", + "use-hwcursor", + "use-hwaccel"; + }; + }; + + compact-flash@b4001000 { + compatible = "renesas,rts7751r2d-ata", "ata-generic"; + reg = <0xb4001000 0x0e>, <0xb400080c 2>; + reg-shift = <1>; + interrupt-parent = <&r2dintc>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + + flash@0 { + compatible = "cfi-flash"; + reg = <0x00000000 0x02000000>; + device-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00040000>; + }; + + partition@1 { + label = "Environemt"; + reg = <0x00040000 0x00040000>; + }; + + partition@2 { + label = "Kernel"; + reg = <0x00080000 0x001c0000>; + }; + + partition@3 { + label = "Flash_FS"; + reg = <0x00240000 0x00dc0000>; + }; + }; +}; + +&extal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x03000000 0 0xab000000 0xab000000 0 0x00000004>, + <0x02000000 0 0x0c000000 0x0c000000 0 0x04000000>, + <0x02000000 0 0xd0000000 0xd0000000 0 0x00000004>; + interrupt-map = <0x0000 0 0 1 &r2dintc 9 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 2 &r2dintc 10 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 3 &r2dintc 3 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 4 &r2dintc 0 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 1 &r2dintc 10 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 2 &r2dintc 3 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 3 &r2dintc 0 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 4 &r2dintc 9 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 1 &r2dintc 3 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 2 &r2dintc 0 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 3 &r2dintc 9 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 4 &r2dintc 10 IRQ_TYPE_LEVEL_LOW>; + interrupt-map-mask = <0x1800 0 0 7>; + status = "okay"; +};
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 30/36 sh: Add IO DATA LANDISK dts
In reply to Yoshinori SatoIO DATA DEVICE Inc. LANDISK HDL-U devicetree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/landisk.dts | 77 ++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/sh/boot/dts/landisk.dts
arch/sh/boot/dts/landisk.dts new file +77 -0
@@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the IO DATA DEVICE LANDISK + */ + +/dts-v1/; + +#include "sh7751r.dtsi" + +/ { + model = "IO DATA Device LANDISK"; + compatible = "iodata,landisk", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:9600n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + julianintc: interrupt-controller@b0000005 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xb0000005 0x01>; + interrupt-controller; + #interrupt-cells = <2>; + /* + * b7: Not assigned + * b6: Power switch + * b5: Not assigned + * b4: Not assigned + * b3: PCI-INTD + * b2: PCI-INTC + * b1: PCI-INTB + * b0: PCI-INTA + */ + renesas,enable-reg = <15 11 15 15 8 7 6 5>; + }; +}; + +&extal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x02000000 0 0x0c000000 0x0c000000 0 0x04000000>, + <0x02000000 0 0xd0000000 0xd0000000 0 0x00000004>; + interrupt-map = <0x0000 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>; + interrupt-map-mask = <0x1800 0 0 7>; + status = "okay"; +};
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 31/36 sh: Add IO DATA USL-5P dts
In reply to Yoshinori SatoIO DATA DEVICE Inc. USL-5P devicetree.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/usl-5p.dts | 85 +++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 arch/sh/boot/dts/usl-5p.dts
arch/sh/boot/dts/usl-5p.dts new file +85 -0
@@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the IO DATA DEVICE USL-5P + */ + +/dts-v1/; + +#include "sh7751r.dtsi" + +/ { + model = "IO-DATA Device USL-5P"; + compatible = "iodata,usl-5p", "renesas,sh7751r"; + + aliases { + serial0 = &scif1; + }; + + chosen { + stdout-path = "serial0:9600n8"; + }; + + memory@c000000 { + device_type = "memory"; + reg = <0x0c000000 0x4000000>; + }; + + julianintc: interrupt-controller@b0000005 { + compatible = "renesas,sh7751-irl-ext"; + reg = <0xb0000005 0x01>; + interrupt-controller; + #interrupt-cells = <2>; + /* + * b7: Button + * b6: Power switch + * b5: Compact Flash + * b4: ATA + * b3: PCI-INTD + * b2: PCI-INTC + * b1: PCI-INTB + * b0: PCI-INTA + */ + renesas,enable-reg = <12 11 10 9 8 7 6 5>; + }; + + compact-flash@b4000040 { + compatible = "iodata,usl-5p-ata", "ata-generic"; + reg = <0xb4000040 0x0e>, <0xb400002c 2>; + reg-shift = <1>; + interrupt-parent = <&julianintc>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&extal { + clock-frequency = <22222222>; +}; + +&cpg { + renesas,mode = <5>; +}; + +&scif1 { + status = "okay"; +}; + +&pcic { + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>, + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>; + dma-ranges = <0x02000000 0 0x0c000000 0x0c000000 0 0x04000000>, + <0x02000000 0 0xd0000000 0xd0000000 0 0x00000004>; + interrupt-map = <0x0000 0 0 1 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 2 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 3 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0000 0 0 4 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 1 &julianintc 6 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 2 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 3 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 4 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 1 &julianintc 7 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 2 &julianintc 8 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 3 &julianintc 5 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 4 &julianintc 6 IRQ_TYPE_LEVEL_LOW>; + interrupt-map-mask = <0x1800 0 0 7>; + status = "okay"; +};
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 32/36 sh: j2_mimas_v2.dts update
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- arch/sh/boot/dts/j2_mimas_v2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/sh/boot/dts/j2_mimas_v2.dts +1 -1
@@ -16,7 +16,7 @@ cpus { cpu@0 { device_type = "cpu"; - compatible = "jcore,j2"; + compatible = "jcore,j2", "renesas,sh2"; reg = <0>; clock-frequency = <50000000>; d-cache-size = <8192>;
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 33/36 sh: Add dtbs target support.
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
Reviewed-by Geert Uytterhoeven <[email protected]>
--- arch/sh/boot/dts/Makefile | 5 +++++ 1 file changed, 5 insertions(+)
arch/sh/boot/dts/Makefile +5 -0
@@ -1,2 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE)) + +dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 34/36 sh: RTS7751R2D Plus OF defconfig
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- arch/sh/configs/rts7751r2dplus-of_defconfig | 77 +++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig
arch/sh/configs/rts7751r2dplus-of_defconfig new file +77 -0
@@ -0,0 +1,77 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_PROFILING=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_ZERO_PAGE_OFFSET=0x00010000 +CONFIG_CMDLINE_BOOTLOADER=y +CONFIG_MODULES=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IPV6 is not set +CONFIG_PCI=y +CONFIG_HOTPLUG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_UEVENT_HELPER=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_PHYSMAP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_NETDEVICES=y +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SPI=y +CONFIG_SPI_SH_SCI=y +CONFIG_MFD_SM501=y +CONFIG_FB=y +CONFIG_FB_SH_MOBILE_LCDC=m +CONFIG_FB_SM501=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +# CONFIG_LOGO_SUPERH_MONO is not set +# CONFIG_LOGO_SUPERH_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=m +CONFIG_SND_YMFPCI=m +CONFIG_HID_GYRATION=y +CONFIG_HID_PANTHERLORD=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SUNPLUS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_R9701=y +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_MINIX_FS=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_FS=y
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 35/36 sh: LANDISK OF defconfig
In reply to Yoshinori SatoSigned-off-by Yoshinori Sato <[email protected]>
--- arch/sh/configs/landisk-of_defconfig | 102 +++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 arch/sh/configs/landisk-of_defconfig
arch/sh/configs/landisk-of_defconfig new file +102 -0
@@ -0,0 +1,102 @@ +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_KEXEC=y +CONFIG_CPU_SUBTYPE_SH7751R=y +CONFIG_MEMORY_START=0x0c000000 +CONFIG_SH_OF_BOARD=y +CONFIG_HEARTBEAT=y +CONFIG_CMDLINE_BOOTLOADER=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_ATALK=m +CONFIG_PCI=y +CONFIG_PCI_SH7751=y +CONFIG_PCCARD=y +CONFIG_YENTA=y +CONFIG_UEVENT_HELPER=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ATA=y +CONFIG_PATA_ARTOP=y +CONFIG_PATA_OF_PLATFORM=y +CONFIG_ATA_GENERIC=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_NETDEVICES=y +CONFIG_TUN=m +CONFIG_8139CP=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_HW_RANDOM=y +CONFIG_SOUND=m +CONFIG_HID_A4TECH=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GYRATION=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SUNPLUS=m +CONFIG_USB_HID=m +CONFIG_USB=y +CONFIG_USB_MON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_SISUSBVGA=m +CONFIG_RENESAS_SH7751_INTC=y +CONFIG_RENESAS_SH7751IRL_INTC=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_REISERFS_FS=y +CONFIG_ISO9660_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_ROMFS_FS=y +CONFIG_UFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFSD=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_INIT_STACK_NONE=y +CONFIG_CRC_T10DIF=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_FTRACE is not set +CONFIG_SH_STANDARD_BIOS=y
Signature · 1 line
2.39.2
Yoshinori Sato
maintainerPATCH v8 36/36 sh: j2_defconfig: update
In reply to Yoshinori SatoI've changed some symbols related to DeviceTree,
so let's take care of those changes.
Signed-off-by Yoshinori Sato <[email protected]>
--- arch/sh/configs/j2_defconfig | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-)
arch/sh/configs/j2_defconfig +3 -8
@@ -1,18 +1,15 @@ -CONFIG_SMP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_CPU_SUBTYPE_J2=y CONFIG_MEMORY_START=0x10000000 -CONFIG_MEMORY_SIZE=0x04000000 CONFIG_CPU_BIG_ENDIAN=y -CONFIG_SH_DEVICE_TREE=y -CONFIG_SH_JCORE_SOC=y +CONFIG_SH_OF_BOARD=y CONFIG_HZ_100=y +CONFIG_SMP=y CONFIG_CMDLINE_OVERWRITE=y CONFIG_CMDLINE="console=ttyUL0 earlycon" -CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_NET=y CONFIG_PACKET=y
@@ -21,7 +18,6 @@ CONFIG_INET=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_NETDEVICES=y -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_UARTLITE=y CONFIG_SERIAL_UARTLITE_CONSOLE=y CONFIG_I2C=y
@@ -30,8 +26,6 @@ CONFIG_SPI_JCORE=y CONFIG_WATCHDOG=y CONFIG_MMC=y CONFIG_MMC_SPI=y -CONFIG_CLKSRC_JCORE_PIT=y -CONFIG_JCORE_AIC=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
@@ -40,3 +34,4 @@ CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_UTF8=y +CONFIG_INIT_STACK_NONE=y
Signature · 1 line
2.39.2
Quoted 4 lines · Yoshinori Sato
This is an updated version of something I wrote about 7 years ago. Minimum support for R2D-plus and LANDISK.
I think R2D-1 will work if you add AX88796 to dts.
And board-specific functions and SCI's SPI functions are not supported.
I don't understand the point of this. It's marked "DO NOT MERGE", so what do you want me to do? I've posted comments several times and they've never been addressed, so I don't think there's any point in looking at this again:
https://lore.kernel.org/r/20240404134652.GA1910402@bhelgaas
Bjorn