PCIe RK3399 clock and reset using new helper functions
v6 cover PCIe RK3399 clock and reset using new helper functions
Following changes are used to reduce the code and used new clk_bulk and reset_control_bulk helper functions.
Additional to the PCie core controller changes added some new PHY changes to help improve and clean up the code.
Resend since last patch got missed.
Previous changes.
v5:
https://lore.kernel.org/all/[email protected]/
V4:
https://lore.kernel.org/all/[email protected]/
V3:
https://lore.kernel.org/all/[email protected]/
V2:
https://lore.kernel.org/all/[email protected]/
V1:
https://lore.kernel.org/all/[email protected]/
Anand Moon (3):
PCI: rockchip: Simplify clock handling by using clk_bulk*() function
PCI: rockchip: Simplify reset control handling by using
reset_control_bulk*() function
PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function
signature
Thanks
-Anand
drivers/pci/controller/pcie-rockchip.c | 219 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 35 ++-- 2 files changed, 61 insertions(+), 193 deletions(-)
base-commit: 8f602276d3902642fdc3429b548d73c745446601
Signature · 1 line
2.44.0
PATCH v6 1/3 PCI: rockchip: Simplify clock handling by using clk_bulk*() function
Refactor the clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for enabling and disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler.
---
v6: None.
v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the
clock names in driver.
v4: use dev_err_probe for error patch.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot.
--- drivers/pci/controller/pcie-rockchip.c | 65 +++----------------------- drivers/pci/controller/pcie-rockchip.h | 7 ++- 2 files changed, 10 insertions(+), 62 deletions(-)
drivers/pci/controller/pcie-rockchip.c +7 -58
@@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) "failed to get ep GPIO\n"); } - rockchip->aclk_pcie =devm_clk_get (dev,"aclk" ); -if (IS_ERR (rockchip->aclk_pcie)) { -dev_err (dev,"aclk clock not found\n" ); -return PTR_ERR (rockchip->aclk_pcie); - } - - rockchip->aclk_perf_pcie =devm_clk_get (dev,"aclk-perf" ); -if (IS_ERR (rockchip->aclk_perf_pcie)) { -dev_err (dev,"aclk_perf clock not found\n" ); -return PTR_ERR (rockchip->aclk_perf_pcie); - } - - rockchip->hclk_pcie =devm_clk_get (dev,"hclk" ); -if (IS_ERR (rockchip->hclk_pcie)) { -dev_err (dev,"hclk clock not found\n" ); -return PTR_ERR (rockchip->hclk_pcie); - } - - rockchip->clk_pcie_pm =devm_clk_get (dev,"pm" ); -if (IS_ERR (rockchip->clk_pcie_pm)) { -dev_err (dev,"pm clock not found\n" ); -return PTR_ERR (rockchip->clk_pcie_pm); - } + rockchip->num_clks =devm_clk_bulk_get_all (dev, &rockchip->clks); +if (rockchip->num_clks <0 ) +return dev_err_probe (dev, err,"failed to get clocks\n" );return 0 ; }
@@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)struct device *dev = rockchip->dev;int err; - err =clk_prepare_enable (rockchip->aclk_pcie); -if (err) { -dev_err (dev,"unable to enable aclk_pcie clock\n" ); -return err; - } - - err =clk_prepare_enable (rockchip->aclk_perf_pcie); -if (err) { -dev_err (dev,"unable to enable aclk_perf_pcie clock\n" ); - goto err_aclk_perf_pcie; - } - - err =clk_prepare_enable (rockchip->hclk_pcie); -if (err) { -dev_err (dev,"unable to enable hclk_pcie clock\n" ); - goto err_hclk_pcie; - } - - err =clk_prepare_enable (rockchip->clk_pcie_pm); -if (err) { -dev_err (dev,"unable to enable clk_pcie_pm clock\n" ); - goto err_clk_pcie_pm; - } + err =clk_bulk_prepare_enable (rockchip->num_clks, rockchip->clks); +if (err) +return dev_err_probe (dev, err,"failed to enable clocks\n" );return 0 ; - -err_clk_pcie_pm: -clk_disable_unprepare (rockchip->hclk_pcie); -err_hclk_pcie: -clk_disable_unprepare (rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: -clk_disable_unprepare (rockchip->aclk_pcie); -return err; }EXPORT_SYMBOL_GPL (rockchip_pcie_enable_clocks);
@@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data) {struct rockchip_pcie *rockchip = data; -clk_disable_unprepare (rockchip->clk_pcie_pm); -clk_disable_unprepare (rockchip->hclk_pcie); -clk_disable_unprepare (rockchip->aclk_perf_pcie); -clk_disable_unprepare (rockchip->aclk_pcie); +clk_bulk_disable_unprepare (rockchip->num_clks, rockchip->clks); }EXPORT_SYMBOL_GPL (rockchip_pcie_disable_clocks);
drivers/pci/controller/pcie-rockchip.h +3 -4
@@ -11,6 +11,7 @@#ifndef _PCIE_ROCKCHIP_H#define _PCIE_ROCKCHIP_H +#include <linux/clk.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h>
@@ -299,10 +300,8 @@ struct rockchip_pcie {struct reset_control *pm_rst;struct reset_control *aclk_rst;struct reset_control *pclk_rst; -struct clk *aclk_pcie; -struct clk *aclk_perf_pcie; -struct clk *hclk_pcie; -struct clk *clk_pcie_pm; +struct clk_bulk_data *clks; +int num_clks;struct regulator *vpcie12v;/* 12V power supply */ struct regulator *vpcie3v3;/* 3.3V power supply */ struct regulator *vpcie1v8;/* 1.8V power supply */
Signature · 1 line
2.44.0
Re: [PATCH v6 RESET 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function
Hi Anand,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-clock-handling-by-using-clk_bulk-function/20241007-022714 base: 8f602276d3902642fdc3429b548d73c745446601 patch link: https://lore.kernel.org/r/20241006182445.3713-2-linux.amoon%40gmail.com patch subject: [PATCH v6 RESET 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function config: loongarch-randconfig-r071-20241009 (https://download.01.org/0day-ci/archive/20241010/[email protected]/config) compiler: loongarch64-linux-gcc (GCC) 14.1.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]> | Reported-by: Dan Carpenter <[email protected]> | Closes: https://lore.kernel.org/r/[email protected]/
smatch warnings:drivers/pci/controller/pcie-rockchip.c:132 rockchip_pcie_parse_dt() warn: passing zero to 'dev_err_probe'
vim +/dev_err_probe +132 drivers/pci/controller/pcie-rockchip.c
964bac9455bee7 drivers/pci/host/pcie-rockchip.c Shawn Lin 2018-05-09 122 if (rockchip->is_rc) {
58adbfb3ebec46 drivers/pci/controller/pcie-rockchip.c Chen-Yu Tsai 2021-01-22 123 rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
840b7a5edf88fe drivers/pci/controller/pcie-rockchip.c Manivannan Sadhasivam 2024-04-16 124 GPIOD_OUT_LOW);
58adbfb3ebec46 drivers/pci/controller/pcie-rockchip.c Chen-Yu Tsai 2021-01-22 125 if (IS_ERR(rockchip->ep_gpio))
58adbfb3ebec46 drivers/pci/controller/pcie-rockchip.c Chen-Yu Tsai 2021-01-22 126 return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
58adbfb3ebec46 drivers/pci/controller/pcie-rockchip.c Chen-Yu Tsai 2021-01-22 127 "failed to get ep GPIO\n");
e77f847df54c6b drivers/pci/host/pcie-rockchip.c Shawn Lin 2016-09-03 128 }
e77f847df54c6b drivers/pci/host/pcie-rockchip.c Shawn Lin 2016-09-03 129
9a8ff91a0ee96b drivers/pci/controller/pcie-rockchip.c Anand Moon 2024-10-06 130 rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks);
9a8ff91a0ee96b drivers/pci/controller/pcie-rockchip.c Anand Moon 2024-10-06 131 if (rockchip->num_clks < 0)
9a8ff91a0ee96b drivers/pci/controller/pcie-rockchip.c Anand Moon 2024-10-06 @132 return dev_err_probe(dev, err, "failed to get clocks\n");
^^^Was intended to be rockchip->num_clks.
4816c4c7b82b55 drivers/pci/host/pcie-rockchip.c Shawn Lin 2016-12-07 133 964bac9455bee7 drivers/pci/host/pcie-rockchip.c Shawn Lin 2018-05-09 134 return 0; 4816c4c7b82b55 drivers/pci/host/pcie-rockchip.c Shawn Lin 2016-12-07 135 }
Signature · 2 lines
0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
PATCH v6 2/3 PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
In reply to Anand MoonRefactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the reset_control_bulk APIs, the reset handling for the core clocks reset unit becomes much simpler.
Spilt the reset controller in two groups as pre the RK3399 TRM. After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the rest reset simultaneously driver need to De-assert the reset pins simultionaly.
PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
---
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: use dev_err_probe in error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning
--- drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 49 insertions(+), 128 deletions(-)
drivers/pci/controller/pcie-rockchip.c +30 -121
@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)struct platform_device *pdev =to_platform_device (dev);struct device_node *node = dev->of_node;struct resource *regs; -int err; +int err, i;if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev,
@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)if (rockchip->link_gen <0 || rockchip->link_gen >2 ) rockchip->link_gen =2 ; - rockchip->core_rst =devm_reset_control_get_exclusive (dev,"core" ); -if (IS_ERR (rockchip->core_rst)) { -if (PTR_ERR (rockchip->core_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing core reset property in node\n" ); -return PTR_ERR (rockchip->core_rst); - } - - rockchip->mgmt_rst =devm_reset_control_get_exclusive (dev,"mgmt" ); -if (IS_ERR (rockchip->mgmt_rst)) { -if (PTR_ERR (rockchip->mgmt_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst =devm_reset_control_get_exclusive (dev, -"mgmt-sticky" ); -if (IS_ERR (rockchip->mgmt_sticky_rst)) { -if (PTR_ERR (rockchip->mgmt_sticky_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing mgmt-sticky reset property in node\n" ); -return PTR_ERR (rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst =devm_reset_control_get_exclusive (dev,"pipe" ); -if (IS_ERR (rockchip->pipe_rst)) { -if (PTR_ERR (rockchip->pipe_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pipe reset property in node\n" ); -return PTR_ERR (rockchip->pipe_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_PM_RSTS ; i++) + rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; - rockchip->pm_rst =devm_reset_control_get_exclusive (dev,"pm" ); -if (IS_ERR (rockchip->pm_rst)) { -if (PTR_ERR (rockchip->pm_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pm reset property in node\n" ); -return PTR_ERR (rockchip->pm_rst); - } + err =devm_reset_control_bulk_get_optional_exclusive (dev, +ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"cannot get the reset control\n" ); - rockchip->pclk_rst =devm_reset_control_get_exclusive (dev,"pclk" ); -if (IS_ERR (rockchip->pclk_rst)) { -if (PTR_ERR (rockchip->pclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing pclk reset property in node\n" ); -return PTR_ERR (rockchip->pclk_rst); - } +for (i =0 ; i <ROCKCHIP_NUM_CORE_RSTS ; i++) + rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i]; - rockchip->aclk_rst =devm_reset_control_get_exclusive (dev,"aclk" ); -if (IS_ERR (rockchip->aclk_rst)) { -if (PTR_ERR (rockchip->aclk_rst) != -EPROBE_DEFER ) -dev_err (dev,"missing aclk reset property in node\n" ); -return PTR_ERR (rockchip->aclk_rst); - } + err =devm_reset_control_bulk_get_optional_exclusive (dev, +ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"cannot get the reset control\n" );if (rockchip->is_rc) { rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
@@ -147,23 +115,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)int err, i;u32 regs; - err =reset_control_assert (rockchip->aclk_rst); -if (err) { -dev_err (dev,"assert aclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"assert pclk_rst err %d\n" , err); -return err; - } - - err =reset_control_assert (rockchip->pm_rst); -if (err) { -dev_err (dev,"assert pm_rst err %d\n" , err); -return err; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts); +if (err) +return dev_err_probe (dev, err,"reset bulk assert pm reset\n" );for (i =0 ; i <MAX_LANE_NUM ; i++) { err =phy_init (rockchip->phys[i]);
@@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } - err =reset_control_assert (rockchip->core_rst); -if (err) { -dev_err (dev,"assert core_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"assert mgmt_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"assert mgmt_sticky_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_assert (rockchip->pipe_rst); -if (err) { -dev_err (dev,"assert pipe_rst err %d\n" , err); - goto err_exit_phy; - } + err =reset_control_bulk_assert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts); +if (err) +return dev_err_probe (dev, err,"reset bulk assert core reset\n" );udelay (10 ); - err =reset_control_deassert (rockchip->pm_rst); -if (err) { -dev_err (dev,"deassert pm_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->aclk_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_PM_RSTS , + rockchip->pm_rsts);if (err) { -dev_err (dev,"deassert aclk_rst err %d\n" , err); - goto err_exit_phy; - } - - err =reset_control_deassert (rockchip->pclk_rst); -if (err) { -dev_err (dev,"deassert pclk_rst err %d\n" , err); +dev_err (dev,"reset bulk deassert pm err %d\n" , err); goto err_exit_phy; }
@@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)* Please don't reorder the deassert sequence of the following * four reset pins. */ - err =reset_control_deassert (rockchip->mgmt_sticky_rst); -if (err) { -dev_err (dev,"deassert mgmt_sticky_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->core_rst); + err =reset_control_bulk_deassert (ROCKCHIP_NUM_CORE_RSTS , + rockchip->core_rsts);if (err) { -dev_err (dev,"deassert core_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->mgmt_rst); -if (err) { -dev_err (dev,"deassert mgmt_rst err %d\n" , err); - goto err_power_off_phy; - } - - err =reset_control_deassert (rockchip->pipe_rst); -if (err) { -dev_err (dev,"deassert pipe_rst err %d\n" , err); +dev_err (dev,"reset bulk deassert core err %d\n" , err); goto err_power_off_phy; }return 0 ; + err_power_off_phy:while (i--)phy_power_off (rockchip->phys[i]);
drivers/pci/controller/pcie-rockchip.h +19 -7
@@ -15,6 +15,7 @@#include <linux/kernel.h> #include <linux/pci.h> #include <linux/pci-ecam.h> +#include <linux/reset.h> /* * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
@@ -288,18 +289,29 @@ (((c) << ((b) *8 +5 )) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_PM_RSTS ARRAY_SIZE(rockchip_pci_pm_rsts) +#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts) + +static const char *const rockchip_pci_pm_rsts[] = { +"pm" , +"pclk" , +"aclk" , +}; + +static const char *const rockchip_pci_core_rsts[] = { +"mgmt-sticky" , +"mgmt" , +"core" , +"pipe" , +}; +struct rockchip_pcie {void __iomem *reg_base;/* DT axi-base */ void __iomem *apb_base;/* DT apb-base */ bool legacy_phy;struct phy *phys[MAX_LANE_NUM ]; -struct reset_control *core_rst; -struct reset_control *mgmt_rst; -struct reset_control *mgmt_sticky_rst; -struct reset_control *pipe_rst; -struct reset_control *pm_rst; -struct reset_control *aclk_rst; -struct reset_control *pclk_rst; +struct reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS ]; +struct reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS ];struct clk_bulk_data *clks;int num_clks;struct regulator *vpcie12v;/* 12V power supply */
Signature · 1 line
2.44.0
Re: [PATCH v6 RESET 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
Quoted 33 lines · Anand Moon
Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the
reset_control_bulkAPIs, the reset handling for the core clocks reset unit becomes much simpler.Spilt the reset controller in two groups as pre the RK3399 TRM. After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the rest reset simultaneously driver need to De-assert the reset pins simultionaly.PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
Signed-off-by Anand Moon <[email protected]>---
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: usedev_err_probein error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning--- drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 49 insertions(+), 128 deletions(-)drivers/pci/controller/pcie-rockchip.c +0
-0
[...]
drivers/pci/controller/pcie-rockchip.c int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) · line 72
Quoted 10 lines
drivers/pci/controller/pcie-rockchip.c +1
-5@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)if (rockchip->link_gen <0 || rockchip->link_gen >2 ) rockchip->link_gen =2 ; - rockchip->core_rst =devm_reset_control_get_exclusive (dev,"core" ); - rockchip->mgmt_rst =devm_reset_control_get_exclusive (dev,"mgmt" ); - rockchip->mgmt_sticky_rst =devm_reset_control_get_exclusive (dev, - rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); - rockchip->pm_rst =devm_reset_control_get_exclusive (dev,"pm" ); + err = devm_reset_control_bulk_get_optional_exclusive(dev,
[...]
Why are the reset controls optional now? The commit message doesn't mention this change.
regards
Philipp
Re: [PATCH v6 RESET 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
Hi Philipp,
Thanks for your review comment.
Quoted 49 lines · Philipp Zabel
Quoted 33 lines · Anand Moon
Refactor the reset control handling in the Rockchip PCIe driver, introducing a more robust and efficient method for assert and deassert reset controller using reset_control_bulk*() API. Using the
reset_control_bulkAPIs, the reset handling for the core clocks reset unit becomes much simpler.Spilt the reset controller in two groups as pre the RK3399 TRM. After power up, the software driver should de-assert the reset of PCIe PHY, then wait the PLL locked by polling the status, if PLL
has locked, then can de-assert the rest reset simultaneously driver need to De-assert the reset pins simultionaly.PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
Signed-off-by Anand Moon <[email protected]>---
V6: Add reason for the split of the RESET pins.
v5: Fix the De-assert reset core as per the TRM
De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N simultaneously.
v4: usedev_err_probein error path.
v3: Fix typo in commit message, dropped reported by.
v2: Fix compilation error reported by Intel test robot
fixed checkpatch warning--- drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- drivers/pci/controller/pcie-rockchip.h | 26 +++-- 2 files changed, 49 insertions(+), 128 deletions(-)drivers/pci/controller/pcie-rockchip.c +0
-0[...]
Quoted 10 lines
drivers/pci/controller/pcie-rockchip.c +1
-5@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)if (rockchip->link_gen <0 || rockchip->link_gen >2 ) rockchip->link_gen =2 ; - rockchip->core_rst =devm_reset_control_get_exclusive (dev,"core" ); - rockchip->mgmt_rst =devm_reset_control_get_exclusive (dev,"mgmt" ); - rockchip->mgmt_sticky_rst =devm_reset_control_get_exclusive (dev, - rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); - rockchip->pm_rst =devm_reset_control_get_exclusive (dev,"pm" ); + err = devm_reset_control_bulk_get_optional_exclusive(dev,[...]
Quoted 3 lines
Why are the reset controls optional now? The commit message doesn't mention this change.
Oops, It should be devm_reset_control_bulk_get_exclusive(), I will update this in the next version.
Quoted 2 lines
regards
Philipp
Thanks
-Anand
PATCH v6 3/3 PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature
In reply to Anand MoonRefactor the rockchip_pcie_disable_clocks function to accept a struct rockchip_pcie pointer instead of a void pointer. This change improves type safety and code readability by explicitly specifying the expected data type.
---
v6: Fix the subject, add the missing () in the function name.
v5: Fix the commit message and add r-b Manivannan.
v4: None
v3: None
v2: None
--- drivers/pci/controller/pcie-rockchip.c | 3 +-- drivers/pci/controller/pcie-rockchip.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-)
drivers/pci/controller/pcie-rockchip.c +1 -2
@@ -269,9 +269,8 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) }EXPORT_SYMBOL_GPL (rockchip_pcie_enable_clocks); -void rockchip_pcie_disable_clocks (void *data) +void rockchip_pcie_disable_clocks (struct rockchip_pcie *rockchip) { -struct rockchip_pcie *rockchip = data;clk_bulk_disable_unprepare (rockchip->num_clks, rockchip->clks); }
drivers/pci/controller/pcie-rockchip.h +1 -1
@@ -347,7 +347,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip);int rockchip_pcie_get_phys (struct rockchip_pcie *rockchip);void rockchip_pcie_deinit_phys (struct rockchip_pcie *rockchip);int rockchip_pcie_enable_clocks (struct rockchip_pcie *rockchip); -void rockchip_pcie_disable_clocks (void *data); +void rockchip_pcie_disable_clocks (struct rockchip_pcie *rockchip);void rockchip_pcie_cfg_configuration_accesses (struct rockchip_pcie *rockchip,u32 type);
Signature · 1 line
2.44.0