Add driver support for Eswin EIC7700 SoC SATA Controller and PHY
Subsystems (3)
v5 cover Add driver support for Eswin EIC7700 SoC SATA Controller and PHY
This series depends on the config option patch [1].
[1] Https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20250929&id=ce2d00c6e192b588ddc3d1efb72b0ea00ab5538f
Updates:
v5 -> v4:
- eswin,eic7700-ahci.yaml
- Add "dt-bindings: ata:" prefix to the subject.
- Wrap at 80 characters in the YAML description field.
- Link to v4: https://lore.kernel.org/lkml/[email protected]/
Yulin Lu (3):
dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
.../bindings/ata/eswin,eic7700-ahci.yaml | 79 +++++++ .../bindings/phy/eswin,eic7700-sata-phy.yaml | 36 ++++ drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/eswin/Kconfig | 14 ++ drivers/phy/eswin/Makefile | 2 + drivers/phy/eswin/phy-eic7700-sata.c | 192 ++++++++++++++++++ 7 files changed, 325 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml create mode 100644 drivers/phy/eswin/Kconfig create mode 100644 drivers/phy/eswin/Makefile create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
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2.25.1 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v5 1/3 dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
Document the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations.
--- .../bindings/ata/eswin,eic7700-ahci.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml
Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml new file +79 -0
@@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC SATA Controller + +maintainers: + - Yulin Lu <[email protected]> + - Huan He <[email protected]> + +description: + AHCI SATA controller embedded into the EIC7700 SoC is based on the DWC AHCI + SATA v5.00a IP core. + +select: + properties: + compatible: + const: eswin,eic7700-ahci + required: + - compatible + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + +properties: + compatible: + items: + - const: eswin,eic7700-ahci + - const: snps,dwc-ahci + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: aclk + + resets: + maxItems: 1 + + reset-names: + const: arst + + ports-implemented: + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports-implemented + +unevaluatedProperties: false + +examples: + - | + sata@50420000 { + compatible = "eswin,eic7700-ahci", "snps,dwc-ahci"; + reg = <0x50420000 0x10000>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clock 171>, <&clock 186>; + clock-names = "pclk", "aclk"; + phys = <&sata_phy>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + resets = <&reset 96>; + reset-names = "arst"; + };
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2.25.1 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v5 1/3] dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
Quoted 9 lines · Yulin Lu
Document the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations.
Signed-off-by Yulin Lu <[email protected]>--- .../bindings/ata/eswin,eic7700-ahci.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml
Niklas Cassel
maintainerRe: [PATCH v5 1/3] dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
In reply to Yulin LuQuoted 4 lines · Yulin Lu
Document the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations.
Signed-off-by Yulin Lu <[email protected]>
I will queue up patch 1/3 once v6.18-rc1 is out.
I expect patch 2/3 and patch 3/3 to go via the phy tree.
Kind regards,
Niklas
PATCH v5 2/3 dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
In reply to Yulin LuDocument the SATA PHY on the EIC7700 SoC platform, describing its usage.
--- .../bindings/phy/eswin,eic7700-sata-phy.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml new file +36 -0
@@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SoC SATA PHY + +maintainers: + - Yulin Lu <[email protected]> + - Huan He <[email protected]> + +properties: + compatible: + const: eswin,eic7700-sata-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + sata-phy@50440300 { + compatible = "eswin,eic7700-sata-phy"; + reg = <0x50440300 0x40>; + #phy-cells = <0>; + };
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2.25.1 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v5 3/3 phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
In reply to Yulin LuCreated the eswin phy driver directory and added support for the SATA phy driver on the EIC7700 SoC platform.
--- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/eswin/Kconfig | 14 ++ drivers/phy/eswin/Makefile | 2 + drivers/phy/eswin/phy-eic7700-sata.c | 192 +++++++++++++++++++++++++++ 5 files changed, 210 insertions(+) create mode 100644 drivers/phy/eswin/Kconfig create mode 100644 drivers/phy/eswin/Makefile create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
drivers/phy/Kconfig +1 -0
@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" +source "drivers/phy/eswin/Kconfig" source "drivers/phy/freescale/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/ingenic/Kconfig"
drivers/phy/Makefile +1 -0
@@ -17,6 +17,7 @@ obj-y += allwinner/ \ amlogic/ \ broadcom/ \ cadence/ \ + eswin/ \ freescale/ \ hisilicon/ \ ingenic/ \
drivers/phy/eswin/Kconfig new file +14 -0
@@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Eswin platforms +# +config PHY_EIC7700_SATA + tristate "eic7700 Sata SerDes/PHY driver" + depends on ARCH_ESWIN || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + help + Enable this to support SerDes/Phy found on ESWIN's + EIC7700 SoC.This Phy supports SATA 1.5 Gb/s, + SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. + It supports one SATA host port to accept one SATA device.
drivers/phy/eswin/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_EIC7700_SATA) += phy-eic7700-sata.o
drivers/phy/eswin/phy-eic7700-sata.c new file +192 -0
192 lines not on this page · raw message
Signature · 7 lines
2.25.1 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Neil Armstrong
reviewerRe: [PATCH v5 3/3] phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
Hi,
Quoted 131 lines · Yulin Lu
Created the eswin phy driver directory and added support for the SATA phy driver on the EIC7700 SoC platform.
Signed-off-by Yulin Lu <[email protected]>--- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/eswin/Kconfig | 14 ++ drivers/phy/eswin/Makefile | 2 + drivers/phy/eswin/phy-eic7700-sata.c | 192 +++++++++++++++++++++++++++ 5 files changed, 210 insertions(+)create mode 100644
drivers/phy/eswin/Kconfigcreate mode 100644drivers/phy/eswin/Makefilecreate mode 100644drivers/phy/eswin/phy-eic7700-sata.cdrivers/phy/Kconfig +1
-0@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" +source "drivers/phy/eswin/Kconfig" source "drivers/phy/freescale/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/ingenic/Kconfig"drivers/phy/Makefile +1
-0@@ -17,6 +17,7 @@ obj-y += allwinner/ \ amlogic/ \ broadcom/ \ cadence/ \ + eswin/ \ freescale/ \ hisilicon/ \ ingenic/ \drivers/phy/eswin/Kconfig new file +14
-0@@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Eswin platforms +# +config PHY_EIC7700_SATA + tristate "eic7700 Sata SerDes/PHY driver" + depends on ARCH_ESWIN || COMPILE_TEST + depends on HAS_IOMEM + select GENERIC_PHY + help + Enable this to support SerDes/Phy found on ESWIN's + EIC7700 SoC.This Phy supports SATA 1.5 Gb/s, + SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. + It supports one SATA host port to accept one SATA device.drivers/phy/eswin/Makefile new file +2
-0@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_EIC7700_SATA) += phy-eic7700-sata.odrivers/phy/eswin/phy-eic7700-sata.c new file +58
-0@@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* ESWIN SATA PHY driver +* +* Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. +* All rights reserved. +* +* Authors: Yulin Lu <[email protected]> +*/ + +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> + +#define SATA_CLK_CTRL 0x0 +#define SATA_AXI_LP_CTRL 0x08 +#define SATA_MPLL_CTRL 0x20 +#define SATA_P0_PHY_STAT 0x24 +#define SATA_PHY_CTRL0 0x28 +#define SATA_PHY_CTRL1 0x2c +#define SATA_REG_CTRL 0x34 +#define SATA_REF_CTRL1 0x38 +#define SATA_LOS_IDEN 0x3c +#define SATA_RESET_CTRL 0x40 + +#define SATA_SYS_CLK_EN BIT(28) +#define SATA_PHY_RESET BIT(0) +#define SATA_PORT_RESET BIT(1) +#define SATA_CLK_RST_SOURCE_PHY BIT(0) +#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0) +#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8) +#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16) +#define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0) +#define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8) +#define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16) +#define SATA_LOS_LEVEL_MASK GENMASK(4, 0) +#define SATA_LOS_BIAS_MASK GENMASK(18, 16) +#define SATA_M_CSYSREQ BIT(0) +#define SATA_S_CSYSREQ BIT(16) +#define SATA_REF_REPEATCLK_EN BIT(0) +#define SATA_REF_USE_PAD BIT(20) +#define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16) +#define SATA_P0_PHY_READY BIT(0) + +#define PHY_READY_TIMEOUT (usecs_to_jiffies(4000)) + +struct eic7700_sata_phy { +void __iomem *regs; +struct phy *phy; +}; + +static int wait_for_phy_ready (void __iomem *base,u32 reg,u32 checkbit, +u32 status) +{
drivers/phy/eswin/phy-eic7700-sata.c line 68
Quoted 10 lines
drivers/phy/eswin/phy-eic7700-sata.c new file +10
-0+unsigned long timeout = jiffies +PHY_READY_TIMEOUT ; + +while (time_before (jiffies, timeout)) { +if ((readl (base + reg) & checkbit) == status) +return 0 ; +usleep_range (50 ,70 ); + } + +return -ETIMEDOUT ; +}
Please use read_poll_timeout() or even better use regmap and use regmap_read_poll_timeout()
Quoted 5 lines
drivers/phy/eswin/phy-eic7700-sata.c new file +5
-0+ +static int eic7700_sata_phy_init (struct phy *phy) +{ +struct eic7700_sata_phy *sata_phy =phy_get_drvdata (phy); +u32 val;
drivers/phy/eswin/phy-eic7700-sata.c line 83
Quoted 10 lines
drivers/phy/eswin/phy-eic7700-sata.c new file +10
-0+int ret; + +/* +* The SATA_CLK_CTRL register offset controls the pmalive, rxoob, and +* rbc clocks gate provided by the PHY through the HSP bus, and it is +* not registered in the clock tree. +*/ + val =readl (sata_phy->regs +SATA_CLK_CTRL ); + val |=SATA_SYS_CLK_EN ; +writel (val, sata_phy->regs +SATA_CLK_CTRL );
regmap_update_bits() would fit here and all other read/modify/write sequence.
Quoted 99 lines
drivers/phy/eswin/phy-eic7700-sata.c new file +99
-0+ +writel (SATA_CLK_RST_SOURCE_PHY , sata_phy->regs +SATA_REF_CTRL1 ); +writel (FIELD_PREP (SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK ,0x42 ) | +FIELD_PREP (SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK ,0x46 ) | +FIELD_PREP (SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK ,0x73 ), + sata_phy->regs +SATA_PHY_CTRL0 ); +writel (FIELD_PREP (SATA_P0_PHY_TX_PREEMPH_GEN1_MASK ,0x5 ) | +FIELD_PREP (SATA_P0_PHY_TX_PREEMPH_GEN2_MASK ,0x5 ) | +FIELD_PREP (SATA_P0_PHY_TX_PREEMPH_GEN3_MASK ,0x8 ), + sata_phy->regs +SATA_PHY_CTRL1 ); +writel (FIELD_PREP (SATA_LOS_LEVEL_MASK ,0x9 ) | +FIELD_PREP (SATA_LOS_BIAS_MASK ,0x2 ), + sata_phy->regs +SATA_LOS_IDEN ); +writel (SATA_M_CSYSREQ |SATA_S_CSYSREQ , + sata_phy->regs +SATA_AXI_LP_CTRL ); +writel (SATA_REF_REPEATCLK_EN |SATA_REF_USE_PAD , + sata_phy->regs +SATA_REG_CTRL ); +writel (FIELD_PREP (SATA_MPLL_MULTIPLIER_MASK ,0x3c ), + sata_phy->regs +SATA_MPLL_CTRL ); +usleep_range (15 ,20 ); + +/* +* The SATA_RESET_CTRL register offset controls reset/deassert for both +* the port and the PHY through the HSP bus, and it is not registered +* in the reset tree. +*/ + val =readl (sata_phy->regs +SATA_RESET_CTRL ); + val &= ~(SATA_PHY_RESET |SATA_PORT_RESET ); +writel (val, sata_phy->regs +SATA_RESET_CTRL ); + + ret =wait_for_phy_ready (sata_phy->regs,SATA_P0_PHY_STAT , +SATA_P0_PHY_READY ,1 ); +if (ret <0 ) +dev_err (&sata_phy->phy->dev, +"PHY READY check failed\n" ); +return ret; +} + +static int eic7700_sata_phy_exit (struct phy *phy) +{ +struct eic7700_sata_phy *sata_phy =phy_get_drvdata (phy); +u32 val; + + val =readl (sata_phy->regs +SATA_RESET_CTRL ); + val |=SATA_PHY_RESET |SATA_PORT_RESET ; +writel (val, sata_phy->regs +SATA_RESET_CTRL ); + + val =readl (sata_phy->regs +SATA_CLK_CTRL ); + val &= ~SATA_SYS_CLK_EN ; +writel (val, sata_phy->regs +SATA_CLK_CTRL ); + +return 0 ; +} + +static const struct phy_ops eic7700_sata_phy_ops = { + .init = eic7700_sata_phy_init, + .exit = eic7700_sata_phy_exit, + .owner =THIS_MODULE , +}; + +static int eic7700_sata_phy_probe (struct platform_device *pdev) +{ +struct eic7700_sata_phy *sata_phy; +struct phy_provider *phy_provider; +struct device *dev = &pdev->dev; + + sata_phy =devm_kzalloc (dev,sizeof (*sata_phy),GFP_KERNEL ); +if (!sata_phy) +return -ENOMEM ; + + sata_phy->regs =devm_platform_ioremap_resource (pdev,0 ); +if (IS_ERR (sata_phy->regs)) +return PTR_ERR (sata_phy->regs); + +dev_set_drvdata (dev, sata_phy); + + sata_phy->phy =devm_phy_create (dev,NULL , &eic7700_sata_phy_ops); +if (IS_ERR (sata_phy->phy)) +return dev_err_probe (dev,PTR_ERR (sata_phy->phy), +"failed to create PHY\n" ); + +phy_set_drvdata (sata_phy->phy, sata_phy); + + phy_provider =devm_of_phy_provider_register (dev, of_phy_simple_xlate); +if (IS_ERR (phy_provider)) +return dev_err_probe (dev,PTR_ERR (phy_provider), +"failed to register PHY provider\n" ); + +return 0 ; +} + +static const struct of_device_id eic7700_sata_phy_of_match[] = { + { .compatible ="eswin,eic7700-sata-phy" }, + { }, +}; +MODULE_DEVICE_TABLE (of, eic7700_sata_phy_of_match); + +static struct platform_driver eic7700_sata_phy_driver = { + .probe = eic7700_sata_phy_probe,
drivers/phy/eswin/phy-eic7700-sata.c line 192
Quoted 10 lines
drivers/phy/eswin/phy-eic7700-sata.c new file +10
-0+ .driver = { + .of_match_table = eic7700_sata_phy_of_match, + .name = "eic7700-sata-phy", + } +}; +module_platform_driver (eic7700_sata_phy_driver); + +MODULE_DESCRIPTION ("SATA PHY driver for the ESWIN EIC7700 SoC" ); +MODULE_AUTHOR ("Yulin Lu <[email protected]>" ); +MODULE_LICENSE ("GPL" );
Thanks,
Neil
Re: (subset) [PATCH v5 0/3] Add driver support for Eswin EIC7700 SoC SATA Controller and PHY
In reply to Yulin LuQuoted 4 lines · Yulin Lu
This series depends on the config option patch [1].
[1] Https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20250929&id=ce2d00c6e192b588ddc3d1efb72b0ea00ab5538f
Quoted 8 lines
Updates:
v5 -> v4:
- eswin,eic7700-ahci.yaml
- Add "dt-bindings: ata:" prefix to the subject.
- Wrap at 80 characters in the YAML description field.
- Link to v4: https://lore.kernel.org/lkml/[email protected]/[...]
Applied to libata/linux.git (for-6.19), thanks!
[1/3] dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
https://git.kernel.org/libata/linux/c/c9d869fb
Kind regards,
Niklas
Hi all,
Gentle ping.
Could you please review the PHY-related changes in patch 2/3 and patch 3/3? Thanks in advance for your time and consideration.
Best regards,
Yulin Lu
Quoted 33 lines
This series depends on the config option patch [1].
[1] Https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20250929&id=ce2d00c6e192b588ddc3d1efb72b0ea00ab5538f
Updates:
v5 -> v4:
- eswin,eic7700-ahci.yaml
- Add "dt-bindings: ata:" prefix to the subject.
- Wrap at 80 characters in the YAML description field.
- Link to v4: https://lore.kernel.org/lkml/[email protected]/Yulin Lu (3):
dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver.../bindings/ata/eswin,eic7700-ahci.yaml | 79 +++++++ .../bindings/phy/eswin,eic7700-sata-phy.yaml | 36 ++++ drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/eswin/Kconfig | 14 ++ drivers/phy/eswin/Makefile | 2 + drivers/phy/eswin/phy-eic7700-sata.c | 192 ++++++++++++++++++ 7 files changed, 325 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml create mode 100644 drivers/phy/eswin/Kconfig create mode 100644 drivers/phy/eswin/Makefile create mode 100644 drivers/phy/eswin/phy-eic7700-sata.cSignature · 1 line
2.25.1