arm64: dts: imx8mm-var-dart: update SoM support
Subsystems (2)
cover arm64: dts: imx8mm-var-dart: update SoM support
This series updates the Variscite DART-MX8M-MINI SoM device tree to better reflect the currently supported hardware configuration.
The changes configure SAI3 in synchronous RX mode, add TPM support, and increase the Ethernet PHY reset deassert delay to improve PHY detection reliability.
Stefano Radaelli (3):
arm64: dts: imx8mm-var-dart: configure SAI3 synchronous RX mode
arm64: dts: imx8mm-var-dart: add TPM support
arm64: dts: imx8mm-var-dart: increase PHY reset deassert delay
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
base-commit: 46d8fa682d263271f3ef7bf95166b124c19d6c62
Signature · 1 line
2.47.3
PATCH 1/3 arm64: dts: imx8mm-var-dart: configure SAI3 synchronous RX mode
From: Stefano Radaelli <[email protected]>
Configure SAI3 to operate in synchronous RX mode, so that the trasmit path uses the receive bit clock and frame sync signals.
Remove the TX_SYNC and TX_BCLK pinmux entries, as these signals are not used in this configuration.
--- arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi +1 -2
@@ -305,6 +305,7 @@ &sai3 { assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clock-rates = <1536000>; fsl,sai-mclk-direction-output; + fsl,sai-synchronous-rx; status = "okay"; };
@@ -446,8 +447,6 @@ pinctrl_sai3: sai3grp { MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 >;
Signature · 1 line
2.47.3
PATCH 2/3 arm64: dts: imx8mm-var-dart: add TPM support
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Add support for the TPM available on the Variscite DART-MX8M-MINI SOM.
--- arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi +7 -0
@@ -138,6 +138,13 @@ &i2c1 { sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + st33ktpm2xi2c_som: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + }; + pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>;
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v1 2/3] arm64: dts: imx8mm-var-dart: add TPM support
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] arm64: dts: incorrect polarity for TPM reset gpio - [Medium] arm64: dts: missing pinctrl for TPM…
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] arm64: dts: incorrect polarity for TPM reset gpio
- [Medium] arm64: dts: missing pinctrl for TPM reset gpio
--
commit b6842f762ba714e622e3da081d4b664400c4462d
Author: Stefano Radaelli <[email protected]>
arm64: dts: imx8mm-var-dart: add TPM support
Add support for the TPM available on the Variscite DART-MX8M-MINI SOM.
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi +0
-0
[ ... ]
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi &i2c1 { · line 145
Quoted 9 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi +5
-0@@ -138,6 +138,13 @@ &i2c1 { sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + st33ktpm2xi2c_som: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
[Severity: Medium]
Will this reset line work without a corresponding pinctrl configuration?
The node requests &gpio4 31 (pad SAI3_TXFS) as its reset line but lacks a pinctrl-0 property to configure the pad's multiplexer to GPIO mode.
Since the i.MX pinctrl driver does not implement .gpio_request_enable(), the GPIO subsystem cannot automatically reconfigure the pad when requested.
Does this leave the pad in its default or bootloader-assigned state, causing software toggling of the GPIO to silently fail and breaking the hardware reset capability?
[Severity: High]
Is the reset GPIO polarity correct for the ST33K TPM hardware?
The STMicroelectronics ST33K TPM hardware reset line is active-low (RST_N), but the reset-gpios property specifies GPIO_ACTIVE_HIGH.
When the driver attempts to release the device from reset by logically de-asserting the GPIO, won't gpiolib drive the physical line LOW (0V)?
Driving the active-low hardware pin LOW will hold the TPM in reset permanently, causing device initialization to fail entirely. Should this be configured as GPIO_ACTIVE_LOW instead?
Quoted 5 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi +2
-0+ }; + pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>;
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
PATCH 3/3 arm64: dts: imx8mm-var-dart: increase PHY reset deassert delay
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
The Ethernet PHY reset signal also controls the regulators supplying VDDA2P5 and VDD1P0, so releasing reset restores the PHY's 2.5 V and 1.0 V analog supplies.
The existing 100 ms reset deassertion delay is not sufficient for reliable PHY detection. The TI DP83867 requires 200 ms of stabilization after power-up before MDIO register access.
Increase the reset deassertion delay to 200 ms to ensure reliable PHY detection across repeated boots.
--- arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi +1 -1
@@ -123,7 +123,7 @@ ethphy0: ethernet-phy@0 { reg = <0>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - reset-deassert-us = <100000>; + reset-deassert-us = <200000>; vddio-supply = <®_phy_vddio>; }; };
Signature · 1 line
2.47.3