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qspi controller: Normal, quad and memory mapped read support

PATCH Superseded Sourav Poddar 5 participants 17 messages Jul 10, 2013 – Jul 11, 2013

Subsystems (3)
Arm (32-bit) Memory technology devices (MTD) SPI

v1 of 6 Superseded Latest is v6 →

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Sourav Poddar

author
#0 lore raw

cover qspi controller: Normal, quad and memory mapped read support

This patch series add uboot ti qspi controller driver.

QSPI is a kind of spi module that allows single, dual and quad read access to external spi devices. The module has a memory mapped interface which provide direct interface for accessing data form external spi devices.

SPI mode
-------
SPI mode uses mtd spi framework for transfer and reception of data. Can be used in:
1. Normal mode: use single pin for transfers
2. Dual Mode: use two pins for transfers.
3. Quad mode: use four pin for transfer

Memory mapped read mode
-----------------------
In this, SPI controller is configured using configuration port and then controler is switched to memory mapped port for data read.

Series proposed suport for quad read as well as memory mapped read in spi mtd frameowrk as well as ti qpsi driver.

Matt Porter (3):
omap5: add qspi support
spi: add TI QSPI driver
dra7xx_evm: add SPL API, QSPI, and serial flash support

Ravikumar Kattekola (1):
drivers: mtd: qspi: Add quad read support

Sourav Poddar (3):
drivers: mtd: spi: Modify read/write command for sfl256s flash.
driver: spi: Add memory mapped read support
README: qspi usecase and testing documentation.

 arch/arm/cpu/armv7/omap5/hw_data.c     |    7 +-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 board/ti/dra7xx/mux_data.h             |   10 +
 doc/README.ti_qspi_dra_test            |   38 ++++
 doc/README.ti_qspi_flash               |   47 +++++
 drivers/mtd/spi/spansion.c             |    1 +
 drivers/mtd/spi/spi_flash.c            |  177 +++++++++++++++++-
 drivers/mtd/spi/spi_flash_internal.h   |    2 +
 drivers/spi/Makefile                   |    1 +
 drivers/spi/ti_qspi.c                  |  327 ++++++++++++++++++++++++++++++++
 include/configs/dra7xx_evm.h           |   24 +++
 include/spi.h                          |    5 +
 15 files changed, 640 insertions(+), 5 deletions(-)
 create mode 100644 doc/README.ti_qspi_dra_test
 create mode 100644 doc/README.ti_qspi_flash
 create mode 100644 drivers/spi/ti_qspi.c
author
#1 lore raw

PATCH 1/7 omap5: add qspi support

From: Matt Porter <[email protected]>

Add QSPI definitions and clock configuration support.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hw_data.c     |    7 ++++++-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +++
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 5 files changed, 12 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/omap5/hw_data.c +6 -1
index 9374c6a..046ce44 100644
@@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
 	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
 	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
 	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */

@@ -423,6 +423,7 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_wkup_wdtimer2_clkctrl,
 		(*prcm)->cm_l4per_uart3_clkctrl,
 		(*prcm)->cm_l4per_i2c1_clkctrl,
+		(*prcm)->cm_l4per_qspi_clkctrl,
 		0
 	};
 

@@ -451,6 +452,10 @@ void enable_basic_clocks(void)
 			 clk_modules_explicit_en_essential,
 			 1);
 
+#ifdef CONFIG_TI_QSPI
+	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
 	/* Enable SCRM OPT clocks for PER and CORE dpll */
 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_PER_MASK);
arch/arm/cpu/armv7/omap5/prcm-regs.c +1 -0
index 331117c..debc56b 100644
@@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
 	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
 	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_qspi_clkctrl			= 0x4a009838,
 	.cm_l4per_uart1_clkctrl			= 0x4a009840,
 	.cm_l4per_uart2_clkctrl			= 0x4a009848,
 	.cm_l4per_uart3_clkctrl			= 0x4a009850,
arch/arm/include/asm/arch-omap5/omap.h +3 -0
index e7d79fc..d2c4930 100644
@@ -67,6 +67,9 @@
 /* GPMC */
 #define OMAP54XX_GPMC_BASE	0x50000000
 
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
 /*
  * Hardware Register Details
  */
arch/arm/include/asm/arch-omap5/spl.h +1 -0
index d4d353c..8905cb8 100644
@@ -31,6 +31,7 @@
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
 #define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
arch/arm/include/asm/omap_common.h +1 -0
index fa28358..c8d4619 100644
@@ -279,6 +279,7 @@ struct prcm_regs {
 	u32 cm_l4per_mmcsd4_clkctrl;
 	u32 cm_l4per_msprohg_clkctrl;
 	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
 	u32 cm_l4per_uart1_clkctrl;
 	u32 cm_l4per_uart2_clkctrl;
 	u32 cm_l4per_uart3_clkctrl;
Signature · 1 line
1.7.1
#2 lore raw

PATCH 1/7 omap5: add qspi support

Quoted 4 lines · Sourav Poddar

From: Matt Porter <[email protected]>

Add QSPI definitions and clock configuration support.

OMAP54xx does not have QSPI. DRA7 has QSPI?

Quoted 15 lines
Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hw_data.c     |    7 ++++++-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +++
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 5 files changed, 12 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/omap5/hw_data.c +0 -0
index 9374c6a..046ce44 100644

arch/arm/cpu/armv7/omap5/hw_data.c static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { · line 189

Quoted 5 lines
arch/arm/cpu/armv7/omap5/hw_data.c +1 -1
@@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
        {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
-       {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
+       {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 20 MHz   */

is this a separate fix?

Quoted 53 lines
arch/arm/cpu/armv7/omap5/hw_data.c +5 -0
        {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
        {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
        {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */

@@ -423,6 +423,7 @@ void enable_basic_clocks(void)
                (*prcm)->cm_wkup_wdtimer2_clkctrl,
                (*prcm)->cm_l4per_uart3_clkctrl,
                (*prcm)->cm_l4per_i2c1_clkctrl,
+               (*prcm)->cm_l4per_qspi_clkctrl,
                0
        };
 

@@ -451,6 +452,10 @@ void enable_basic_clocks(void)
                         clk_modules_explicit_en_essential,
                         1);
 
+#ifdef CONFIG_TI_QSPI
+       setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
        /* Enable SCRM OPT clocks for PER and CORE dpll */
        setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
                        OPTFCLKEN_SCRM_PER_MASK);
arch/arm/cpu/armv7/omap5/prcm-regs.c +1 -0
index 331117c..debc56b 100644
@@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_l4per_gpio8_clkctrl                 = 0x4a009818,
        .cm_l4per_mmcsd3_clkctrl                = 0x4a009820,
        .cm_l4per_mmcsd4_clkctrl                = 0x4a009828,
+       .cm_l4per_qspi_clkctrl                  = 0x4a009838,
        .cm_l4per_uart1_clkctrl                 = 0x4a009840,
        .cm_l4per_uart2_clkctrl                 = 0x4a009848,
        .cm_l4per_uart3_clkctrl                 = 0x4a009850,
arch/arm/include/asm/arch-omap5/omap.h +3 -0
index e7d79fc..d2c4930 100644
@@ -67,6 +67,9 @@
 /* GPMC */
 #define OMAP54XX_GPMC_BASE     0x50000000
 
+/* QSPI */
+#define QSPI_BASE              0x4B300000
+
 /*
  * Hardware Register Details
  */
arch/arm/include/asm/arch-omap5/spl.h +0 -0
index d4d353c..8905cb8 100644

arch/arm/include/asm/arch-omap5/spl.h line 34

Quoted 4 lines
arch/arm/include/asm/arch-omap5/spl.h +1 -0
@@ -31,6 +31,7 @@
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
 #define BOOT_DEVICE_MMC2_2     7
+#define BOOT_DEVICE_SPI                10

why not 8?

Quoted 22 lines
arch/arm/include/asm/arch-omap5/spl.h +0 -0
 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2_2
arch/arm/include/asm/omap_common.h +1 -1
index fa28358..c8d4619 100644
@@ -279,6 +279,7 @@ struct prcm_regs {
        u32 cm_l4per_mmcsd4_clkctrl;
        u32 cm_l4per_msprohg_clkctrl;
        u32 cm_l4per_slimbus2_clkctrl;
+       u32 cm_l4per_qspi_clkctrl;
        u32 cm_l4per_uart1_clkctrl;
        u32 cm_l4per_uart2_clkctrl;
        u32 cm_l4per_uart3_clkctrl;
--

1.7.1

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#3 lore raw

PATCH 1/7 omap5: add qspi support

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 3 lines · Nishanth Menon
Quoted 1 line · Sourav Poddar

From: Matt Porter <[email protected]>

I think it's good form to update folks addresses, Matt is now matt.porter at linaro.org

Quoted 1 line
Quoted 1 line

Add QSPI definitions and clock configuration support.

[snip]

Quoted 8 lines
Quoted 6 lines
(quoted diff) +0 -0

b/arch/arm/include/asm/arch-omap5/spl.h index d4d353c..8905cb8 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -31,6 +31,7 @@
#define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2
6 #define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10

why not 8?

This is the value ROM passes when we boot here. What I would like to know is, is this really "SPI" or QSPI_1 or QSPI_4 ? I suspect it's QSPI_1. And yes, we want to be precise here because while DRA7 doesn't have McSPI AM437x will, along with QSPI.

- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJR3WURAAoJENk4IS6UOR1W9aQP/jEBoyQKtU7n+B6aAMY5b5U4 FF54lAfRvJZfUaRVDCLmLMF+87Obx6ctQ95SogkKbsNmc5TxbDy7dBfd7G3++5ZG ivYQcEv9MKi/kGgJ0UZejc2J4e+QbQbymvnVqHG2mKJnMjRSdeuQG7UUGGIRQeA7 /VwR4cZuNqVrcejlglrBrwxr5PdA1f/cMCr1Dp4PhiHzxG+YYbiS4EVmnT+GNXmL RfZuy2TzjAir7brn4Y6sQ2fcHu2qXIzO6U/a16ZawfwB8089Zj4FMvP20IugsIyU drZhaJ3jY+leTCW1Wq5BZ1s2IJ7eaIqW4kbCSif9sPqxqM1lwJdqFJAdY8eGUWD/ c7cpJxkyLvleK0WFZDVraljIXoY7SMiTpnjYU5M+ASV43s+fFSl3f0VnZLuQtkkW +nFQeF1FdRDUd32jFDOzCuEeJbiPpy3mJLn60ND1r56VPQweroVBE3AetavzYDA0 K40Q3o/vXBLPyl2IELLOK5hpESWVlXasgMUOsNSfqpxGblh9ea5sXZ/Nvk8hjdmm ViVXk5lqNvmZzYzu0znRmLEg3ucuyYif0IOh/IOb97mAjR8KX0iCavw42RI5ympb E6d4is/Ap3x67BMBiEquRVWYmXv78Mr0o6LEhgayxM9rrT38uJyaGgIXlszia0xE QIqgV1U808hJVFMMnAK+
=EY5D
-----END PGP SIGNATURE-----

author
#4 lore raw

PATCH 1/7 omap5: add qspi support

Quoted 19 lines · Tom Rini

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Quoted 3 lines · Nishanth Menon
Quoted 1 line · Sourav Poddar

From: Matt Porter<[email protected]>

I think it's good form to update folks addresses, Matt is now matt.porter at linaro.org

Quoted 1 line
Quoted 1 line

Add QSPI definitions and clock configuration support.

[snip]

Quoted 7 lines
Quoted 6 lines
(quoted diff) +0 -0

b/arch/arm/include/asm/arch-omap5/spl.h index d4d353c..8905cb8 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -31,6 +31,7 @@
#define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2
6 #define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10

why not 8?

Quoted 5 lines

This is the value ROM passes when we boot here. What I would like to know is, is this really "SPI" or QSPI_1 or QSPI_4 ? I suspect it's QSPI_1. And yes, we want to be precise here because while DRA7 doesn't have McSPI AM437x will, along with QSPI.

Yes, its QSPI1.
Will explicitl define it as QSPI91/4) in next version.

Quoted 20 lines

- --
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJR3WURAAoJENk4IS6UOR1W9aQP/jEBoyQKtU7n+B6aAMY5b5U4 FF54lAfRvJZfUaRVDCLmLMF+87Obx6ctQ95SogkKbsNmc5TxbDy7dBfd7G3++5ZG ivYQcEv9MKi/kGgJ0UZejc2J4e+QbQbymvnVqHG2mKJnMjRSdeuQG7UUGGIRQeA7 /VwR4cZuNqVrcejlglrBrwxr5PdA1f/cMCr1Dp4PhiHzxG+YYbiS4EVmnT+GNXmL RfZuy2TzjAir7brn4Y6sQ2fcHu2qXIzO6U/a16ZawfwB8089Zj4FMvP20IugsIyU drZhaJ3jY+leTCW1Wq5BZ1s2IJ7eaIqW4kbCSif9sPqxqM1lwJdqFJAdY8eGUWD/ c7cpJxkyLvleK0WFZDVraljIXoY7SMiTpnjYU5M+ASV43s+fFSl3f0VnZLuQtkkW +nFQeF1FdRDUd32jFDOzCuEeJbiPpy3mJLn60ND1r56VPQweroVBE3AetavzYDA0 K40Q3o/vXBLPyl2IELLOK5hpESWVlXasgMUOsNSfqpxGblh9ea5sXZ/Nvk8hjdmm ViVXk5lqNvmZzYzu0znRmLEg3ucuyYif0IOh/IOb97mAjR8KX0iCavw42RI5ympb E6d4is/Ap3x67BMBiEquRVWYmXv78Mr0o6LEhgayxM9rrT38uJyaGgIXlszia0xE QIqgV1U808hJVFMMnAK+
=EY5D
-----END PGP SIGNATURE-----

author
#5 lore raw

PATCH 1/7 omap5: add qspi support

In reply to Nishanth Menon
Quoted 7 lines · Nishanth Menon
Quoted 4 lines · Sourav Poddar

From: Matt Porter<[email protected]>

Add QSPI definitions and clock configuration support.

OMAP54xx does not have QSPI. DRA7 has QSPI?

Yes.

Quoted 16 lines
Quoted 16 lines
Signed-off-by Matt Porter<[email protected]>
Signed-off-by Sourav Poddar<[email protected]>
---
  arch/arm/cpu/armv7/omap5/hw_data.c     |    7 ++++++-
  arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
  arch/arm/include/asm/arch-omap5/omap.h |    3 +++
  arch/arm/include/asm/arch-omap5/spl.h  |    1 +
  arch/arm/include/asm/omap_common.h     |    1 +
  5 files changed, 12 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/omap5/hw_data.c +0 -0
index 9374c6a..046ce44 100644
@@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
Quoted 6 lines

arch/arm/cpu/armv7/omap5/hw_data.c static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { · line 189

Quoted 4 lines
arch/arm/cpu/armv7/omap5/hw_data.c +1 -1
  static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
         {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
-       {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 20 MHz   */
+       {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 20 MHz   */

is this a separate fix?

Ahh..it can be send as a seperate fix actually. Will change.

Quoted 80 lines
Quoted 53 lines
arch/arm/cpu/armv7/omap5/hw_data.c +5 -0
         {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
         {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
         {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */

@@ -423,6 +423,7 @@ void enable_basic_clocks(void)
                 (*prcm)->cm_wkup_wdtimer2_clkctrl,
                 (*prcm)->cm_l4per_uart3_clkctrl,
                 (*prcm)->cm_l4per_i2c1_clkctrl,
+               (*prcm)->cm_l4per_qspi_clkctrl,
                 0
         };
 

@@ -451,6 +452,10 @@ void enable_basic_clocks(void)
                          clk_modules_explicit_en_essential,
                          1);
 
+#ifdef CONFIG_TI_QSPI
+       setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
         /* Enable SCRM OPT clocks for PER and CORE dpll */
         setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
                         OPTFCLKEN_SCRM_PER_MASK);
arch/arm/cpu/armv7/omap5/prcm-regs.c +1 -0
index 331117c..debc56b 100644
@@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
         .cm_l4per_gpio8_clkctrl                 = 0x4a009818,
         .cm_l4per_mmcsd3_clkctrl                = 0x4a009820,
         .cm_l4per_mmcsd4_clkctrl                = 0x4a009828,
+       .cm_l4per_qspi_clkctrl                  = 0x4a009838,
         .cm_l4per_uart1_clkctrl                 = 0x4a009840,
         .cm_l4per_uart2_clkctrl                 = 0x4a009848,
         .cm_l4per_uart3_clkctrl                 = 0x4a009850,
arch/arm/include/asm/arch-omap5/omap.h +3 -0
index e7d79fc..d2c4930 100644
@@ -67,6 +67,9 @@
  /* GPMC */
  #define OMAP54XX_GPMC_BASE     0x50000000
 
+/* QSPI */
+#define QSPI_BASE              0x4B300000
+
  /*
   * Hardware Register Details
   */
arch/arm/include/asm/arch-omap5/spl.h +0 -0
index d4d353c..8905cb8 100644

arch/arm/include/asm/arch-omap5/spl.h line 34

Quoted 4 lines
arch/arm/include/asm/arch-omap5/spl.h +1 -0
@@ -31,6 +31,7 @@
  #define BOOT_DEVICE_MMC1        5
  #define BOOT_DEVICE_MMC2        6
  #define BOOT_DEVICE_MMC2_2     7
+#define BOOT_DEVICE_SPI                10

why not 8?

Quoted 21 lines
arch/arm/include/asm/arch-omap5/spl.h +0 -0
  #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
  #define MMC_BOOT_DEVICES_END   BOOT_DEVICE_MMC2_2
arch/arm/include/asm/omap_common.h +1 -1
index fa28358..c8d4619 100644
@@ -279,6 +279,7 @@ struct prcm_regs {
         u32 cm_l4per_mmcsd4_clkctrl;
         u32 cm_l4per_msprohg_clkctrl;
         u32 cm_l4per_slimbus2_clkctrl;
+       u32 cm_l4per_qspi_clkctrl;
         u32 cm_l4per_uart1_clkctrl;
         u32 cm_l4per_uart2_clkctrl;
         u32 cm_l4per_uart3_clkctrl;
--

1.7.1

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#6 lore raw

PATCH 1/7 omap5: add qspi support

In reply to Sourav Poddar
Quoted 28 lines · Sourav Poddar

From: Matt Porter <[email protected]>

Add QSPI definitions and clock configuration support.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hw_data.c     |    7 ++++++-
 arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
 arch/arm/include/asm/arch-omap5/omap.h |    3 +++
 arch/arm/include/asm/arch-omap5/spl.h  |    1 +
 arch/arm/include/asm/omap_common.h     |    1 +
 5 files changed, 12 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/omap5/hw_data.c +1 -1
index 9374c6a..046ce44 100644
@@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
 	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
 	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
 	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
 	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */

arch/arm/cpu/armv7/omap5/hw_data.c void enable_basic_clocks(void) · line 426

Quoted 4 lines
arch/arm/cpu/armv7/omap5/hw_data.c +1 -0
@@ -423,6 +423,7 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_wkup_wdtimer2_clkctrl,
 		(*prcm)->cm_l4per_uart3_clkctrl,
 		(*prcm)->cm_l4per_i2c1_clkctrl,
+		(*prcm)->cm_l4per_qspi_clkctrl,

Keep this also under CONFIG_TI_QSPI because we should enable QSPI clocks only if support is available.

Thanks,
Lokesh

Quoted 65 lines
arch/arm/cpu/armv7/omap5/hw_data.c +4 -0
 		0
 	};
 

@@ -451,6 +452,10 @@ void enable_basic_clocks(void)
 			 clk_modules_explicit_en_essential,
 			 1);
 
+#ifdef CONFIG_TI_QSPI
+	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
 	/* Enable SCRM OPT clocks for PER and CORE dpll */
 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_PER_MASK);
arch/arm/cpu/armv7/omap5/prcm-regs.c +1 -0
index 331117c..debc56b 100644
@@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
 	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
 	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_qspi_clkctrl			= 0x4a009838,
 	.cm_l4per_uart1_clkctrl			= 0x4a009840,
 	.cm_l4per_uart2_clkctrl			= 0x4a009848,
 	.cm_l4per_uart3_clkctrl			= 0x4a009850,
arch/arm/include/asm/arch-omap5/omap.h +3 -0
index e7d79fc..d2c4930 100644
@@ -67,6 +67,9 @@
 /* GPMC */
 #define OMAP54XX_GPMC_BASE	0x50000000
 
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
 /*
  * Hardware Register Details
  */
arch/arm/include/asm/arch-omap5/spl.h +1 -0
index d4d353c..8905cb8 100644
@@ -31,6 +31,7 @@
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
 #define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
arch/arm/include/asm/omap_common.h +1 -0
index fa28358..c8d4619 100644
@@ -279,6 +279,7 @@ struct prcm_regs {
 	u32 cm_l4per_mmcsd4_clkctrl;
 	u32 cm_l4per_msprohg_clkctrl;
 	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
 	u32 cm_l4per_uart1_clkctrl;
 	u32 cm_l4per_uart2_clkctrl;
 	u32 cm_l4per_uart3_clkctrl;
author
#7 lore raw

PATCH 1/7 omap5: add qspi support

Quoted 21 lines · Lokesh Vutla
Quoted 20 lines · Sourav Poddar

From: Matt Porter<[email protected]>

Add QSPI definitions and clock configuration support.

Signed-off-by Matt Porter<[email protected]>
Signed-off-by Sourav Poddar<[email protected]>
---
  arch/arm/cpu/armv7/omap5/hw_data.c     |    7 ++++++-
  arch/arm/cpu/armv7/omap5/prcm-regs.c   |    1 +
  arch/arm/include/asm/arch-omap5/omap.h |    3 +++
  arch/arm/include/asm/arch-omap5/spl.h  |    1 +
  arch/arm/include/asm/omap_common.h     |    1 +
  5 files changed, 12 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/omap5/hw_data.c +0 -0
index 9374c6a..046ce44 100644
@@ -186,7 +186,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
Quoted 15 lines

arch/arm/cpu/armv7/omap5/hw_data.c void enable_basic_clocks(void) · line 426

Quoted 12 lines
arch/arm/cpu/armv7/omap5/hw_data.c +2 -1
  static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
  	{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
+	{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 20 MHz   */
  	{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 16.8 MHz */
  	{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 19.2 MHz */
  	{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 26 MHz   */

@@ -423,6 +423,7 @@ void enable_basic_clocks(void)
  		(*prcm)->cm_wkup_wdtimer2_clkctrl,
  		(*prcm)->cm_l4per_uart3_clkctrl,
  		(*prcm)->cm_l4per_i2c1_clkctrl,
+		(*prcm)->cm_l4per_qspi_clkctrl,

Keep this also under CONFIG_TI_QSPI because we should enable QSPI clocks only if support is available.

Ok.

Quoted 67 lines

Thanks,
Lokesh

Quoted 65 lines
arch/arm/cpu/armv7/omap5/hw_data.c +4 -0
  		0
  	};
 

@@ -451,6 +452,10 @@ void enable_basic_clocks(void)
  			 clk_modules_explicit_en_essential,
  			 1);
 
+#ifdef CONFIG_TI_QSPI
+	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
  	/* Enable SCRM OPT clocks for PER and CORE dpll */
  	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
  			OPTFCLKEN_SCRM_PER_MASK);
arch/arm/cpu/armv7/omap5/prcm-regs.c +1 -0
index 331117c..debc56b 100644
@@ -926,6 +926,7 @@ struct prcm_regs const dra7xx_prcm = {
  	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
  	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
  	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
+	.cm_l4per_qspi_clkctrl			= 0x4a009838,
  	.cm_l4per_uart1_clkctrl			= 0x4a009840,
  	.cm_l4per_uart2_clkctrl			= 0x4a009848,
  	.cm_l4per_uart3_clkctrl			= 0x4a009850,
arch/arm/include/asm/arch-omap5/omap.h +3 -0
index e7d79fc..d2c4930 100644
@@ -67,6 +67,9 @@
  /* GPMC */
  #define OMAP54XX_GPMC_BASE	0x50000000
 
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
  /*
   * Hardware Register Details
   */
arch/arm/include/asm/arch-omap5/spl.h +1 -0
index d4d353c..8905cb8 100644
@@ -31,6 +31,7 @@
  #define BOOT_DEVICE_MMC1        5
  #define BOOT_DEVICE_MMC2        6
  #define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
 
  #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
  #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
arch/arm/include/asm/omap_common.h +1 -0
index fa28358..c8d4619 100644
@@ -279,6 +279,7 @@ struct prcm_regs {
  	u32 cm_l4per_mmcsd4_clkctrl;
  	u32 cm_l4per_msprohg_clkctrl;
  	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
  	u32 cm_l4per_uart1_clkctrl;
  	u32 cm_l4per_uart2_clkctrl;
  	u32 cm_l4per_uart3_clkctrl;
author
#8 lore raw

PATCH 2/7 spi: add TI QSPI driver

In reply to Sourav Poddar

From: Matt Porter <[email protected]>

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 drivers/spi/Makefile  |    1 +
 drivers/spi/ti_qspi.c |  262 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 263 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/ti_qspi.c
drivers/spi/Makefile +1 -0
index d08609e..f51033d 100644
@@ -54,6 +54,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
 COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
 COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
+COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o
 COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 
 COBJS	:= $(COBJS-y)
drivers/spi/ti_qspi.c new file +262 -0

262 lines not on this page · raw message

Signature · 1 line
1.7.1
author
#9 lore raw

PATCH 3/7 dra7xx_evm: add SPL API, QSPI, and serial flash support

In reply to Sourav Poddar

From: Matt Porter <[email protected]>

Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 board/ti/dra7xx/mux_data.h   |   10 ++++++++++
 include/configs/dra7xx_evm.h |   22 ++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)
board/ti/dra7xx/mux_data.h +10 -0
index 338a241..2441c55 100644
@@ -53,5 +53,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{UART1_RTSN, (IEN | PTU | PDIS | M3)},	/* UART1_RTSN */
 	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
 	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
+	{GPMC_A13, (IEN | PDIS | M1)},	/* QSPI1_RTCLK */
+	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
+	{GPMC_A15, (IEN | PDIS | M1)},	/* QSPI1_D[2] */
+	{GPMC_A16, (IEN | PDIS | M1)},	/* QSPI1_D[1] */
+	{GPMC_A17, (IEN | PDIS | M1)},	/* QSPI1_D[0] */
+	{GPMC_A18, (IEN | PDIS | M1)},	/* QSPI1_SCLK */
+	{GPMC_A3, (IEN | PDIS | M1)},	/* QSPI1_CS2 */
+	{GPMC_A4, (IEN | PDIS | M1)},	/* QSPI1_CS3 */
+	{GPMC_CS2, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS0 */
+	{GPMC_CS3, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS1*/
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
include/configs/dra7xx_evm.h +22 -0
index 6b37e1d..0583858 100644
@@ -46,4 +46,26 @@
 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
 
 #define CONFIG_SYS_OMAP_ABE_SYSCK
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#define EMIF1_EMIF2
+
+/* SPI */
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SF_DEFAULT_SPEED		12000000
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
Signature · 1 line
1.7.1
#10 lore raw

PATCH 3/7 dra7xx_evm: add SPL API, QSPI, and serial flash support

Quoted 37 lines · Sourav Poddar

From: Matt Porter <[email protected]>

Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by Matt Porter <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 board/ti/dra7xx/mux_data.h   |   10 ++++++++++
 include/configs/dra7xx_evm.h |   22 ++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)
board/ti/dra7xx/mux_data.h +10 -0
index 338a241..2441c55 100644
@@ -53,5 +53,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
 	{UART1_RTSN, (IEN | PTU | PDIS | M3)},	/* UART1_RTSN */
 	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
 	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
+	{GPMC_A13, (IEN | PDIS | M1)},	/* QSPI1_RTCLK */
+	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
+	{GPMC_A15, (IEN | PDIS | M1)},	/* QSPI1_D[2] */
+	{GPMC_A16, (IEN | PDIS | M1)},	/* QSPI1_D[1] */
+	{GPMC_A17, (IEN | PDIS | M1)},	/* QSPI1_D[0] */
+	{GPMC_A18, (IEN | PDIS | M1)},	/* QSPI1_SCLK */
+	{GPMC_A3, (IEN | PDIS | M1)},	/* QSPI1_CS2 */
+	{GPMC_A4, (IEN | PDIS | M1)},	/* QSPI1_CS3 */
+	{GPMC_CS2, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS0 */
+	{GPMC_CS3, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS1*/
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
include/configs/dra7xx_evm.h +0 -0
index 6b37e1d..0583858 100644

include/configs/dra7xx_evm.h line 50

Quoted 5 lines
include/configs/dra7xx_evm.h +2 -0
@@ -46,4 +46,26 @@
 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
 
 #define CONFIG_SYS_OMAP_ABE_SYSCK
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF

Is it necessary to Disable caches to use QSPI?
If not please drop these two defines.

include/configs/dra7xx_evm.h line 52

Quoted 2 lines
include/configs/dra7xx_evm.h +2 -0
+
+#define EMIF1_EMIF2

This one too..

Thanks,
Lokesh

Quoted 20 lines
include/configs/dra7xx_evm.h +18 -0
+
+/* SPI */
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SF_DEFAULT_SPEED		12000000
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_3
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
#11 lore raw

PATCH 3/7 dra7xx_evm: add SPL API, QSPI, and serial flash support

[...]

Quoted 10 lines
Quoted 10 lines
board/ti/dra7xx/mux_data.h +2 -0
index 338a241..2441c55 100644
@@ -53,5 +53,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
  	{UART1_RTSN, (IEN | PTU | PDIS | M3)},	/* UART1_RTSN */
  	{I2C1_SDA, (IEN | PTU | PDIS | M0)},	/* I2C1_SDA */
  	{I2C1_SCL, (IEN | PTU | PDIS | M0)},	/* I2C1_SCL */
+	{GPMC_A13, (IEN | PDIS | M1)},	/* QSPI1_RTCLK */
+	{GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
Quoted 8 lines

board/ti/dra7xx/mux_data.h const struct pad_conf_entry core_padconf_array_essential[] = { · line 65

Quoted 8 lines
board/ti/dra7xx/mux_data.h +8 -0
+	{GPMC_A15, (IEN | PDIS | M1)},	/* QSPI1_D[2] */
+	{GPMC_A16, (IEN | PDIS | M1)},	/* QSPI1_D[1] */
+	{GPMC_A17, (IEN | PDIS | M1)},	/* QSPI1_D[0] */
+	{GPMC_A18, (IEN | PDIS | M1)},	/* QSPI1_SCLK */
+	{GPMC_A3, (IEN | PDIS | M1)},	/* QSPI1_CS2 */
+	{GPMC_A4, (IEN | PDIS | M1)},	/* QSPI1_CS3 */
+	{GPMC_CS2, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS0 */
+	{GPMC_CS3, (IEN | PTU | PDIS | M1)},	/* QSPI1_CS1*/

Just a nitpick - Could someone audit this to ensure that only input/full duplex pins are set to IEN(Input Enable)?
Chip select (CS), SCLK, RTCLK dont seem to be candidates for input to DRA.

---
Regards,
Nishanth Menon

author
#12 lore raw

PATCH 3/7 dra7xx_evm: add SPL API, QSPI, and serial flash support

Quoted 16 lines · Nishanth Menon

[...]

Quoted 15 lines
Quoted 15 lines
board/ti/dra7xx/mux_data.h +6 -0
index 338a241..2441c55 100644
@@ -53,5 +53,15 @@ const struct pad_conf_entry 
 core_padconf_array_essential[] = {
      {UART1_RTSN, (IEN | PTU | PDIS | M3)},    /* UART1_RTSN */
      {I2C1_SDA, (IEN | PTU | PDIS | M0)},    /* I2C1_SDA */
      {I2C1_SCL, (IEN | PTU | PDIS | M0)},    /* I2C1_SCL */
+    {GPMC_A13, (IEN | PDIS | M1)},    /* QSPI1_RTCLK */
+    {GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
+    {GPMC_A15, (IEN | PDIS | M1)},    /* QSPI1_D[2] */
+    {GPMC_A16, (IEN | PDIS | M1)},    /* QSPI1_D[1] */
+    {GPMC_A17, (IEN | PDIS | M1)},    /* QSPI1_D[0] */
+    {GPMC_A18, (IEN | PDIS | M1)},    /* QSPI1_SCLK */
Quoted 9 lines
Quoted 4 lines

board/ti/dra7xx/mux_data.h const struct pad_conf_entry core_padconf_array_essential[] = { · line 65

Quoted 4 lines
board/ti/dra7xx/mux_data.h +4 -0
+    {GPMC_A3, (IEN | PDIS | M1)},    /* QSPI1_CS2 */
+    {GPMC_A4, (IEN | PDIS | M1)},    /* QSPI1_CS3 */
+    {GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
+    {GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/

Just a nitpick - Could someone audit this to ensure that only input/full duplex pins are set to IEN(Input Enable)?
Chip select (CS), SCLK, RTCLK dont seem to be candidates for input to DRA.

Yes, SCLK is just an output and IEN should not be required. RTCLK is an input to qspi to synchronise the data read, so probably I should keep IEN.
CS are also the outputs to slave, though I dont know why the dra data manual shows its type as IO.

Quoted 3 lines

---
Regards,
Nishanth Menon

author
#13 lore raw

PATCH 4/7 drivers: mtd: spi: Modify read/write command for sfl256s flash.

In reply to Sourav Poddar

Reading using the already supported read command is causing regression even while reading 4k bytes, as a result doing a page by page read.

At the end of the write sequence, write enable latch should be disabled and re enabled while doing the next page programming.

Looking for help from community on this patch.
I am using S25fl256s flash and already existing framework does not work on my board. So, I have modified the read function to do page read.

IF i use the already existing framework, read happend till 4k boundary, after which everything is read as zero. Write happens for a single page, if I dont provide a write disable at the end of the write function.

Signed-off-by Sourav Poddar <[email protected]>
---
 drivers/mtd/spi/spi_flash.c |   41 ++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 40 insertions(+), 1 deletions(-)
drivers/mtd/spi/spi_flash.c +40 -1
index 111185a..e7f1188 100644
@@ -117,6 +117,12 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
 		if (ret)
 			break;
 
+		ret = spi_flash_cmd_write_disable(flash);
+		if (ret < 0) {
+			printf("SF: disabling write failed\n");
+			break;
+		}
+
 		byte_addr += chunk_len;
 		if (byte_addr == page_size) {
 			page_addr++;

@@ -147,17 +153,50 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 		size_t len, void *data)
 {
-	u8 cmd[5];
+	unsigned long page_addr, byte_addr, page_size;
+	size_t chunk_len, actual;
+	int ret = 0;
 
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map)
 		memcpy(data, flash->memory_map + offset, len);
 
+#ifdef CONFIG_TI_QSPI
+        u8 cmd[4];
+	page_size = flash->page_size;
+	page_addr = offset / page_size;
+	byte_addr = offset % page_size;
+
+	cmd[0] = CMD_READ_ARRAY_SLOW;
+	for (actual = 0; actual < len; actual += chunk_len) {
+		chunk_len = min(len - actual, page_size - byte_addr);
+
+		cmd[1] = page_addr >> 8;
+		cmd[2] = page_addr;
+		cmd[3] = byte_addr;
+
+		ret = spi_flash_read_common(flash, cmd, sizeof(cmd), data + actual, chunk_len);
+		if (ret < 0) {
+			debug("SF: read failed");
+			break;
+		}
+
+		byte_addr += chunk_len;
+		if (byte_addr == page_size) {
+			page_addr++;
+			byte_addr = 0;
+		}
+	}
+
+	return ret;
+#else
+        u8 cmd[5];
 	cmd[0] = CMD_READ_ARRAY_FAST;
 	spi_flash_addr(offset, cmd);
 	cmd[4] = 0x00;
 
 	return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len);
+#endif
 }
 
 int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
Signature · 1 line
1.7.1
author
#14 lore raw

PATCH 5/7 drivers: mtd: qspi: Add quad read support

In reply to Sourav Poddar

From: Ravikumar Kattekola <[email protected]>

Add Quad read mode (6 pin interface) support to spi flash and ti qspi driver.

Quad mode (0x6bh on spansion) uses two extra pins (D2 and D3) for data transfer apart from the usual D0 and D1 pins thus transfering 4 bits per cycle.

Signed-off-by Ravikumar Kattekola <[email protected]>
Signed-off-by Sourav Poddar <[email protected]>
---
 drivers/mtd/spi/spi_flash.c          |  110 +++++++++++++++++++++++++++++++++-
 drivers/mtd/spi/spi_flash_internal.h |    2 +
 drivers/spi/ti_qspi.c                |   18 ++++--
 include/configs/dra7xx_evm.h         |    1 +
 include/spi.h                        |    2 +
 5 files changed, 127 insertions(+), 6 deletions(-)
drivers/mtd/spi/spi_flash.c +109 -1
index 5cc5669..f3094a2 100644
@@ -42,7 +42,12 @@ static int spi_flash_read_write(struct spi_slave *spi,
 		debug("SF: Failed to send command (%zu bytes): %d\n",
 				cmd_len, ret);
 	} else if (data_len != 0) {
-		ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END);
+		if (spi->quad_enable)
+			flags = SPI_6WIRE;
+		else
+			flags = 0;
+
+		ret = spi_xfer(spi, data_len * 8, data_out, data_in, flags | SPI_XFER_END);
 		if (ret)
 			debug("SF: Failed to transfer %zu bytes of data: %d\n",
 					data_len, ret);

@@ -198,6 +203,51 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 #endif
 }
 
+int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,
+               size_t len, void *data)
+{
+	struct spi_slave *spi = flash->spi;
+
+	unsigned long page_addr, byte_addr, page_size;
+	size_t chunk_len, actual;
+	int ret = 0;
+	u8 cmd[5];
+
+	spi->quad_enable = 1;
+	/* Handle memory-mapped SPI */
+	if (flash->memory_map)
+		memcpy(data, flash->memory_map + offset, len);
+
+	page_size = flash->page_size;
+	page_addr = offset / page_size;
+	byte_addr = offset % page_size;
+
+	cmd[0] = CMD_READ_ARRAY_QUAD;
+	for (actual = 0; actual < len; actual += chunk_len) {
+		chunk_len = min(len - actual, page_size - byte_addr);
+
+		cmd[1] = page_addr >> 8;
+		cmd[2] = page_addr;
+		cmd[3] = byte_addr;
+		cmd[4] = 0x0;
+
+		ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
+				data + actual, chunk_len);
+		if (ret < 0) {
+			debug("SF: read failed");
+			break;
+		}
+
+		byte_addr += chunk_len;
+		if (byte_addr == page_size) {
+			page_addr++;
+			byte_addr = 0;
+		}
+	}
+
+	return ret;
+}
+
 int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
 			   u8 cmd, u8 poll_bit)
 {

@@ -320,6 +370,56 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
 	return 0;
 }
 
+int spi_flash_en_quad_mode(struct spi_flash *flash)
+{
+	u8 stat, con, cd;
+	u16 cr;
+	int ret;
+	cd = CMD_WRITE_STATUS;
+
+	ret = spi_flash_cmd_write_enable(flash);
+	if (ret < 0) {
+		debug("SF: enabling write failed\n");
+		goto out;
+	}
+	ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1);
+	ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1);
+	if (ret < 0) {
+		debug("%s: SF: read CR failed\n", __func__);
+		goto out;
+	}
+	/* Byte 1 - status reg, Byte 2 - config reg */
+	cr = ((con | 0x1 << 1) << 8) | (stat << 0);
+
+	ret = spi_flash_cmd_write(flash->spi, &cd, 1, &cr, 2);
+	if (ret) {
+		debug("SF: fail to write conf register\n");
+		goto out;
+	}
+
+	ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+	if (ret < 0) {
+		debug("SF: write conf register timed out\n");
+		goto out;
+	}
+
+	ret = spi_flash_cmd(flash->spi, CMD_READ_STATUS, &stat, 1);
+	ret = spi_flash_cmd(flash->spi, CMD_READ_CONFIG, &con, 1);
+	if (ret < 0) {
+		debug("%s: SF: read CR failed\n", __func__);
+		goto out;
+	}
+	debug("%s: *** CR = %x\n", __func__, con);
+
+	ret = spi_flash_cmd_write_disable(flash);
+	if (ret < 0) {
+		debug("SF: disabling write failed\n");
+		goto out;
+	}
+out:
+	return ret;
+}
+
 #ifdef CONFIG_OF_CONTROL
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {

@@ -464,6 +564,10 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		goto err_manufacturer_probe;
 	}
 
+#ifdef CONFIG_SF_QUAD_RD
+	spi_flash_en_quad_mode(flash);
+#endif
+
 #ifdef CONFIG_OF_CONTROL
 	if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
 		debug("SF: FDT decode error\n");

@@ -507,7 +611,11 @@ void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi,
 	flash->spi = spi;
 	flash->name = name;
 
+#ifdef CONFIG_SF_QUAD_RD
+	flash->read = spi_flash_cmd_read_quad;
+#else
 	flash->read = spi_flash_cmd_read_fast;
+#endif
 	flash->write = spi_flash_cmd_write_multi;
 	flash->erase = spi_flash_cmd_erase;
drivers/mtd/spi/spi_flash_internal.h +2 -0
index 141cfa8..6dc2d6d 100644
@@ -17,11 +17,13 @@
 
 #define CMD_READ_ARRAY_SLOW		0x03
 #define CMD_READ_ARRAY_FAST		0x0b
+#define CMD_READ_ARRAY_QUAD		0x6b
 
 #define CMD_WRITE_STATUS		0x01
 #define CMD_PAGE_PROGRAM		0x02
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_READ_STATUS			0x05
+#define CMD_READ_CONFIG			0x35
 #define CMD_WRITE_ENABLE		0x06
 #define CMD_ERASE_4K			0x20
 #define CMD_ERASE_32K			0x52
drivers/spi/ti_qspi.c +13 -5
index 1973b85..12bba11 100644
@@ -72,6 +72,7 @@ static struct qspi_regs *qspi = (struct qspi_regs *)QSPI_BASE;
 #define QSPI_RD_SNGL			(1 << 16)
 #define QSPI_WR_SNGL			(2 << 16)
 #define QSPI_INVAL			(4 << 16)
+#define QSPI_RD_QUAD			(7 << 16)
 
 /* Device Control */
 #define QSPI_DD(m, n)			(m << (3 + n*8))

@@ -235,10 +236,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 			debug("tx done, status %08x\n", status);
 		}
 		if (rxp) {
-			debug("rx cmd %08x dc %08x\n",
-			      qslave->cmd | QSPI_RD_SNGL, qslave->dc);
-			writel(qslave->dc, &qspi->spi_dc);
-			writel(qslave->cmd | QSPI_RD_SNGL, &qspi->spi_cmd);
+			if (flags & SPI_6WIRE) {
+				debug("rx cmd %08x dc %08x\n",
+				      qslave->cmd | QSPI_RD_QUAD, qslave->dc);
+				writel(qslave->cmd | QSPI_RD_QUAD,
+				       &qspi->spi_cmd);
+			} else {
+				debug("rx cmd %08x dc %08x\n",
+				      qslave->cmd | QSPI_RD_SNGL, qslave->dc);
+				writel(qslave->cmd | QSPI_RD_SNGL,
+				       &qspi->spi_cmd);
+			}
 			status = readl(&qspi->spi_status);
 			timeout = QSPI_TIMEOUT;
 			while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {

@@ -250,7 +258,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 			}
 			*rxp++ = readl(&qspi->spi_data);
 			debug("rx done, status %08x, read %02x\n",
-			      status, *(rxp-1));
+				 status, *(rxp-1));
 		}
 	}
include/configs/dra7xx_evm.h +1 -0
index 0583858..f16920b 100644
@@ -57,6 +57,7 @@
 #define CONFIG_SPI_FLASH_SPANSION
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
+#define CONFIG_SF_QUAD_RD
 #define CONFIG_SF_DEFAULT_SPEED		12000000
 #define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_3
include/spi.h +2 -0
index 3fe2e1e..13280dc 100644
@@ -37,6 +37,7 @@
 #define	SPI_LSB_FIRST	0x08			/* per-word bits-on-wire */
 #define	SPI_3WIRE	0x10			/* SI/SO signals shared */
 #define	SPI_LOOP	0x20			/* loopback mode */
+#define	SPI_6WIRE	0x10			/* SI/SO signals shared */
 
 /* SPI transfer flags */
 #define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */

@@ -56,6 +57,7 @@ struct spi_slave {
 	unsigned int	bus;
 	unsigned int	cs;
 	unsigned int max_write_size;
+	bool quad_enable;
 };
 
 /*-----------------------------------------------------------------------
Signature · 1 line
1.7.1
author
#15 lore raw

PATCH 6/7 driver: spi: Add memory mapped read support

In reply to Sourav Poddar

Qspi controller has a memory mapped port which can be used for data transfers. First controller need to be configured through configuration port, then for data read switch the controller to memory mapped and read from the predefined location.

Signed-off-by Sourav Poddar <[email protected]>
---
 drivers/mtd/spi/spansion.c   |    1 +
 drivers/mtd/spi/spi_flash.c  |   31 +++++++++++++--
 drivers/spi/ti_qspi.c        |   85 +++++++++++++++++++++++++++++++++++-------
 include/configs/dra7xx_evm.h |    3 +-
 include/spi.h                |    3 +
 5 files changed, 104 insertions(+), 19 deletions(-)
drivers/mtd/spi/spansion.c +1 -0
index bc558c4..7edc369 100644
@@ -137,6 +137,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
 	flash->page_size = 256;
 	flash->sector_size = 256 * params->pages_per_sector;
 	flash->size = flash->sector_size * params->nr_sectors;
+        flash->memory_map = spi->memory_map;
 
 	return flash;
 }
drivers/mtd/spi/spi_flash.c +27 -4
index f3094a2..1482a25 100644
@@ -155,6 +155,18 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 	return ret;
 }
 
+void mem1cpy(void *dstAddr, void *srcAddr, size_t length)
+{
+	unsigned  i;
+	unsigned *DAddr = (unsigned *) (dstAddr);
+	unsigned *SAddr = (unsigned *) (srcAddr);
+	for (i = 0; i < length; i++)
+	{
+		*DAddr++ = *SAddr++;
+	}
+	return;
+}
+
 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 		size_t len, void *data)
 {

@@ -164,8 +176,13 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
 	u8 cmd[4];
 
 	/* Handle memory-mapped SPI */
-	if (flash->memory_map)
-		memcpy(data, flash->memory_map + offset, len);
+	if (flash->memory_map) {
+	        spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
+		memcpy(data, (void *)(flash->memory_map + offset), len);
+		*((unsigned *) flash->memory_map) += (len * 4);
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
+		return 0;
+	}
 
 #ifdef CONFIG_TI_QSPI
 	page_size = flash->page_size;

@@ -214,9 +231,15 @@ int spi_flash_cmd_read_quad(struct spi_flash *flash, u32 offset,
 	u8 cmd[5];
 
 	spi->quad_enable = 1;
+
 	/* Handle memory-mapped SPI */
-	if (flash->memory_map)
-		memcpy(data, flash->memory_map + offset, len);
+	if (flash->memory_map) {
+	        spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP);
+		memcpy(data, (void *)(flash->memory_map + offset), len);
+		*((unsigned *) flash->memory_map) += (len * 4);
+		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MEM_MAP_END);
+		return 0;
+	}
 
 	page_size = flash->page_size;
 	page_addr = offset / page_size;
drivers/spi/ti_qspi.c +71 -14

124 lines not on this page · raw message

include/configs/dra7xx_evm.h +2 -1
index f16920b..34a9c07 100644
@@ -58,7 +58,8 @@
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_SF_QUAD_RD
-#define CONFIG_SF_DEFAULT_SPEED		12000000
+#define CONFIG_MMAP
+#define CONFIG_SF_DEFAULT_SPEED		48000000
 #define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_3
 
 /* SPI SPL */
include/spi.h +3 -0
index 13280dc..312ca92 100644
@@ -43,6 +43,8 @@
 #define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */
 #define SPI_XFER_END	0x02			/* Deassert CS after transfer */
 
+#define SPI_XFER_MEM_MAP 0x05
+#define SPI_XFER_MEM_MAP_END 0x06
 /*-----------------------------------------------------------------------
  * Representation of a SPI slave, i.e. what we're communicating with.
  *

@@ -58,6 +60,7 @@ struct spi_slave {
 	unsigned int	cs;
 	unsigned int max_write_size;
 	bool quad_enable;
+	void *memory_map;
 };
 
 /*-----------------------------------------------------------------------
Signature · 1 line
1.7.1
author
#16 lore raw

PATCH 7/7 README: qspi usecase and testing documentation.

In reply to Sourav Poddar

Contains documentation and testing details for qspi flash interface.

Signed-off-by Sourav Poddar <[email protected]>
---
 doc/README.ti_qspi_dra_test |   38 ++++++++++++++++++++++++++++++++++
 doc/README.ti_qspi_flash    |   47 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 85 insertions(+), 0 deletions(-)
 create mode 100644 doc/README.ti_qspi_dra_test
 create mode 100644 doc/README.ti_qspi_flash
doc/README.ti_qspi_dra_test new file +38 -0
new file mode 100644
index 0000000..8910ff1
@@ -0,0 +1,38 @@
+-------------------------------------------------
+   Simple steps used to test the QSPI at U-Boot
+-------------------------------------------------
+
+For #1, build the patched U-Boot and load MLO/u-boot.img
+
+----------------------------------
+Boot from another medium like MMC
+----------------------------------
+
+DRA752 EVM # mmc dev 0
+DRA752 EVM # fatload mmc 0 0x82000000 MLO
+DRA752 EVM # fatload mmc 0 0x82000000 u-boot.img
+
+--------------------------------------------------
+Commands to erase/write u-boot/mlo to flash device
+--------------------------------------------------
+
+DRA752 EVM # sf probe 0
+[should detect the S25FL256S serial flash device]
+
+DRA752 EVM # sf erase 0 10000
+DRA752 EVM # sf erase 10000 10000
+DRA752 EVM # sf erase 20000 10000
+DRA752 EVM # sf erase 30000 10000
+DRA752 EVM # sf erase 40000 10000
+DRA752 EVM # sf erase 50000 10000
+DRA752 EVM # sf erase 60000 10000
+
+DRA752 EVM # sf write 82000000 0 10000
+DRA752 EVM # sf write 83000000 20000 80000
+
+For #2, set sysboot to QSPI-1 boot mode(SYSBOOT[5:0] = 100110) and power
+on. ROM should find the GP header at offset 0 and load/execute SPL. SPL
+then detects that ROM was in QSPI-1 mode (boot code 10) and attempts to
+find a U-Boot image header at offset 0x20000 (set in the config file)
+and proceeds to load that image using the U-Boot image payload offset/size
+from the header. It will then start U-Boot.
doc/README.ti_qspi_flash new file +47 -0

47 lines not on this page · raw message

Signature · 1 line
1.7.1