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PCI: qcom: fix pipe clock imbalance

PATCH Superseded Johan Hovold 2 participants 2 messages Apr 1, 2022 – Apr 3, 2022

Subsystems (5)
Stable branch Arm Qualcomm mailing list PCI PCI native host bridge and endpoint drivers +1 more subsystems

v1 of 2 Superseded Latest is v2 →

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Johan Hovold

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#0 lore raw

PATCH 1/1 PCI: qcom: fix pipe clock imbalance

Commit ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") introduced a clock imbalance by enabling the pipe clock both in init() and in post_init() but only disabling in post_deinit().

Note that the pipe clock was also never disabled in the init() error paths and that enabling the clock before powering up the PHY looks questionable.

Fixes ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller")
Cc [email protected] # 5.6
Cc Bjorn Andersson <[email protected]>
Signed-off-by Johan Hovold <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 6 ------
 1 file changed, 6 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -6
index b79d98e5e228..20a0e6533a1c 100644
@@ -1238,12 +1238,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
 		goto err_disable_clocks;
 	}
 
-	ret = clk_prepare_enable(res->pipe_clk);
-	if (ret) {
-		dev_err(dev, "cannot prepare/enable pipe clock\n");
-		goto err_disable_clocks;
-	}
-
 	/* Wait for reset to complete, required on SM8450 */
 	usleep_range(1000, 1500);
Signature · 1 line
2.35.1
Reviewed-by on v1 1/1
#1 lore raw
Quoted 4 lines · Johan Hovold

Commit ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") introduced a clock imbalance by enabling the pipe clock both in init() and in post_init() but only disabling in post_deinit().

Quoted 8 lines

Note that the pipe clock was also never disabled in the init() error paths and that enabling the clock before powering up the PHY looks questionable.

Fixes ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller")
Cc [email protected] # 5.6
Cc Bjorn Andersson <[email protected]>
Signed-off-by Johan Hovold <[email protected]>
Reviewed-by Bjorn Andersson <[email protected]>

Regards,
Bjorn

Quoted 24 lines
---
 drivers/pci/controller/dwc/pcie-qcom.c | 6 ------
 1 file changed, 6 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -6
index b79d98e5e228..20a0e6533a1c 100644
@@ -1238,12 +1238,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
 		goto err_disable_clocks;
 	}
 
-	ret = clk_prepare_enable(res->pipe_clk);
-	if (ret) {
-		dev_err(dev, "cannot prepare/enable pipe clock\n");
-		goto err_disable_clocks;
-	}
-
 	/* Wait for reset to complete, required on SM8450 */
 	usleep_range(1000, 1500);
Signature · 1 line
2.35.1