C-SKY(csky) Linux Intc Driver

This is about 13th patchset for C-SKY linux intc drivers and it should pair with 9th kernel patchset. Timer drivers are seperated according to requirements.

This version patch improve the comment in commit-msg and move the changelog to the end with "---", so git am will ignore the changelog.

Hope it could be merged into linux-4.20 and I'm very grateful to any help.

Guo Ren (4):
irqchip: add C-SKY SMP interrupt controller
dt-bindings: interrupt-controller: C-SKY SMP intc
irqchip: add C-SKY APB bus interrupt controller
dt-bindings: interrupt-controller: C-SKY APB intc

 .../interrupt-controller/csky,apb-intc.txt         |  62 +++++
 .../bindings/interrupt-controller/csky,mpintc.txt  |  40 +++
 drivers/irqchip/Kconfig                            |  17 ++
 drivers/irqchip/Makefile                           |   2 +
 drivers/irqchip/irq-csky-apb-intc.c                | 274 +++++++++++++++++++++
 drivers/irqchip/irq-csky-mpintc.c                  | 198 +++++++++++++++
 6 files changed, 593 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
 create mode 100644 drivers/irqchip/irq-csky-apb-intc.c
 create mode 100644 drivers/irqchip/irq-csky-mpintc.c

2.7.4

The driver is for C-SKY SMP interrupt controller. It support 16 soft-irqs, 16 private-irqs, and 992 max external-irqs, a total of 1024 interrupts.

C-SKY CPU 807/810/860 SMP/non-SMP could use it.

---
Changelog:
- Remove set_ipi_irq_mapping.
- Convert the cpumask to an interrupt-controller specific representation in driver's code, and not the SMP code's.
- pass checkpatch.pl
- Move IPI_IRQ into the driver
- Remove irq_set_default_host() and use set_ipi_irq_mapping()
- Change name with upstream feed-back
- Change irq map, reserve soft_irq & private_irq space
- Add License and Copyright
- Support set_affinity for irq balance in SMP
---

---
 drivers/irqchip/Kconfig           |   9 ++
 drivers/irqchip/Makefile          |   1 +
 drivers/irqchip/irq-csky-mpintc.c | 198 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 208 insertions(+)
 create mode 100644 drivers/irqchip/irq-csky-mpintc.c

index 383e7b7..8103f6f 100644
@@ -371,6 +371,15 @@ config QCOM_PDC
 	  Power Domain Controller driver to manage and configure wakeup
 	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
 
+config CSKY_MPINTC
+	bool "C-SKY Multi Processor Interrupt Controller"
+	depends on CSKY
+	help
+	  Say yes here to enable C-SKY SMP interrupt controller driver used
+	  for C-SKY SMP system.
+	  In fact it's not mmio map in hw and it use ld/st to visit the
+	  controller's register inside CPU.
+
 endmenu
 
 config SIFIVE_PLIC

index fbd1ec8..6b739ea 100644
@@ -87,4 +87,5 @@ obj-$(CONFIG_MESON_IRQ_GPIO)		+= irq-meson-gpio.o
 obj-$(CONFIG_GOLDFISH_PIC) 		+= irq-goldfish-pic.o
 obj-$(CONFIG_NDS32)			+= irq-ativic32.o
 obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
+obj-$(CONFIG_CSKY_MPINTC)		+= irq-csky-mpintc.o
 obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o

2.7.4

Dt-bindings doc about C-SKY Multi-processors interrupt controller.

Changelog:
- Should be: '#interrupt-cells' not 'interrupt-cells'

---
 .../bindings/interrupt-controller/csky,mpintc.txt  | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt

new file mode 100644
index 0000000..ab921f1
@@ -0,0 +1,40 @@
+===========================================
+C-SKY Multi-processors Interrupt Controller
+===========================================
+
+C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
+SMP soc, and it also could be used in non-SMP system.
+
+Interrupt number definition:
+
+  0-15  : software irq, and we use 15 as our IPI_IRQ.
+ 16-31  : private  irq, and we use 16 as the co-processor timer.
+ 31-1024: common irq for soc ip.
+
+=============================
+intc node bindings definition
+=============================
+
+	Description: Describes SMP interrupt controller
+
+	PROPERTIES
+
+	- compatible
+		Usage: required
+		Value type: <string>
+		Definition: must be "csky,mpintc"
+	- #interrupt-cells
+		Usage: required
+		Value type: <u32>
+		Definition: must be <1>
+	- interrupt-controller:
+		Usage: required
+
+Examples:
+---------
+
+	intc: interrupt-controller {
+		compatible = "csky,mpintc";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};

2.7.4

The driver is for C-SKY APB bus interrupt controller. It's a simple interrupt controller which use pending reg to detect the irq and use enable/disable reg to mask/unmask interrupt sources.

A lot of SOCs based on C-SKY CPU use the interrupt controller as root controller.

---
Changelog:
- pass checkpatch.pl.
- use "bool ret" instead of "int ret"
- add support-pulse-signal in irq-csky-apb-intc.c
- change name with upstream feed-back
- add INTC_IFR to clear irq-pending
- remove CSKY_VECIRQ_LEGENCY
- change to generic irq chip framework
- add License and Copyright
- use irq_domain_add_linear instead of leagcy
---

---
 drivers/irqchip/Kconfig             |   8 ++
 drivers/irqchip/Makefile            |   1 +
 drivers/irqchip/irq-csky-apb-intc.c | 274 ++++++++++++++++++++++++++++++++++++
 3 files changed, 283 insertions(+)
 create mode 100644 drivers/irqchip/irq-csky-apb-intc.c

index 8103f6f..41cdca0 100644
@@ -380,6 +380,14 @@ config CSKY_MPINTC
 	  In fact it's not mmio map in hw and it use ld/st to visit the
 	  controller's register inside CPU.
 
+config CSKY_APB_INTC
+	bool "C-SKY APB Interrupt Controller"
+	depends on CSKY
+	help
+	  Say yes here to enable C-SKY APB interrupt controller driver used
+	  by C-SKY single core SOC system. It use mmio map apb-bus to visit
+	  the controller's register.
+
 endmenu
 
 config SIFIVE_PLIC

index 6b739ea..72eaf53 100644
@@ -88,4 +88,5 @@ obj-$(CONFIG_GOLDFISH_PIC) 		+= irq-goldfish-pic.o
 obj-$(CONFIG_NDS32)			+= irq-ativic32.o
 obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
 obj-$(CONFIG_CSKY_MPINTC)		+= irq-csky-mpintc.o
+obj-$(CONFIG_CSKY_APB_INTC)		+= irq-csky-apb-intc.o
 obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o

2.7.4

- Dt-bindings doc about C-SKY apb bus interrupt controller.

---
 .../interrupt-controller/csky,apb-intc.txt         | 62 ++++++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt

new file mode 100644
index 0000000..44286dc
@@ -0,0 +1,62 @@
+==============================
+C-SKY APB Interrupt Controller
+==============================
+
+C-SKY APB Interrupt Controller is a simple soc interrupt controller
+on the apb bus and we only use it as root irq controller.
+
+ - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
+ - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
+ - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
+
+=============================
+intc node bindings definition
+=============================
+
+	Description: Describes APB interrupt controller
+
+	PROPERTIES
+
+	- compatible
+		Usage: required
+		Value type: <string>
+		Definition: must be "csky,apb-intc"
+				    "csky,dual-apb-intc"
+				    "csky,gx6605s-intc"
+	- #interrupt-cells
+		Usage: required
+		Value type: <u32>
+		Definition: must be <1>
+	- reg
+		Usage: required
+		Value type: <u32 u32>
+		Definition: <phyaddr size> in soc from cpu view
+	- interrupt-controller:
+		Usage: required
+	- csky,support-pulse-signal:
+		Usage: select
+		Description: to support pulse signal flag
+
+Examples:
+---------
+
+	intc: interrupt-controller@500000 {
+		compatible = "csky,apb-intc";
+		#interrupt-cells = <1>;
+		reg = <0x00500000 0x400>;
+		interrupt-controller;
+	};
+
+	intc: interrupt-controller@500000 {
+		compatible = "csky,dual-apb-intc";
+		#interrupt-cells = <1>;
+		reg = <0x00500000 0x400>;
+		interrupt-controller;
+	};
+
+	intc: interrupt-controller@500000 {
+		compatible = "csky,gx6605s-intc";
+		#interrupt-cells = <1>;
+		reg = <0x00500000 0x400>;
+		interrupt-controller;
+	};

2.7.4

Guo,

I can't really see that happening, in all honesty. On its own, this code is not very useful (it cannot compile standalone), and I haven't seen a clear indication that the rest of the architecture code is going to be merged for 4.20.

If the arch code is actually being merged for 4.20, then please add my:

to these 4 patches, and get the whole thing merged in one go.

Thanks,

	M.

Jazz is not dead. It just smells funny...

Hi Marc,

Thank you very much for your frankness.

Got it, thx for the conditional Reviewed-by.

Best Regards
Guo Ren

Hi Guo,

The Reviewed-by is not conditional, and you can apply it right now. What I meant is that I'm happy for you to get these irqchip patches merged with the rest of the architecture code.

Thanks,

	M.

Jazz is not dead. It just smells funny...

Hi Marc,

Thank you and I agree that these patches should be merged with arch code together.

Best Regards
Guo Ren