Enable IPQ9574 TSENS support
Subsystems (5)
v6 cover Enable IPQ9574 TSENS support
This patch set enables tsens in IPQ9574
Depends on
https://lore.kernel.org/linux-arm-msm/[email protected]/
[v6]:
Remove comments from tsens node in dtsi
[v5]:
Fix make DT_CHECKER_FLAGS=-m dt_binding_check and make dtbs_check errors without removing existing entries
[v4]:
Drop the sm6375-tsens and qcm2290-tsens related bindings fix as it is already posted
Remove unnecessary changes from previous version
[v3]:
Fix make DT_CHECKER_FLAGS=-m dt_binding_check and make dtbs_check errors
[v2]:
Drop the driver change (https://lore.kernel.org/lkml/b45d33d38a334aabbd52c83b0d6028af1f4c74c8.1682682753.git.quic_varada@quicinc.com/)
since the tsens device is compatible with 8074's tsens
and use 8074's compatible itself
Rename clusterX nodes as cpussX
[v1]:
Fix DT node names
[v0]:
Initial patch introducing TSENS support
Praveenkumar I (1):
dt-bindings: thermal: tsens: Add ipq9574 compatible
Varadarajan Narayanan (2):
arm64: dts: qcom: ipq9574: add tsens node
arm64: dts: qcom: ipq9574: add thermal zone nodes
.../devicetree/bindings/thermal/qcom-tsens.yaml | 6 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 218 +++++++++++++++++++++ 2 files changed, 224 insertions(+)
Signature · 1 line
2.7.4
PATCH v6 1/3 dt-bindings: thermal: tsens: Add ipq9574 compatible
From: Praveenkumar I <[email protected]>
Qualcomm IPQ9574 has tsens v2.3.1 block, which is similar to IPQ8074 tsens.
---
[v5]:
Fix dt_binding_check & dtbs_check errors without removing existing entries
[v4]:
Add description about IPQ9574 and remove unnecessary additions to the file
[v3]:
Fix dt_binding_check & dtbs_check errors (Used Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml as reference/example)
Drop 'Acked-by: Rob Herring' as suggested in review
[v2]:
Thanks to Krzysztof Kozlowski <[email protected]> for the tip to make qcom,ipq8074-tsens as fallback.
--- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +6 -0
@@ -67,6 +67,12 @@ properties: enum: - qcom,ipq8074-tsens + - description: v2 of TSENS with combined interrupt + items: + - enum: + - qcom,ipq9574-tsens + - const: qcom,ipq8074-tsens + reg: items: - description: TM registers
Signature · 1 line
2.7.4
Daniel Lezcano
AppliedRe: [PATCH v6 1/3] dt-bindings: thermal: tsens: Add ipq9574 compatible
Quoted 8 lines · Varadarajan Narayanan
From: Praveenkumar I <[email protected]>
Qualcomm IPQ9574 has tsens v2.3.1 block, which is similar to IPQ8074 tsens.
Reviewed-by Krzysztof Kozlowski <[email protected]>Signed-off-by Praveenkumar I <[email protected]>Signed-off-by Varadarajan Narayanan <[email protected]>---
Applied patch 1, thank
Signature · 5 lines
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PATCH v6 2/3 arm64: dts: qcom: ipq9574: add tsens node
In reply to Varadarajan NarayananIPQ9574 has a tsens v2.3.1 peripheral which monitors temperatures around the various subsystems on the die.
---
[v6]:
Remove comments from tsens node
[v5]:
Pad "reg" address value to 8 digits
[v2]:
Add "qcom,ipq8074-tsens" as fallback compatible
--- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574.dtsi +10 -0
@@ -206,6 +206,16 @@ #size-cells = <1>; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>;
Signature · 1 line
2.7.4
PATCH v6 3/3 arm64: dts: qcom: ipq9574: add thermal zone nodes
In reply to Varadarajan NarayananThis patch adds thermal zone nodes for the various sensors present in IPQ9574
---
[v2]:
Rename clusterX nodes as cpussX nodes
[v1]:
Fix node names
--- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 208 ++++++++++++++++++++++++++++++++++ 1 file changed, 208 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574.dtsi +208 -0
@@ -592,6 +592,214 @@ }; }; + thermal-zones { + nss-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 3>; + + trips { + nss-top-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 4>; + + trips { + ubi_0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 5>; + + trips { + ubi_1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 6>; + + trips { + ubi_2-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 7>; + + trips { + ubi_3-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 8>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 9>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 10>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 11>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 12>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 13>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <10000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wcss-phyb-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 14>; + + trips { + wcss_phyb-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 15>; + + trips { + top_glue-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
Signature · 1 line
2.7.4
Re: (subset) [PATCH v6 0/3] Enable IPQ9574 TSENS support
In reply to Varadarajan NarayananQuoted 10 lines · Varadarajan Narayanan
This patch set enables tsens in IPQ9574
Depends on
https://lore.kernel.org/linux-arm-msm/[email protected]/[v6]:
Remove comments from tsens node in dtsi
[v5]:
Fix make DT_CHECKER_FLAGS=-mdt_binding_checkand makedtbs_checkerrors without removing existing entries[...]
Applied, thanks!
[2/3] arm64: dts: qcom: ipq9574: add tsens node
commit: 2e0580e10e919b544d7be1b2b8fc48fc7dff1322
[3/3] arm64: dts: qcom: ipq9574: add thermal zone nodes
commit: 581dcbe60b6390c633f318a29db41d1df642e6d8Best regards,
Signature · 1 line
Bjorn Andersson <[email protected]>