Enable Power Modes Support for SAMA7D65 SoC

From: Ryan Wanner <[email protected]>

Add SAMA7D65 DDR3phy compatible to DT bindings documentation

Signed-off-by Ryan Wanner <[email protected]>

---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
 1 file changed, 2 insertions(+)

From: Ryan Wanner <[email protected]>

Add SAMA7D65 SFRBU compatible string to DT bindings documentation

Signed-off-by Ryan Wanner <[email protected]>

---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/mfd/syscon.yaml +0 -0

index 51d896c88dafa..727292ffe092e 100644

Quoted 14 lines · On Mon, Feb 10, 2025 at 02:13:02PM -0700, [email protected] wrote:

From: Ryan Wanner <[email protected]>

Add SAMA7D65 SFRBU compatible string to DT bindings documentation

Signed-off-by Ryan Wanner <[email protected]>

---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/mfd/syscon.yaml +0 -0

index 51d896c88dafa..727292ffe092e 100644

Documentation/devicetree/bindings/mfd/syscon.yaml select: · line 94

Quoted 4 lines

Documentation/devicetree/bindings/mfd/syscon.yaml +1 -0

@@ -91,6 +91,7 @@ select:
           - microchip,mpfs-sysreg-scb
           - microchip,sam9x60-sfr
           - microchip,sama7d65-ddr3phy
+          - microchip,sama7d65-sfrbu

You got comment on #1 of your v1, so if you make exactly the same mistake in other patches then fix it there as well.

Apply v1 Rob's comments to all your patches.

Quoted 13 lines

Documentation/devicetree/bindings/mfd/syscon.yaml select: · line 94

Quoted 9 lines

Documentation/devicetree/bindings/mfd/syscon.yaml +1 -0

index 51d896c88dafa..727292ffe092e 100644
@@ -91,6 +91,7 @@ select:
           - microchip,mpfs-sysreg-scb
           - microchip,sam9x60-sfr
           - microchip,sama7d65-ddr3phy
+          - microchip,sama7d65-sfrbu

You got comment on #1 of your v1, so if you make exactly the same mistake in other patches then fix it there as well.

Quoted 1 line

Apply v1 Rob's comments to all your patches.

Actually, this patch v1 did put it in both lists, but here it got dropped from the second list:
https://lore.kernel.org/all/[email protected]/

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RSTC compatible to DT bindings documentation. The sama7d65-rstc is compatible with the sama7g5-rstc.

Signed-off-by Ryan Wanner <[email protected]>

---
 .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml   | 5 +++++
 1 file changed, 5 insertions(+)

Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +0 -0

index 98465d26949ee..a1c21c3880f9d 100644

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTC compatible to DT bindings documentation.

Signed-off-by Ryan Wanner <[email protected]>

---
 .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml          | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +0 -0

index c8bb2eef442dd..0c878331170b4 100644

Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +0 -0

   reg:
     maxItems: 1

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTC compatible to DT bindings documentation.

Signed-off-by Ryan Wanner <[email protected]>

---
 .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml          | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +0 -0

index c8bb2eef442dd..0c878331170b4 100644

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTT compatible to DT bindings documentation.

Signed-off-by Ryan Wanner <[email protected]>

---
 .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml         | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +0 -0

index a7f6c1d1a08ab..48a2e013a6b24 100644

Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +1 -0

+          - const: atmel,at91sam9260-rtt
       - items:
           - const: microchip,sama7g5-rtt
           - const: microchip,sam9x60-rtt

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTT compatible to DT bindings documentation.

Signed-off-by Ryan Wanner <[email protected]>

---
 .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml         | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +0 -0

index a7f6c1d1a08ab..48a2e013a6b24 100644

From: Li Bin <[email protected]>

For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error" during recalibrating the impedance in BootStrap.
We found that the impedance value saved in at91_suspend_finish() before the DDR entered self-refresh mode did not match the resistor values. The ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to select the different impedance setting.
But these gray code are incorrect, a workaournd from design team fixed the bug in the calibration logic. The ZDATA contains four independent impedance elements, but the algorithm combined the four elements into one. The elements were fixed using properly shifted offsets.

Signed-off-by Li Bin <[email protected]>

[[email protected]: fix indentation and combine 2 patches]

Signed-off-by Nicolas Ferre <[email protected]>

Tested-by Ryan Wanner <[email protected]>

Tested-by Durai Manickam KR <[email protected]>

Tested-by Andrei Simion <[email protected]>

---
 arch/arm/mach-at91/pm.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

arch/arm/mach-at91/pm.c +11 -10

index 05a1547642b60..6c3e6aa22606f 100644
@@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz;
 
 static int at91_suspend_finish(unsigned long val)
 {
-	unsigned char modified_gray_code[] = {
-		0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
-		0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
-		0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
-		0x10, 0x11,
+	/* SYNOPSYS workaround to fix a bug in the calibration logic */
+	unsigned char modified_fix_code[] = {
+		0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18,
+		0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13,
+		0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14,
+		0x1e, 0x1f,
 	};
 	unsigned int tmp, index;
 	int i;

@@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val)
 		 * restore the ZQ0SR0 with the value saved here. But the
 		 * calibration is buggy and restoring some values from ZQ0SR0
 		 * is forbidden and risky thus we need to provide processed
-		 * values for these (modified gray code values).
+		 * values for these.
 		 */
 		tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
 
 		/* Store pull-down output impedance select. */
 		index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
-		soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
+		soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF;
 
 		/* Store pull-up output impedance select. */
 		index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
-		soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+		soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF;
 
 		/* Store pull-down on-die termination impedance select. */
 		index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
-		soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+		soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF;
 
 		/* Store pull-up on-die termination impedance select. */
 		index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
-		soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+		soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF;
 
 		/*
 		 * The 1st 8 words of memory might get corrupted in the process

From: Ryan Wanner <[email protected]>

Add support for SAMA7D65 new compatible strings in pm.c file for wakeup source IDs and PMC.
This is the first bits of PM for this new SoC. PM depends on other patches.

Signed-off-by Ryan Wanner <[email protected]>

[[email protected]: split patch and address only the pm.c changes]

Signed-off-by Nicolas Ferre <[email protected]>

---
 arch/arm/mach-at91/pm.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

arch/arm/mach-at91/pm.c +0 -0

index 6c3e6aa22606f..1eec68e92f8d8 100644

arch/arm/mach-at91/pm.c +2 -1

 	{ .compatible = "microchip,sama7g5-rtt",	.data = &ws_info[4] },
 	{ /* sentinel */ }
 };

@@ -1379,6 +1382,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
 	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
 	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
 	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
+	{ .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
 	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
 	{ /* sentinel */ },
 };

@@ -1672,7 +1676,7 @@ void __init sama7_pm_init(void)
 	at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
 	at91_pm_init(NULL);
 
-	soc_pm.ws_ids = sama7g5_ws_ids;
+	soc_pm.ws_ids = sama7_ws_ids;
 	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
 
 	soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);

From: Ryan Wanner <[email protected]>

Add config check that enables Backup mode for SAMA7D65 SoC.

Add SHDWC_SR read to clear the status bits once finished exiting low power modes.

This is only for SAMA7D65 SoCs.

Signed-off-by Ryan Wanner <[email protected]>

---
 arch/arm/mach-at91/pm.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

arch/arm/mach-at91/pm.c +0 -0

index 1eec68e92f8d8..55cab31ce1ecb 100644

arch/arm/mach-at91/pm.c +2 -1

 }
 
 

@@ -1065,7 +1068,8 @@ static int __init at91_pm_backup_init(void)
 	int ret = -ENODEV, located = 0;
 
 	if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
-	    !IS_ENABLED(CONFIG_SOC_SAMA7G5))
+	    !IS_ENABLED(CONFIG_SOC_SAMA7G5) &&
+	    !IS_ENABLED(CONFIG_SOC_SAMA7D65))
 		return -EPERM;
 
 	if (!at91_is_pm_mode_active(AT91_PM_BACKUP))

From: Ryan Wanner <[email protected]>

New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a total of 10 main clocks that need to be saved for ULP0 mode.

Add mck_count member to at91_pm_data, this will be used to determine how many mcks need to be saved. In the mck_count member will also make sure that no unnecessary clock settings are written during mck_ps_restore.

Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low power modes.

Signed-off-by Ryan Wanner <[email protected]>

Acked-by Nicolas Ferre <[email protected]>

---
 arch/arm/mach-at91/pm.c              | 19 +++++-
 arch/arm/mach-at91/pm.h              |  1 +
 arch/arm/mach-at91/pm_data-offsets.c |  2 +
 arch/arm/mach-at91/pm_suspend.S      | 97 ++++++++++++++++++++++++++--
 4 files changed, 110 insertions(+), 9 deletions(-)

arch/arm/mach-at91/pm.c +1 -0

index 55cab31ce1ecb..50bada544eede 100644
@@ -1337,6 +1337,7 @@ struct pmc_info {
 	unsigned long uhp_udp_mask;
 	unsigned long mckr;
 	unsigned long version;
+	unsigned long mck_count;>  };
 
 static const struct pmc_info pmc_infos[] __initconst = {

arch/arm/mach-at91/pm.c +3 -0

 	},
 
 	{
 		.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
 		.mckr = 0x30,
 		.version = AT91_PMC_V1,
+		.mck_count = 1,
 	},
 	{
 		.uhp_udp_mask = AT91SAM926x_PMC_UHP,
 		.mckr = 0x30,
 		.version = AT91_PMC_V1,
+		.mck_count = 1,
 	},
 	{	.uhp_udp_mask = 0,
 		.mckr = 0x30,
 		.version = AT91_PMC_V1,
+		.mck_count = 1,
 	},

arch/arm/mach-at91/pm.c +8 -1

+	},
+	{
+		.uhp_udp_mask = AT91SAM926x_PMC_UHP,
+		.mckr = 0x28,
+		.version = AT91_PMC_V2,
+		.mck_count = 10,
 	},
 
 };

@@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
 	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
 	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
 	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
-	{ .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
+	{ .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
 	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
 	{ /* sentinel */ },
 };

@@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
 	soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
 	soc_pm.data.pmc_mckr_offset = pmc->mckr;
 	soc_pm.data.pmc_version = pmc->version;
+	soc_pm.data.pmc_mck_count = pmc->mck_count;
 
 	if (pm_idle)
 		arm_pm_idle = pm_idle;

arch/arm/mach-at91/pm.c +0 -0

 		[AT91_PM_ULP1]		= AT91_PM_IOMAP(SFRBU) |
 					  AT91_PM_IOMAP(SHDWC) |
 					  AT91_PM_IOMAP(ETHC),

arch/arm/mach-at91/pm.h +1 -0

index 53bdc9000e447..ccde9c8728c27 100644
@@ -39,6 +39,7 @@ struct at91_pm_data {
 	unsigned int suspend_mode;
 	unsigned int pmc_mckr_offset;
 	unsigned int pmc_version;
+	unsigned int pmc_mck_count;
 };
 #endif
 

arch/arm/mach-at91/pm_data-offsets.c +2 -0

index 40bd4e8fe40a5..59a4838038381 100644
@@ -18,6 +18,8 @@ int main(void)
 						 pmc_mckr_offset));
 	DEFINE(PM_DATA_PMC_VERSION,	offsetof(struct at91_pm_data,
 						 pmc_version));
+	DEFINE(PM_DATA_PMC_MCK_COUNT,	offsetof(struct at91_pm_data,
+						 pmc_mck_count));
 
 	return 0;
 }

arch/arm/mach-at91/pm_suspend.S +1 -1

index e5869cca5e791..2bbcbb26adb28 100644
@@ -814,17 +814,19 @@ sr_dis_exit:
 .endm
 
 /**
- * at91_mckx_ps_enable:	save MCK1..4 settings and switch it to main clock
+ * at91_mckx_ps_enable:	save MCK settings and switch it to main clock
  *

arch/arm/mach-at91/pm_suspend.S +30 -0

 	/* Write MCK ID to retrieve the settings. */

@@ -850,7 +852,37 @@ e_save_mck3:
 	b	e_ps
 
 e_save_mck4:
+	cmp	tmp1, #4
+	bne	e_save_mck5
 	str	tmp2, .saved_mck4
+	b	e_ps
+
+e_save_mck5:
+	cmp	tmp1, #5
+	bne	e_save_mck6
+	str	tmp2, .saved_mck5
+	b	e_ps
+
+e_save_mck6:
+	cmp	tmp1, #6
+	bne	e_save_mck7
+	str	tmp2, .saved_mck6
+	b	e_ps
+
+e_save_mck7:
+	cmp	tmp1, #7
+	bne	e_save_mck8
+	str	tmp2, .saved_mck7
+	b	e_ps
+
+e_save_mck8:
+	cmp	tmp1, #8
+	bne	e_save_mck9
+	str	tmp2, .saved_mck8
+	b	e_ps
+
+e_save_mck9:
+	str	tmp2, .saved_mck9
 
 e_ps:
 	/* Use CSS=MAINCK and DIV=1. */

arch/arm/mach-at91/pm_suspend.S +0 -0

  *
  * Side effects: overwrites tmp1, tmp2
  */
 .macro at91_mckx_ps_restore
 #ifdef CONFIG_SOC_SAMA7

arch/arm/mach-at91/pm_suspend.S +30 -0

 r_save_mck1:

@@ -902,7 +936,37 @@ r_save_mck3:
 	b	r_ps
 
 r_save_mck4:
+	cmp	tmp1, #4
+	bne	r_save_mck5
 	ldr	tmp2, .saved_mck4
+	b	r_ps
+
+r_save_mck5:
+	cmp	tmp1, #5
+	bne	r_save_mck6
+	ldr	tmp2, .saved_mck5
+	b	r_ps
+
+r_save_mck6:
+	cmp	tmp1, #6
+	bne	r_save_mck7
+	ldr	tmp2, .saved_mck6
+	b	r_ps
+
+r_save_mck7:
+	cmp	tmp1, #7
+	bne	r_save_mck8
+	ldr	tmp2, .saved_mck7
+	b	r_ps
+
+r_save_mck8:
+	cmp	tmp1, #8
+	bne	r_save_mck9
+	ldr	tmp2, .saved_mck8
+	b	r_ps
+
+r_save_mck9:
+	ldr	tmp2, .saved_mck9
 
 r_ps:
 	/* Write MCK ID to retrieve the settings. */

arch/arm/mach-at91/pm_suspend.S +18 -0

 	b	r_loop
 r_done:
 #endif

@@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
 	str	tmp1, .memtype
 	ldr	tmp1, [r0, #PM_DATA_MODE]
 	str	tmp1, .pm_mode
+#ifdef CONFIG_SOC_SAMA7
+	ldr	tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
+	str	tmp1, .mck_count
+#endif
 
 	/*
 	 * ldrne below are here to preload their address in the TLB as access

@@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
 	.word 0
 .pmc_version:
 	.word 0
+#ifdef CONFIG_SOC_SAMA7
+.mck_count:
+	.word 0
+#endif
 .saved_mckr:
 	.word 0
 .saved_pllar:

@@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
 	.word 0
 .saved_mck4:
 	.word 0
+.saved_mck5:
+	.word 0
+.saved_mck6:
+	.word 0
+.saved_mck7:
+	.word 0
+.saved_mck8:
+	.word 0
+.saved_mck9:
+	.word 0
 #endif
 
 ENTRY(at91_pm_suspend_in_sram_sz)

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Hi, Ryan,

Quoted 4 lines · On 10.02.2025 23:13, [email protected] wrote:

From: Ryan Wanner <[email protected]>

New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a total of 10 main clocks that need to be saved for ULP0 mode.

Isn't 9 the total number of MCKs that are handled in the last/first phase of suspend/resume?

Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.

Quoted 8 lines

Add mck_count member to at91_pm_data, this will be used to determine how many mcks need to be saved. In the mck_count member will also make sure that no unnecessary clock settings are written during mck_ps_restore.

Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low power modes.

Can you explain why this clear need to be done? The commit message should answer to the "what?" and "why?" questions.

Quoted 22 lines

Signed-off-by Ryan Wanner <[email protected]>

Acked-by Nicolas Ferre <[email protected]>

---
 arch/arm/mach-at91/pm.c              | 19 +++++-
 arch/arm/mach-at91/pm.h              |  1 +
 arch/arm/mach-at91/pm_data-offsets.c |  2 +
 arch/arm/mach-at91/pm_suspend.S      | 97 ++++++++++++++++++++++++++--
 4 files changed, 110 insertions(+), 9 deletions(-)

arch/arm/mach-at91/pm.c +1 -0

index 55cab31ce1ecb..50bada544eede 100644
@@ -1337,6 +1337,7 @@ struct pmc_info {
      unsigned long uhp_udp_mask;
      unsigned long mckr;
      unsigned long version;
+     unsigned long mck_count;>  };
 
 static const struct pmc_info pmc_infos[] __initconst = {

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1348

Quoted 4 lines

arch/arm/mach-at91/pm.c +1 -0

@@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
              .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,

As this member is used only for SAMA7 SoCs I would drop it here and above (where initialized with 1).

Quoted 19 lines

arch/arm/mach-at91/pm.c +3 -0

      },
 
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {       .uhp_udp_mask = 0,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1377

Quoted 10 lines

arch/arm/mach-at91/pm.c +2 -0

      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 1,
      },
      {
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 5,

I'm not sure mck_count is a good name when used like proposed in this patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for SAMA7D65.

Maybe, better change it here to 4 (.mck_count = 4) and to 9 above (.mck_count = 9) and adjust properly the assembly macros (see below)? What do you think?

Quoted 25 lines

arch/arm/mach-at91/pm.c +8 -1

+     },
+     {
+             .uhp_udp_mask = AT91SAM926x_PMC_UHP,
+             .mckr = 0x28,
+             .version = AT91_PMC_V2,
+             .mck_count = 10,
      },
 
 };

@@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
      { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
      { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
      { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
-     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
+     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
      { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
      { /* sentinel */ },
 };

@@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
      soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
      soc_pm.data.pmc_mckr_offset = pmc->mckr;
      soc_pm.data.pmc_version = pmc->version;
+     soc_pm.data.pmc_mck_count = pmc->mck_count;
 

arch/arm/mach-at91/pm.c void __init sama7_pm_init(void) · line 1677

Quoted 9 lines

arch/arm/mach-at91/pm.c +2 -1

      if (pm_idle)
              arm_pm_idle = pm_idle;

@@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
              AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
      };
      static const u32 iomaps[] __initconst = {
-             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU),
+             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU) |
+                                       AT91_PM_IOMAP(SHDWC),

In theory, as the wakeup sources can also resumes the system from standby (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and the wakeup sources covered by the SHDWC_SR register don't apply to standby (WFI).

Quoted 41 lines

arch/arm/mach-at91/pm.c +0 -0

              [AT91_PM_ULP1]          = AT91_PM_IOMAP(SFRBU) |
                                        AT91_PM_IOMAP(SHDWC) |
                                        AT91_PM_IOMAP(ETHC),

arch/arm/mach-at91/pm.h +1 -0

index 53bdc9000e447..ccde9c8728c27 100644
@@ -39,6 +39,7 @@ struct at91_pm_data {
      unsigned int suspend_mode;
      unsigned int pmc_mckr_offset;
      unsigned int pmc_version;
+     unsigned int pmc_mck_count;
 };
 #endif
 

arch/arm/mach-at91/pm_data-offsets.c +2 -0

index 40bd4e8fe40a5..59a4838038381 100644
@@ -18,6 +18,8 @@ int main(void)
                                               pmc_mckr_offset));
      DEFINE(PM_DATA_PMC_VERSION,     offsetof(struct at91_pm_data,
                                               pmc_version));
+     DEFINE(PM_DATA_PMC_MCK_COUNT,   offsetof(struct at91_pm_data,
+                                              pmc_mck_count));
 
      return 0;
 }

arch/arm/mach-at91/pm_suspend.S +1 -1

index e5869cca5e791..2bbcbb26adb28 100644
@@ -814,17 +814,19 @@ sr_dis_exit:
 .endm
 
 /**
- * at91_mckx_ps_enable:      save MCK1..4 settings and switch it to main clock
+ * at91_mckx_ps_enable:      save MCK settings and switch it to main clock
  *

arch/arm/mach-at91/pm_suspend.S sr_dis_exit: · line 826

Quoted 10 lines

arch/arm/mach-at91/pm_suspend.S +3 -2

- * Side effects: overwrites tmp1, tmp2
+ * Side effects: overwrites tmp1, tmp2, tmp3
  */
 .macro at91_mckx_ps_enable
 #ifdef CONFIG_SOC_SAMA7
      ldr     pmc, .pmc_base
+     ldr     tmp3, .mck_count
 
-     /* There are 4 MCKs we need to handle: MCK1..4 */
+     /* Start at MCK1 and go until MCK_count */

s/MCK_count/mck_count to align with the mck_count above.

arch/arm/mach-at91/pm_suspend.S sr_dis_exit: · line 830

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +2 -1

      mov     tmp1, #1
-e_loop:      cmp     tmp1, #5
+e_loop:
+     cmp     tmp1, tmp3
      beq     e_done

If providing mck_count = 4 (for SAMA7G5) and mck_count = 9 (for SAMA7D65) you can change this to:

bqt e_done

Quoted 41 lines

arch/arm/mach-at91/pm_suspend.S +30 -0

      /* Write MCK ID to retrieve the settings. */

@@ -850,7 +852,37 @@ e_save_mck3:
      b       e_ps
 
 e_save_mck4:
+     cmp     tmp1, #4
+     bne     e_save_mck5
      str     tmp2, .saved_mck4
+     b       e_ps
+
+e_save_mck5:
+     cmp     tmp1, #5
+     bne     e_save_mck6
+     str     tmp2, .saved_mck5
+     b       e_ps
+
+e_save_mck6:
+     cmp     tmp1, #6
+     bne     e_save_mck7
+     str     tmp2, .saved_mck6
+     b       e_ps
+
+e_save_mck7:
+     cmp     tmp1, #7
+     bne     e_save_mck8
+     str     tmp2, .saved_mck7
+     b       e_ps
+
+e_save_mck8:
+     cmp     tmp1, #8
+     bne     e_save_mck9
+     str     tmp2, .saved_mck8
+     b       e_ps
+
+e_save_mck9:
+     str     tmp2, .saved_mck9
 
 e_ps:
      /* Use CSS=MAINCK and DIV=1. */

arch/arm/mach-at91/pm_suspend.S e_done: · line 905

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +1 -1

@@ -870,17 +902,19 @@ e_done:
 .endm
 
 /**
- * at91_mckx_ps_restore: restore MCK1..4 settings
+ * at91_mckx_ps_restore: restore MCKx settings

s/MCKx/MCK to align with the description from at91_mckx_ps_enable

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +0 -0

  *
  * Side effects: overwrites tmp1, tmp2
  */
 .macro at91_mckx_ps_restore
 #ifdef CONFIG_SOC_SAMA7

arch/arm/mach-at91/pm_suspend.S e_done: · line 918

Quoted 10 lines

arch/arm/mach-at91/pm_suspend.S +4 -2

      ldr     pmc, .pmc_base
+     ldr     tmp2, .mck_count
 
-     /* There are 4 MCKs we need to handle: MCK1..4 */
+     /* Start from MCK1 and go up to MCK_count */
      mov     tmp1, #1
-r_loop:      cmp     tmp1, #5
+r_loop:
+     cmp     tmp1, tmp2
      beq     r_done

Same here:
bgt r_done

should be enough if providing mck_count = 4 or 9

Quoted 41 lines

arch/arm/mach-at91/pm_suspend.S +30 -0

 r_save_mck1:

@@ -902,7 +936,37 @@ r_save_mck3:
      b       r_ps
 
 r_save_mck4:
+     cmp     tmp1, #4
+     bne     r_save_mck5
      ldr     tmp2, .saved_mck4
+     b       r_ps
+
+r_save_mck5:
+     cmp     tmp1, #5
+     bne     r_save_mck6
+     ldr     tmp2, .saved_mck5
+     b       r_ps
+
+r_save_mck6:
+     cmp     tmp1, #6
+     bne     r_save_mck7
+     ldr     tmp2, .saved_mck6
+     b       r_ps
+
+r_save_mck7:
+     cmp     tmp1, #7
+     bne     r_save_mck8
+     ldr     tmp2, .saved_mck7
+     b       r_ps
+
+r_save_mck8:
+     cmp     tmp1, #8
+     bne     r_save_mck9
+     ldr     tmp2, .saved_mck8
+     b       r_ps
+
+r_save_mck9:
+     ldr     tmp2, .saved_mck9
 
 r_ps:
      /* Write MCK ID to retrieve the settings. */

arch/arm/mach-at91/pm_suspend.S r_ps: · line 988

Quoted 4 lines

arch/arm/mach-at91/pm_suspend.S +1 -0

@@ -921,6 +985,7 @@ r_ps:
      wait_mckrdy tmp1
 
      add     tmp1, tmp1, #1
+     ldr     tmp2, .mck_count

Or you can add tmp4 for this

Quoted 42 lines

arch/arm/mach-at91/pm_suspend.S +18 -0

      b       r_loop
 r_done:
 #endif

@@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
      str     tmp1, .memtype
      ldr     tmp1, [r0, #PM_DATA_MODE]
      str     tmp1, .pm_mode
+#ifdef CONFIG_SOC_SAMA7
+     ldr     tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
+     str     tmp1, .mck_count
+#endif
 
      /*
       * ldrne below are here to preload their address in the TLB as access

@@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
      .word 0
 .pmc_version:
      .word 0
+#ifdef CONFIG_SOC_SAMA7
+.mck_count:
+     .word 0
+#endif
 .saved_mckr:
      .word 0
 .saved_pllar:

@@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
      .word 0
 .saved_mck4:
      .word 0
+.saved_mck5:
+     .word 0
+.saved_mck6:
+     .word 0
+.saved_mck7:
+     .word 0
+.saved_mck8:
+     .word 0
+.saved_mck9:
+     .word 0
 #endif
 
 ENTRY(at91_pm_suspend_in_sram_sz)

Quoted 5 lines · Claudiu Beznea

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Hi, Ryan,

Quoted 8 lines

Quoted 4 lines · On 10.02.2025 23:13, [email protected] wrote:

From: Ryan Wanner <[email protected]>

New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a total of 10 main clocks that need to be saved for ULP0 mode.

Isn't 9 the total number of MCKs that are handled in the last/first phase of suspend/resume?

Yes I was including 10 to match the indexing in the mck_count variable. Since bgt instruction was suggested I will correct this to reflect the true behavior of the change.

Quoted 79 lines

Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.

Quoted 8 lines

Add mck_count member to at91_pm_data, this will be used to determine how many mcks need to be saved. In the mck_count member will also make sure that no unnecessary clock settings are written during mck_ps_restore.

Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low power modes.

Can you explain why this clear need to be done? The commit message should answer to the "what?" and "why?" questions.

Quoted 22 lines

Signed-off-by Ryan Wanner <[email protected]>

Acked-by Nicolas Ferre <[email protected]>

---
 arch/arm/mach-at91/pm.c              | 19 +++++-
 arch/arm/mach-at91/pm.h              |  1 +
 arch/arm/mach-at91/pm_data-offsets.c |  2 +
 arch/arm/mach-at91/pm_suspend.S      | 97 ++++++++++++++++++++++++++--
 4 files changed, 110 insertions(+), 9 deletions(-)

arch/arm/mach-at91/pm.c +1 -0

index 55cab31ce1ecb..50bada544eede 100644
@@ -1337,6 +1337,7 @@ struct pmc_info {
      unsigned long uhp_udp_mask;
      unsigned long mckr;
      unsigned long version;
+     unsigned long mck_count;>  };
 
 static const struct pmc_info pmc_infos[] __initconst = {

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1348

Quoted 4 lines

arch/arm/mach-at91/pm.c +1 -0

@@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
              .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,

As this member is used only for SAMA7 SoCs I would drop it here and above (where initialized with 1).

Quoted 19 lines

arch/arm/mach-at91/pm.c +3 -0

      },
 
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {       .uhp_udp_mask = 0,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1377

Quoted 10 lines

arch/arm/mach-at91/pm.c +2 -0

      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 1,
      },
      {
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 5,

I'm not sure mck_count is a good name when used like proposed in this patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for SAMA7D65.

Quoted 3 lines

Maybe, better change it here to 4 (.mck_count = 4) and to 9 above (.mck_count = 9) and adjust properly the assembly macros (see below)? What do you think?

Yes I think this is better and cleaner to read. Should this mck_count match the pmc_mck_count variable name? Or should this be more descriptive or would mcks be sufficient.

Quoted 25 lines

Quoted 25 lines

arch/arm/mach-at91/pm.c +8 -1

+     },
+     {
+             .uhp_udp_mask = AT91SAM926x_PMC_UHP,
+             .mckr = 0x28,
+             .version = AT91_PMC_V2,
+             .mck_count = 10,
      },
 
 };

@@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
      { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
      { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
      { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
-     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
+     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
      { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
      { /* sentinel */ },
 };

@@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
      soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
      soc_pm.data.pmc_mckr_offset = pmc->mckr;
      soc_pm.data.pmc_version = pmc->version;
+     soc_pm.data.pmc_mck_count = pmc->mck_count;
 

Quoted 14 lines

arch/arm/mach-at91/pm.c void __init sama7_pm_init(void) · line 1677

Quoted 9 lines

arch/arm/mach-at91/pm.c +2 -1

      if (pm_idle)
              arm_pm_idle = pm_idle;

@@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
              AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
      };
      static const u32 iomaps[] __initconst = {
-             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU),
+             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU) |
+                                       AT91_PM_IOMAP(SHDWC),

In theory, as the wakeup sources can also resumes the system from standby (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and the wakeup sources covered by the SHDWC_SR register don't apply to standby (WFI).

The device can wake up from an RTT or RTC alarm event on both the standby power mode and the ULP0 power mode, since the RTT/RTC are included in the SHDWC_SR I think it is safe to have this. If I understand what you are asking correctly.

Quoted 226 lines

Quoted 41 lines

arch/arm/mach-at91/pm.c +0 -0

              [AT91_PM_ULP1]          = AT91_PM_IOMAP(SFRBU) |
                                        AT91_PM_IOMAP(SHDWC) |
                                        AT91_PM_IOMAP(ETHC),

arch/arm/mach-at91/pm.h +1 -0

index 53bdc9000e447..ccde9c8728c27 100644
@@ -39,6 +39,7 @@ struct at91_pm_data {
      unsigned int suspend_mode;
      unsigned int pmc_mckr_offset;
      unsigned int pmc_version;
+     unsigned int pmc_mck_count;
 };
 #endif
 

arch/arm/mach-at91/pm_data-offsets.c +2 -0

index 40bd4e8fe40a5..59a4838038381 100644
@@ -18,6 +18,8 @@ int main(void)
                                               pmc_mckr_offset));
      DEFINE(PM_DATA_PMC_VERSION,     offsetof(struct at91_pm_data,
                                               pmc_version));
+     DEFINE(PM_DATA_PMC_MCK_COUNT,   offsetof(struct at91_pm_data,
+                                              pmc_mck_count));
 
      return 0;
 }

arch/arm/mach-at91/pm_suspend.S +1 -1

index e5869cca5e791..2bbcbb26adb28 100644
@@ -814,17 +814,19 @@ sr_dis_exit:
 .endm
 
 /**
- * at91_mckx_ps_enable:      save MCK1..4 settings and switch it to main clock
+ * at91_mckx_ps_enable:      save MCK settings and switch it to main clock
  *

arch/arm/mach-at91/pm_suspend.S sr_dis_exit: · line 826

Quoted 10 lines

arch/arm/mach-at91/pm_suspend.S +3 -2

- * Side effects: overwrites tmp1, tmp2
+ * Side effects: overwrites tmp1, tmp2, tmp3
  */
 .macro at91_mckx_ps_enable
 #ifdef CONFIG_SOC_SAMA7
      ldr     pmc, .pmc_base
+     ldr     tmp3, .mck_count
 
-     /* There are 4 MCKs we need to handle: MCK1..4 */
+     /* Start at MCK1 and go until MCK_count */

s/MCK_count/mck_count to align with the mck_count above.

arch/arm/mach-at91/pm_suspend.S sr_dis_exit: · line 830

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +2 -1

      mov     tmp1, #1
-e_loop:      cmp     tmp1, #5
+e_loop:
+     cmp     tmp1, tmp3
      beq     e_done

If providing mck_count = 4 (for SAMA7G5) and mck_count = 9 (for SAMA7D65) you can change this to:

bqt e_done

Quoted 41 lines

arch/arm/mach-at91/pm_suspend.S +30 -0

      /* Write MCK ID to retrieve the settings. */

@@ -850,7 +852,37 @@ e_save_mck3:
      b       e_ps
 
 e_save_mck4:
+     cmp     tmp1, #4
+     bne     e_save_mck5
      str     tmp2, .saved_mck4
+     b       e_ps
+
+e_save_mck5:
+     cmp     tmp1, #5
+     bne     e_save_mck6
+     str     tmp2, .saved_mck5
+     b       e_ps
+
+e_save_mck6:
+     cmp     tmp1, #6
+     bne     e_save_mck7
+     str     tmp2, .saved_mck6
+     b       e_ps
+
+e_save_mck7:
+     cmp     tmp1, #7
+     bne     e_save_mck8
+     str     tmp2, .saved_mck7
+     b       e_ps
+
+e_save_mck8:
+     cmp     tmp1, #8
+     bne     e_save_mck9
+     str     tmp2, .saved_mck8
+     b       e_ps
+
+e_save_mck9:
+     str     tmp2, .saved_mck9
 
 e_ps:
      /* Use CSS=MAINCK and DIV=1. */

arch/arm/mach-at91/pm_suspend.S e_done: · line 905

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +1 -1

@@ -870,17 +902,19 @@ e_done:
 .endm
 
 /**
- * at91_mckx_ps_restore: restore MCK1..4 settings
+ * at91_mckx_ps_restore: restore MCKx settings

s/MCKx/MCK to align with the description from at91_mckx_ps_enable

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +0 -0

  *
  * Side effects: overwrites tmp1, tmp2
  */
 .macro at91_mckx_ps_restore
 #ifdef CONFIG_SOC_SAMA7

arch/arm/mach-at91/pm_suspend.S e_done: · line 918

Quoted 10 lines

arch/arm/mach-at91/pm_suspend.S +4 -2

      ldr     pmc, .pmc_base
+     ldr     tmp2, .mck_count
 
-     /* There are 4 MCKs we need to handle: MCK1..4 */
+     /* Start from MCK1 and go up to MCK_count */
      mov     tmp1, #1
-r_loop:      cmp     tmp1, #5
+r_loop:
+     cmp     tmp1, tmp2
      beq     r_done

Same here:
bgt r_done

should be enough if providing mck_count = 4 or 9

Quoted 41 lines

arch/arm/mach-at91/pm_suspend.S +30 -0

 r_save_mck1:

@@ -902,7 +936,37 @@ r_save_mck3:
      b       r_ps
 
 r_save_mck4:
+     cmp     tmp1, #4
+     bne     r_save_mck5
      ldr     tmp2, .saved_mck4
+     b       r_ps
+
+r_save_mck5:
+     cmp     tmp1, #5
+     bne     r_save_mck6
+     ldr     tmp2, .saved_mck5
+     b       r_ps
+
+r_save_mck6:
+     cmp     tmp1, #6
+     bne     r_save_mck7
+     ldr     tmp2, .saved_mck6
+     b       r_ps
+
+r_save_mck7:
+     cmp     tmp1, #7
+     bne     r_save_mck8
+     ldr     tmp2, .saved_mck7
+     b       r_ps
+
+r_save_mck8:
+     cmp     tmp1, #8
+     bne     r_save_mck9
+     ldr     tmp2, .saved_mck8
+     b       r_ps
+
+r_save_mck9:
+     ldr     tmp2, .saved_mck9
 
 r_ps:
      /* Write MCK ID to retrieve the settings. */

arch/arm/mach-at91/pm_suspend.S r_ps: · line 988

Quoted 4 lines

arch/arm/mach-at91/pm_suspend.S +1 -0

@@ -921,6 +985,7 @@ r_ps:
      wait_mckrdy tmp1
 
      add     tmp1, tmp1, #1
+     ldr     tmp2, .mck_count

Or you can add tmp4 for this

Quoted 42 lines

arch/arm/mach-at91/pm_suspend.S +18 -0

      b       r_loop
 r_done:
 #endif

@@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
      str     tmp1, .memtype
      ldr     tmp1, [r0, #PM_DATA_MODE]
      str     tmp1, .pm_mode
+#ifdef CONFIG_SOC_SAMA7
+     ldr     tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
+     str     tmp1, .mck_count
+#endif
 
      /*
       * ldrne below are here to preload their address in the TLB as access

@@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
      .word 0
 .pmc_version:
      .word 0
+#ifdef CONFIG_SOC_SAMA7
+.mck_count:
+     .word 0
+#endif
 .saved_mckr:
      .word 0
 .saved_pllar:

@@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
      .word 0
 .saved_mck4:
      .word 0
+.saved_mck5:
+     .word 0
+.saved_mck6:
+     .word 0
+.saved_mck7:
+     .word 0
+.saved_mck8:
+     .word 0
+.saved_mck9:
+     .word 0
 #endif
 
 ENTRY(at91_pm_suspend_in_sram_sz)

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Hi, Ryan,

Quoted 96 lines · On 14.02.2025 20:09, [email protected] wrote:

Quoted 5 lines · Claudiu Beznea

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Hi, Ryan,

Quoted 8 lines

Quoted 4 lines · On 10.02.2025 23:13, [email protected] wrote:

From: Ryan Wanner <[email protected]>

New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a total of 10 main clocks that need to be saved for ULP0 mode.

Isn't 9 the total number of MCKs that are handled in the last/first phase of suspend/resume?

Yes I was including 10 to match the indexing in the mck_count variable. Since bgt instruction was suggested I will correct this to reflect the true behavior of the change.

Quoted 79 lines

Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.

Quoted 8 lines

Add mck_count member to at91_pm_data, this will be used to determine how many mcks need to be saved. In the mck_count member will also make sure that no unnecessary clock settings are written during mck_ps_restore.

Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low power modes.

Can you explain why this clear need to be done? The commit message should answer to the "what?" and "why?" questions.

Quoted 22 lines

Signed-off-by Ryan Wanner <[email protected]>

Acked-by Nicolas Ferre <[email protected]>

---
 arch/arm/mach-at91/pm.c              | 19 +++++-
 arch/arm/mach-at91/pm.h              |  1 +
 arch/arm/mach-at91/pm_data-offsets.c |  2 +
 arch/arm/mach-at91/pm_suspend.S      | 97 ++++++++++++++++++++++++++--
 4 files changed, 110 insertions(+), 9 deletions(-)

arch/arm/mach-at91/pm.c +1 -0

index 55cab31ce1ecb..50bada544eede 100644
@@ -1337,6 +1337,7 @@ struct pmc_info {
      unsigned long uhp_udp_mask;
      unsigned long mckr;
      unsigned long version;
+     unsigned long mck_count;>  };
 
 static const struct pmc_info pmc_infos[] __initconst = {

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1348

Quoted 4 lines

arch/arm/mach-at91/pm.c +1 -0

@@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
              .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,

As this member is used only for SAMA7 SoCs I would drop it here and above (where initialized with 1).

Quoted 19 lines

arch/arm/mach-at91/pm.c +3 -0

      },
 
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {       .uhp_udp_mask = 0,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1377

Quoted 10 lines

arch/arm/mach-at91/pm.c +2 -0

      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 1,
      },
      {
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 5,

I'm not sure mck_count is a good name when used like proposed in this patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for SAMA7D65.

Quoted 7 lines

Quoted 3 lines

Maybe, better change it here to 4 (.mck_count = 4) and to 9 above (.mck_count = 9) and adjust properly the assembly macros (see below)? What do you think?

Yes I think this is better and cleaner to read. Should this mck_count match the pmc_mck_count variable name? Or should this be more descriptive or would mcks be sufficient.

mck_count/mcks should be enough. These will be anyway in the context of pmc_info.

Quoted 39 lines

Quoted 39 lines

Quoted 28 lines

arch/arm/mach-at91/pm.c +8 -1

+     },
+     {
+             .uhp_udp_mask = AT91SAM926x_PMC_UHP,
+             .mckr = 0x28,
+             .version = AT91_PMC_V2,
+             .mck_count = 10,
      },
 
 };

@@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
      { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
      { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
      { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
-     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
+     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
      { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
      { /* sentinel */ },
 };

@@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
      soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
      soc_pm.data.pmc_mckr_offset = pmc->mckr;
      soc_pm.data.pmc_version = pmc->version;
+     soc_pm.data.pmc_mck_count = pmc->mck_count;
 
      if (pm_idle)
              arm_pm_idle = pm_idle;

arch/arm/mach-at91/pm.c void __init sama7_pm_init(void) · line 1677

Quoted 6 lines

arch/arm/mach-at91/pm.c +2 -1

@@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
              AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
      };
      static const u32 iomaps[] __initconst = {
-             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU),
+             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU) |
+                                       AT91_PM_IOMAP(SHDWC),

In theory, as the wakeup sources can also resumes the system from standby (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and the wakeup sources covered by the SHDWC_SR register don't apply to standby (WFI).

Quoted 4 lines

The device can wake up from an RTT or RTC alarm event on both the standby power mode and the ULP0 power mode, since the RTT/RTC are included in the SHDWC_SR I think it is safe to have this. If I understand what you are asking correctly.

I was asking if the SHDWC should also be mapped for standby like:

        static const u32 iomaps[] __initconst = {

                [AT91_PM_STANDBY]       = AT91_PM_IOMAP(SHDWC) |

                [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU) |

                                          AT91_PM_IOMAP(SHDWC),

                [AT91_PM_ULP1]          = AT91_PM_IOMAP(SFRBU) |

                                          AT91_PM_IOMAP(SHDWC) |

                                          AT91_PM_IOMAP(ETHC),

                [AT91_PM_BACKUP]        = AT91_PM_IOMAP(SFRBU) |

                                          AT91_PM_IOMAP(SHDWC),

        };

Quoted 227 lines

Quoted 226 lines

Quoted 41 lines

arch/arm/mach-at91/pm.c +0 -0

              [AT91_PM_ULP1]          = AT91_PM_IOMAP(SFRBU) |
                                        AT91_PM_IOMAP(SHDWC) |
                                        AT91_PM_IOMAP(ETHC),

arch/arm/mach-at91/pm.h +1 -0

index 53bdc9000e447..ccde9c8728c27 100644
@@ -39,6 +39,7 @@ struct at91_pm_data {
      unsigned int suspend_mode;
      unsigned int pmc_mckr_offset;
      unsigned int pmc_version;
+     unsigned int pmc_mck_count;
 };
 #endif
 

arch/arm/mach-at91/pm_data-offsets.c +2 -0

index 40bd4e8fe40a5..59a4838038381 100644
@@ -18,6 +18,8 @@ int main(void)
                                               pmc_mckr_offset));
      DEFINE(PM_DATA_PMC_VERSION,     offsetof(struct at91_pm_data,
                                               pmc_version));
+     DEFINE(PM_DATA_PMC_MCK_COUNT,   offsetof(struct at91_pm_data,
+                                              pmc_mck_count));
 
      return 0;
 }

arch/arm/mach-at91/pm_suspend.S +1 -1

index e5869cca5e791..2bbcbb26adb28 100644
@@ -814,17 +814,19 @@ sr_dis_exit:
 .endm
 
 /**
- * at91_mckx_ps_enable:      save MCK1..4 settings and switch it to main clock
+ * at91_mckx_ps_enable:      save MCK settings and switch it to main clock
  *

arch/arm/mach-at91/pm_suspend.S sr_dis_exit: · line 826

Quoted 10 lines

arch/arm/mach-at91/pm_suspend.S +3 -2

- * Side effects: overwrites tmp1, tmp2
+ * Side effects: overwrites tmp1, tmp2, tmp3
  */
 .macro at91_mckx_ps_enable
 #ifdef CONFIG_SOC_SAMA7
      ldr     pmc, .pmc_base
+     ldr     tmp3, .mck_count
 
-     /* There are 4 MCKs we need to handle: MCK1..4 */
+     /* Start at MCK1 and go until MCK_count */

s/MCK_count/mck_count to align with the mck_count above.

arch/arm/mach-at91/pm_suspend.S sr_dis_exit: · line 830

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +2 -1

      mov     tmp1, #1
-e_loop:      cmp     tmp1, #5
+e_loop:
+     cmp     tmp1, tmp3
      beq     e_done

If providing mck_count = 4 (for SAMA7G5) and mck_count = 9 (for SAMA7D65) you can change this to:

bqt e_done

Quoted 41 lines

arch/arm/mach-at91/pm_suspend.S +30 -0

      /* Write MCK ID to retrieve the settings. */

@@ -850,7 +852,37 @@ e_save_mck3:
      b       e_ps
 
 e_save_mck4:
+     cmp     tmp1, #4
+     bne     e_save_mck5
      str     tmp2, .saved_mck4
+     b       e_ps
+
+e_save_mck5:
+     cmp     tmp1, #5
+     bne     e_save_mck6
+     str     tmp2, .saved_mck5
+     b       e_ps
+
+e_save_mck6:
+     cmp     tmp1, #6
+     bne     e_save_mck7
+     str     tmp2, .saved_mck6
+     b       e_ps
+
+e_save_mck7:
+     cmp     tmp1, #7
+     bne     e_save_mck8
+     str     tmp2, .saved_mck7
+     b       e_ps
+
+e_save_mck8:
+     cmp     tmp1, #8
+     bne     e_save_mck9
+     str     tmp2, .saved_mck8
+     b       e_ps
+
+e_save_mck9:
+     str     tmp2, .saved_mck9
 
 e_ps:
      /* Use CSS=MAINCK and DIV=1. */

arch/arm/mach-at91/pm_suspend.S e_done: · line 905

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +1 -1

@@ -870,17 +902,19 @@ e_done:
 .endm
 
 /**
- * at91_mckx_ps_restore: restore MCK1..4 settings
+ * at91_mckx_ps_restore: restore MCKx settings

s/MCKx/MCK to align with the description from at91_mckx_ps_enable

Quoted 5 lines

arch/arm/mach-at91/pm_suspend.S +0 -0

  *
  * Side effects: overwrites tmp1, tmp2
  */
 .macro at91_mckx_ps_restore
 #ifdef CONFIG_SOC_SAMA7

arch/arm/mach-at91/pm_suspend.S e_done: · line 918

Quoted 10 lines

arch/arm/mach-at91/pm_suspend.S +4 -2

      ldr     pmc, .pmc_base
+     ldr     tmp2, .mck_count
 
-     /* There are 4 MCKs we need to handle: MCK1..4 */
+     /* Start from MCK1 and go up to MCK_count */
      mov     tmp1, #1
-r_loop:      cmp     tmp1, #5
+r_loop:
+     cmp     tmp1, tmp2
      beq     r_done

Same here:
bgt r_done

should be enough if providing mck_count = 4 or 9

Quoted 41 lines

arch/arm/mach-at91/pm_suspend.S +30 -0

 r_save_mck1:

@@ -902,7 +936,37 @@ r_save_mck3:
      b       r_ps
 
 r_save_mck4:
+     cmp     tmp1, #4
+     bne     r_save_mck5
      ldr     tmp2, .saved_mck4
+     b       r_ps
+
+r_save_mck5:
+     cmp     tmp1, #5
+     bne     r_save_mck6
+     ldr     tmp2, .saved_mck5
+     b       r_ps
+
+r_save_mck6:
+     cmp     tmp1, #6
+     bne     r_save_mck7
+     ldr     tmp2, .saved_mck6
+     b       r_ps
+
+r_save_mck7:
+     cmp     tmp1, #7
+     bne     r_save_mck8
+     ldr     tmp2, .saved_mck7
+     b       r_ps
+
+r_save_mck8:
+     cmp     tmp1, #8
+     bne     r_save_mck9
+     ldr     tmp2, .saved_mck8
+     b       r_ps
+
+r_save_mck9:
+     ldr     tmp2, .saved_mck9
 
 r_ps:
      /* Write MCK ID to retrieve the settings. */

arch/arm/mach-at91/pm_suspend.S r_ps: · line 988

Quoted 4 lines

arch/arm/mach-at91/pm_suspend.S +1 -0

@@ -921,6 +985,7 @@ r_ps:
      wait_mckrdy tmp1
 
      add     tmp1, tmp1, #1
+     ldr     tmp2, .mck_count

Or you can add tmp4 for this

Quoted 42 lines

arch/arm/mach-at91/pm_suspend.S +18 -0

      b       r_loop
 r_done:
 #endif

@@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram)
      str     tmp1, .memtype
      ldr     tmp1, [r0, #PM_DATA_MODE]
      str     tmp1, .pm_mode
+#ifdef CONFIG_SOC_SAMA7
+     ldr     tmp1, [r0, #PM_DATA_PMC_MCK_COUNT]
+     str     tmp1, .mck_count
+#endif
 
      /*
       * ldrne below are here to preload their address in the TLB as access

@@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram)
      .word 0
 .pmc_version:
      .word 0
+#ifdef CONFIG_SOC_SAMA7
+.mck_count:
+     .word 0
+#endif
 .saved_mckr:
      .word 0
 .saved_pllar:

@@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram)
      .word 0
 .saved_mck4:
      .word 0
+.saved_mck5:
+     .word 0
+.saved_mck6:
+     .word 0
+.saved_mck7:
+     .word 0
+.saved_mck8:
+     .word 0
+.saved_mck9:
+     .word 0
 #endif
 
 ENTRY(at91_pm_suspend_in_sram_sz)

Quoted 151 lines · Claudiu Beznea

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Hi, Ryan,

Quoted 96 lines · On 14.02.2025 20:09, [email protected] wrote:

Quoted 5 lines · Claudiu Beznea

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Hi, Ryan,

Quoted 8 lines

Quoted 4 lines · On 10.02.2025 23:13, [email protected] wrote:

From: Ryan Wanner <[email protected]>

New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a total of 10 main clocks that need to be saved for ULP0 mode.

Isn't 9 the total number of MCKs that are handled in the last/first phase of suspend/resume?

Yes I was including 10 to match the indexing in the mck_count variable. Since bgt instruction was suggested I will correct this to reflect the true behavior of the change.

Quoted 79 lines

Also, the state of MCKs are saved/restored for ULP0 and ULP1 as well.

Quoted 8 lines

Add mck_count member to at91_pm_data, this will be used to determine how many mcks need to be saved. In the mck_count member will also make sure that no unnecessary clock settings are written during mck_ps_restore.

Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low power modes.

Can you explain why this clear need to be done? The commit message should answer to the "what?" and "why?" questions.

Quoted 22 lines

Signed-off-by Ryan Wanner <[email protected]>

Acked-by Nicolas Ferre <[email protected]>

---
 arch/arm/mach-at91/pm.c              | 19 +++++-
 arch/arm/mach-at91/pm.h              |  1 +
 arch/arm/mach-at91/pm_data-offsets.c |  2 +
 arch/arm/mach-at91/pm_suspend.S      | 97 ++++++++++++++++++++++++++--
 4 files changed, 110 insertions(+), 9 deletions(-)

arch/arm/mach-at91/pm.c +1 -0

index 55cab31ce1ecb..50bada544eede 100644
@@ -1337,6 +1337,7 @@ struct pmc_info {
      unsigned long uhp_udp_mask;
      unsigned long mckr;
      unsigned long version;
+     unsigned long mck_count;>  };
 
 static const struct pmc_info pmc_infos[] __initconst = {

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1348

Quoted 4 lines

arch/arm/mach-at91/pm.c +1 -0

@@ -1344,30 +1345,42 @@ static const struct pmc_info pmc_infos[] __initconst = {
              .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,

As this member is used only for SAMA7 SoCs I would drop it here and above (where initialized with 1).

Quoted 19 lines

arch/arm/mach-at91/pm.c +3 -0

      },
 
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },
      {       .uhp_udp_mask = 0,
              .mckr = 0x30,
              .version = AT91_PMC_V1,
+             .mck_count = 1,
      },

arch/arm/mach-at91/pm.c static const struct pmc_info pmc_infos[] __initconst = { · line 1377

Quoted 10 lines

arch/arm/mach-at91/pm.c +2 -0

      {
              .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 1,
      },
      {
              .mckr = 0x28,
              .version = AT91_PMC_V2,
+             .mck_count = 5,

I'm not sure mck_count is a good name when used like proposed in this patch. We know that only 4 MCKs need to be handled for SAMA7G5 and 9 for SAMA7D65.

Quoted 7 lines

Quoted 3 lines

Maybe, better change it here to 4 (.mck_count = 4) and to 9 above (.mck_count = 9) and adjust properly the assembly macros (see below)? What do you think?

Yes I think this is better and cleaner to read. Should this mck_count match the pmc_mck_count variable name? Or should this be more descriptive or would mcks be sufficient.

mck_count/mcks should be enough. These will be anyway in the context of pmc_info.

Quoted 39 lines

Quoted 39 lines

Quoted 28 lines

arch/arm/mach-at91/pm.c +8 -1

+     },
+     {
+             .uhp_udp_mask = AT91SAM926x_PMC_UHP,
+             .mckr = 0x28,
+             .version = AT91_PMC_V2,
+             .mck_count = 10,
      },
 
 };

@@ -1386,7 +1399,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
      { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
      { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
      { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
-     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[4] },
+     { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] },
      { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
      { /* sentinel */ },
 };

@@ -1457,6 +1470,7 @@ static void __init at91_pm_init(void (*pm_idle)(void))
      soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
      soc_pm.data.pmc_mckr_offset = pmc->mckr;
      soc_pm.data.pmc_version = pmc->version;
+     soc_pm.data.pmc_mck_count = pmc->mck_count;
 
      if (pm_idle)
              arm_pm_idle = pm_idle;

arch/arm/mach-at91/pm.c void __init sama7_pm_init(void) · line 1677

Quoted 6 lines

arch/arm/mach-at91/pm.c +2 -1

@@ -1659,7 +1673,8 @@ void __init sama7_pm_init(void)
              AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
      };
      static const u32 iomaps[] __initconst = {
-             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU),
+             [AT91_PM_ULP0]          = AT91_PM_IOMAP(SFRBU) |
+                                       AT91_PM_IOMAP(SHDWC),

In theory, as the wakeup sources can also resumes the system from standby (WFI), the shdwc should be mapped for standby, too. Unless I'm wrong and the wakeup sources covered by the SHDWC_SR register don't apply to standby (WFI).

Quoted 6 lines

Quoted 4 lines

The device can wake up from an RTT or RTC alarm event on both the standby power mode and the ULP0 power mode, since the RTT/RTC are included in the SHDWC_SR I think it is safe to have this. If I understand what you are asking correctly.

I was asking if the SHDWC should also be mapped for standby like:

Ok I see. I have a better understanding now of wake up sources table like you showed below. I think for readability of code I should not have SHDWC set as ULP0 and STANDBY source because in at91_pm_config_ws() SHDWC is only configured as a wake up source in ULP1 power mode.

So removing SHDWC from the ULP0 wake up source would reflect more accurately what is configured as a wake up source in the code. What do you think?

From: Ryan Wanner <[email protected]>

Add sama7d65-pmc compatible string to the list of valid PMC IDs.

Signed-off-by Ryan Wanner <[email protected]>

---
 drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
 1 file changed, 1 insertion(+)

drivers/power/reset/at91-sama5d2_shdwc.c +0 -0

index edb0df86aff45..0cb7fe9f25a07 100644

drivers/power/reset/at91-sama5d2_shdwc.c +0 -0

 	{ /* Sentinel. */ }
 };
 

From: Ryan Wanner <[email protected]>

Add support for reset controller, wake up alarm timers, and shutdown controller.

Add SRAM, SFR, secumod, UDDRC, and DDR3phy to enable support for low power modes.

Signed-off-by Ryan Wanner <[email protected]>

---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++++++++++
 1 file changed, 77 insertions(+)

arch/arm/boot/dts/microchip/sama7d65.dtsi +0 -0

index 854b30d15dcd4..1d40235bdab0a 100644

arch/arm/boot/dts/microchip/sama7d65.dtsi +2 -0

+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
 		#address-cells = <1>;

arch/arm/boot/dts/microchip/sama7d65.dtsi +61 -0

+		};
+
+		secumod: secumod@e0004000 {
+			compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon";
+			reg = <0xe0004000 0x4000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		sfrbu: sfr@e0008000 {
+			compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
+			reg = <0xe0008000 0x20>;
+		};
+
 		pioa: pinctrl@e0014000 {
 			compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
 			reg = <0xe0014000 0x800>;

@@ -76,6 +106,31 @@ pmc: clock-controller@e0018000 {
 			clock-names = "td_slck", "md_slck", "main_xtal";
 		};
 
+		reset_controller: reset-controller@e001d100 {
+			compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc";
+			reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>;
+			#reset-cells = <1>;
+			clocks = <&clk32k 0>;
+		};
+
+		shdwc: poweroff@e001d200 {
+			compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon";
+			reg = <0xe001d200 0x20>;
+			clocks = <&clk32k 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			atmel,wakeup-rtc-timer;
+			atmel,wakeup-rtt-timer;
+			status = "disabled";
+		};
+
+		rtt: rtc@e001d300 {
+			compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+			reg = <0xe001d300 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 0>;
+		};
+
 		clk32k: clock-controller@e001d500 {
 			compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
 			reg = <0xe001d500 0x4>;

@@ -83,6 +138,18 @@ clk32k: clock-controller@e001d500 {
 			#clock-cells = <1>;
 		};
 
+		gpbr: gpbr@e001d700 {
+			compatible = "microchip,sama7d65-gpbr", "syscon";
+			reg = <0xe001d700 0x48>;
+		};
+
+		rtc: rtc@e001d800 {
+			compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc";
+			reg = <0xe001d800 0x30>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 1>;
+		};
+
 		sdmmc1: mmc@e1208000 {
 			compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
 			reg = <0xe1208000 0x400>;

@@ -132,6 +199,16 @@ uart6: serial@200 {
 			};
 		};
 
+		uddrc: uddrc@e3800000 {
+			compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
+			reg = <0xe3800000 0x4000>;
+		};
+
+		ddr3phy: ddr3phy@e3804000 {
+			compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
+			reg = <0xe3804000 0x1000>;
+		};
+
 		gic: interrupt-controller@e8c11000 {
 			compatible = "arm,cortex-a7-gic";
 			reg = <0xe8c11000 0x1000>,

From: Ryan Wanner <[email protected]>

Add shutdown controller and rtt timer to support shutdown and wake up.

Signed-off-by Ryan Wanner <[email protected]>

---
 .../boot/dts/microchip/at91-sama7d65_curiosity.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +0 -0

index 0f86360fb733a..d1d0b06fbfc43 100644

arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +11 -0

+};
+
 &sdmmc1 {
 	bus-width = <4>;
 	pinctrl-names = "default";

@@ -84,6 +89,15 @@ &sdmmc1 {
 	status = "okay";
 };
 
+&shdwc {
+	debounce-delay-us = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
 &slow_xtal {
 	clock-frequency = <32768>;
 };