Enable Power Modes Support for SAMA7D65 SoC

From: Ryan Wanner <[email protected]>

This patch set adds support for low power modes for the SAMA7D65 SoC and the required components and changes for low power modes.

The series includes changes in the asm code to account for the addtional clocks that are in this SoC.

The Device tree additions are to enable all the components needed to keep the SoC in low power mode.

There are some DTB check warnings but that is due to the dt-binding not in the correct .yaml file format.

Changes v1 -> v2:
- Add missing compatible for ddr3phy, it is now in both syscon sets.
- Fix alphabetical ordering for sama7d65.
- Remove the incorrect reorganizing patch.
- Remove sama7g5-rtt as a compatible for sama7d65-rtt and add sama7d65-rtt as a compatible wake up source in the pm driver.

Changes from v2 -> v3:
- Correct mistake in v2 sfrbu dt-binding patch.
- Correct incorrect dt-binding addition and formatting for rtc and rtt bindings.
- Add missing SoB tag.
- Cleaned up commit message for Backup mode to describe SHDWC is status register is cleared for this SoC.
- Cleaned up variable naming and usage for mcks. Changed the mcks number to the correct number of clocks needed to be saved and corrected the ASM code accordingly.
- Removed the SHDWC from ULP0 wake-up source as it is not configured as a valid wake-up source for ULP0.
- Separated all the DTSI and DTS changes into individual patches.

Changes from v3 -> v4:
- Add sama7d65-gpbr to the dt-binding.
- Converted the sama5d2-secumod binding into yaml format.
- Add sama7d65-secumod to the new dt binding.
- Collect and remove applied and accpeted pathces from the set.

Changes from v4 -> v5:
- Use generic naming for dt-binding yaml example.
- Adjust DTSI SECUMOD node to match generic naming.
- Collect Acked and Reviewed tags.

v1) https://lore.kernel.org/linux-arm-kernel/[email protected]/
v2) https://lore.kernel.org/linux-arm-kernel/[email protected]/
v3) https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#m576233e7af84d68559afb286884c2b9294e7bc1d
v4) https://lore.kernel.org/linux-arm-kernel/[email protected]/

Ryan Wanner (11):
dt-bindings: sram: Add microchip,sama7d65-sram
dt-bindings: power: reset: atmel,sama5d2-shdwc: Add
microchip,sama7d65-shdwc
dt-bindings: reset: atmel,at91sam9260-reset: add
microchip,sama7d65-rstc
dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
dt-bindings: mfd: atmel: Add microchip,sama7d65-gpbr
dt-bindings: mfd: syscon: atmel,sama5d2-secumod: convert to yaml
dt-bindings: mfd: syscon: add microchip,sama7d65-secumod
ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support
ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65
SoC
ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board

 .../bindings/arm/atmel,sama5d2-secumod.yaml   | 49 +++++++++++++++++++
 .../devicetree/bindings/arm/atmel-sysregs.txt | 25 ----------
 .../bindings/mfd/atmel,at91sam9260-gpbr.yaml  |  1 +
 .../power/reset/atmel,sama5d2-shdwc.yaml      |  5 ++
 .../reset/atmel,at91sam9260-reset.yaml        |  3 ++
 .../bindings/rtc/atmel,at91rm9200-rtc.yaml    |  4 +-
 .../bindings/rtc/atmel,at91sam9260-rtt.yaml   |  1 +
 .../devicetree/bindings/sram/sram.yaml        |  1 +
 .../dts/microchip/at91-sama7d65_curiosity.dts |  4 ++
 arch/arm/boot/dts/microchip/sama7d65.dtsi     | 47 ++++++++++++++++++
 10 files changed, 114 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml

2.43.0

From: Ryan Wanner <[email protected]>

Add microchip,sama7d65-sram compatibility to DT binding documentation.

---
 Documentation/devicetree/bindings/sram/sram.yaml | 1 +
 1 file changed, 1 insertion(+)

index 7c1337e159f2..3071c5075ee4 100644
@@ -31,6 +31,7 @@ properties:
         - amlogic,meson-gxbb-sram
         - arm,juno-sram-ns
         - atmel,sama5d2-securam
+        - microchip,sama7d65-securam
         - nvidia,tegra186-sysram
         - nvidia,tegra194-sysram
         - nvidia,tegra234-sysram

2.43.0

From: Ryan Wanner <[email protected]>

Add SAMA7D65 SHDWC compatible to DT bindings documentation

---
 .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 5 +++++
 1 file changed, 5 insertions(+)

index 0735ceb7c103..9c34249b2d6d 100644
@@ -16,6 +16,11 @@ description: |
 properties:
   compatible:
     oneOf:
+      - items:
+          - enum:
+              - microchip,sama7d65-shdwc
+          - const: microchip,sama7g5-shdwc
+          - const: syscon
       - items:
           - const: microchip,sama7g5-shdwc
           - const: syscon

2.43.0

You are sending patches which are already applied.

Best regards,
Krzysztof

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RSTC compatible to DT bindings documentation. The sama7d65-rstc is compatible with the sama7g5-rstc.

---
 .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml     | 3 +++
 1 file changed, 3 insertions(+)

index 98465d26949e..a2ab7f8a11f8 100644
@@ -23,6 +23,9 @@ properties:
               - atmel,sama5d3-rstc
               - microchip,sam9x60-rstc
               - microchip,sama7g5-rstc
+      - items:
+          - const: microchip,sama7d65-rstc
+          - const: microchip,sama7g5-rstc
       - items:
           - const: atmel,sama5d3-rstc
           - const: atmel,at91sam9g45-rstc

2.43.0

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTC compatible to DT bindings documentation.

---
 .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml         | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

index c8bb2eef442d..7c5b13caa40b 100644
@@ -23,7 +23,9 @@ properties:
           - microchip,sam9x60-rtc
           - microchip,sama7g5-rtc
       - items:
-          - const: microchip,sam9x7-rtc
+          - enum:
+              - microchip,sam9x7-rtc
+              - microchip,sama7d65-rtc
           - const: microchip,sam9x60-rtc
 
   reg:

2.43.0

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTT compatible to DT bindings documentation.

---
 Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 1 +
 1 file changed, 1 insertion(+)

index a7f6c1d1a08a..9c9b981fe38b 100644
@@ -22,6 +22,7 @@ properties:
           - enum:
               - microchip,sam9x60-rtt
               - microchip,sam9x7-rtt
+              - microchip,sama7d65-rtt
           - const: atmel,at91sam9260-rtt
       - items:
           - const: microchip,sama7g5-rtt

2.43.0

From: Ryan Wanner <[email protected]>

Add SAMA7D65 GPBR compatible to DT bindings documentation.

---
 .../devicetree/bindings/mfd/atmel,at91sam9260-gpbr.yaml          | 1 +
 1 file changed, 1 insertion(+)

index f805545aa62a..f6f47999c6c1 100644
@@ -19,6 +19,7 @@ properties:
       - items:
           - enum:
               - atmel,at91sam9260-gpbr
+              - microchip,sama7d65-gpbr
           - const: syscon
       - items:
           - enum:

2.43.0

From: Ryan Wanner <[email protected]>

Convert Microchip AT91 secumod to YAML format.

---
 .../bindings/arm/atmel,sama5d2-secumod.yaml   | 48 +++++++++++++++++++
 .../devicetree/bindings/arm/atmel-sysregs.txt | 25 ----------
 2 files changed, 48 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml

new file mode 100644
index 000000000000..b1f766e333d4
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 Security Module (SECUMOD)
+
+maintainers:
+  - Nicolas Ferre <[email protected]>
+
+description:
+  The Security Module also offers the PIOBU pins which can be used as GPIO pins.
+  Note that they maintain their voltage during Backup/Self-refresh.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: atmel,sama5d2-secumod
+          - const: syscon
+      - items:
+          - enum:
+              - microchip,sama7g5-secumod
+          - const: atmel,sama5d2-secumod
+          - const: syscon
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    security-module@fc040000 {
+      compatible = "atmel,sama5d2-secumod", "syscon";
+      reg = <0xfc040000 0x100>;
+      gpio-controller;
+      #gpio-cells = <2>;
+    };

index d3821f651e72..5ce54f9befe6 100644
@@ -46,28 +46,3 @@ Examples:
 		reg = <0xffffe800 0x200>;
 	};
 
-Security Module (SECUMOD)
-
-The Security Module macrocell provides all necessary secure functions to avoid
-voltage, temperature, frequency and mechanical attacks on the chip. It also
-embeds secure memories that can be scrambled.
-
-The Security Module also offers the PIOBU pins which can be used as GPIO pins.
-Note that they maintain their voltage during Backup/Self-refresh.
-
-required properties:
-- compatible: Should be "atmel,<chip>-secumod", "syscon".
-  <chip> can be "sama5d2".
-- reg: Should contain registers location and length
-- gpio-controller:	Marks the port as GPIO controller.
-- #gpio-cells:		There are 2. The pin number is the
-			first, the second represents additional
-			parameters such as GPIO_ACTIVE_HIGH/LOW.
-
-
-	secumod@fc040000 {
-		compatible = "atmel,sama5d2-secumod", "syscon";
-		reg = <0xfc040000 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};

2.43.0

From: Ryan Wanner <[email protected]>

Add SAMA7D65 SECUMOD compatible string to DT bindings documentation.

---
 Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml | 1 +
 1 file changed, 1 insertion(+)

index b1f766e333d4..ad4a98a4ee67 100644
@@ -21,6 +21,7 @@ properties:
           - const: syscon
       - items:
           - enum:
+              - microchip,sama7d65-secumod
               - microchip,sama7g5-secumod
           - const: atmel,sama5d2-secumod
           - const: syscon

2.43.0

From: Ryan Wanner <[email protected]>

Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes.

---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 35 +++++++++++++++++++++++
 1 file changed, 35 insertions(+)

index b6710ccd4c36..8439c6a9e9f2 100644
@@ -47,6 +47,14 @@ slow_xtal: clock-slowxtal {
 		};
 	};
 
+	ns_sram: sram@100000 {
+		compatible = "mmio-sram";
+		reg = <0x100000 0x20000>;
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;

@@ -58,6 +66,23 @@ sfrbu: sfr@e0008000 {
 			reg = <0xe0008000 0x20>;
 		};
 
+		securam: sram@e0000800 {
+			compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram";
+			reg = <0xe0000800 0x4000>;
+			ranges = <0 0xe0000800 0x4000>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			no-memory-wc;
+		};
+
+		secumod: security-module@e0004000 {
+			compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon";
+			reg = <0xe0004000 0x4000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
 		pioa: pinctrl@e0014000 {
 			compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
 			reg = <0xe0014000 0x800>;

@@ -227,6 +252,16 @@ i2c10: i2c@600 {
 			};
 		};
 
+		uddrc: uddrc@e3800000 {
+			compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
+			reg = <0xe3800000 0x4000>;
+		};
+
+		ddr3phy: ddr3phy@e3804000 {
+			compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
+			reg = <0xe3804000 0x1000>;
+		};
+
 		gic: interrupt-controller@e8c11000 {
 			compatible = "arm,cortex-a7-gic";
 			reg = <0xe8c11000 0x1000>,

2.43.0

Hi, Ryan,

From: Ryan Wanner <[email protected]>

Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data.

---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

index 8439c6a9e9f2..bec70164a75c 100644
@@ -132,6 +132,13 @@ shdwc: poweroff@e001d200 {
 			status = "disabled";
 		};
 
+		rtt: rtc@e001d300 {
+			compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+			reg = <0xe001d300 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 0>;
+		};
+
 		clk32k: clock-controller@e001d500 {
 			compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
 			reg = <0xe001d500 0x4>;

@@ -146,6 +153,11 @@ rtc: rtc@e001d800 {
 			clocks = <&clk32k 1>;
 		};
 
+		gpbr: syscon@e001d700 {
+			compatible = "microchip,sama7d65-gpbr", "syscon";
+			reg = <0xe001d700 0x48>;
+		};
+
 		chipid@e0020000 {
 			compatible = "microchip,sama7d65-chipid";
 			reg = <0xe0020000 0x8>;

2.43.0

Hi, Ryan,

From: Ryan Wanner <[email protected]>

Add RTT timer with backup register for SAMA7D65_Curiosity board.

---
 arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts | 4 ++++
 1 file changed, 4 insertions(+)

index 30fdc4f55a3b..3105fe1766c3 100644
@@ -141,6 +141,10 @@ pinctrl_uart6_default: uart6-default {
 	};
 };
 
+&rtt {
+	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+};
+
 &sdmmc1 {
 	bus-width = <4>;
 	pinctrl-names = "default";

2.43.0

My bot found new DTB warnings on the .dts files added or changed in this series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date:

  pip3 install dtschema --upgrade

This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: tags/v6.15-rc1-45-g43e9076a00b1 (best guess, 7/9 blobs matched)

If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/microchip/' for [email protected]:

arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/uddrc@e3800000: failed to match any schema with compatible: ['microchip,sama7d65-uddrc', 'microchip,sama7g5-uddrc'] arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: /soc/uddrc@e3800000: failed to match any schema with compatible: ['microchip,sama7d65-uddrc', 'microchip,sama7g5-uddrc'] arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: ddr3phy@e3804000 (microchip,sama7d65-ddr3phy): compatible: ['microchip,sama7d65-ddr3phy', 'microchip,sama7g5-ddr3phy'] does not contain items matching the given schema
from schema $id: http://devicetree.org/schemas/mfd/syscon.yaml#
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: ddr3phy@e3804000 (microchip,sama7d65-ddr3phy): compatible:1: 'syscon' was expected
from schema $id: http://devicetree.org/schemas/mfd/syscon.yaml#
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dtb: ddr3phy@e3804000 (microchip,sama7d65-ddr3phy): Unevaluated properties are not allowed ('compatible' was unexpected)
from schema $id: http://devicetree.org/schemas/mfd/syscon.yaml#

Applied, thanks!

[06/11] dt-bindings: mfd: atmel: Add microchip,sama7d65-gpbr

        commit: cf616eb55ba84118d0f8274a3e78dd526ef235a4
[07/11] dt-bindings: mfd: syscon: atmel,sama5d2-secumod: convert to yaml
        commit: da4151479628b170074dadcdcdbb1c042643bd3b
[08/11] dt-bindings: mfd: syscon: add microchip,sama7d65-secumod
        commit: d0eceba4d13341a1d2d52a1ffc31b6987174dfd0

--
Lee Jones [李琼斯]

Applied to at91-dt, thanks!

Applied, thanks!

[03/11] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc

        commit: 4e55fb7d60e128fb5a57921cbd59f9ff29cd4297

Best regards,

Sebastian Reichel <[email protected]>

Applied, thanks!

[04/11] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc

        https://git.kernel.org/abelloni/c/0a68f5be7883
[05/11] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
        https://git.kernel.org/abelloni/c/bf1c27c6d540

Best regards,

Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com