Add support for mt8167 display blocks
Subsystems (7)
v3 cover Add support for mt8167 display blocks
This series adds support for the display blocks on MediaTek mt8167. Tested on Xiaomi Mi Smart Clock x04g.
The first patch just does some reordering of dts nodes with no other changes as this makes later patches cleaner and easier to follow.
v3:
- Added mt8167-dsi compatible to driver instead of changing the binding;
- Resolved patch formatting issues.
v2:
- Separate patch for mediatek,dsi-phy binding;
- Separate patch for mt8167-dsi binding;
- Simplified OF graph endpoints in mt8167.dtsi.
Luca Leonardo Scorcia (5):
arm64: dts: mt8167: Reorder nodes according to mmio address
dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
arm64: dts: mediatek: mt8167: Add DRM nodes drm/mediatek: dsi: Add compatible for mt8167-dsi
Val Packett (1):
gpu: drm: mediatek: ovl: add specific entry for mt8167
.../display/mediatek/mediatek,aal.yaml | 1 + .../display/mediatek/mediatek,ccorr.yaml | 4 +- .../display/mediatek/mediatek,dither.yaml | 1 + .../display/mediatek/mediatek,gamma.yaml | 1 + .../display/mediatek/mediatek,ovl.yaml | 1 + .../display/mediatek/mediatek,rdma.yaml | 1 + .../display/mediatek/mediatek,wdma.yaml | 4 +- .../bindings/phy/mediatek,dsi-phy.yaml | 1 + arch/arm64/boot/dts/mediatek/mt8167.dtsi | 381 ++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 + drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 11 files changed, 374 insertions(+), 34 deletions(-)
Signature · 1 line
2.43.0
PATCH v3 1/6 arm64: dts: mt8167: Reorder nodes according to mmio address
In preparation for adding display nodes. No other changes.
--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++------------ 1 file changed, 34 insertions(+), 34 deletions(-)
arch/arm64/boot/dts/mediatek/mt8167.dtsi +34 -34
@@ -29,12 +29,6 @@ infracfg: infracfg@10001000 { #clock-cells = <1>; }; - apmixedsys: apmixedsys@10018000 { - compatible = "mediatek,mt8167-apmixedsys", "syscon"; - reg = <0 0x10018000 0 0x710>; - #clock-cells = <1>; - }; - scpsys: syscon@10006000 { compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>;
@@ -101,18 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN { }; }; - imgsys: syscon@15000000 { - compatible = "mediatek,mt8167-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt8167-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - pio: pinctrl@1000b000 { compatible = "mediatek,mt8167-pinctrl"; reg = <0 0x1000b000 0 0x1000>;
@@ -124,12 +106,36 @@ pio: pinctrl@1000b000 { interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; }; + apmixedsys: apmixedsys@10018000 { + compatible = "mediatek,mt8167-apmixedsys", "syscon"; + reg = <0 0x10018000 0 0x710>; + #clock-cells = <1>; + }; + + iommu: m4u@10203000 { + compatible = "mediatek,mt8167-m4u"; + reg = <0 0x10203000 0 0x1000>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; + #iommu-cells = <1>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; + larb0: larb@14016000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x14016000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + smi_common: smi@14017000 { compatible = "mediatek,mt8167-smi-common"; reg = <0 0x14017000 0 0x1000>;
@@ -139,14 +145,10 @@ smi_common: smi@14017000 { power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; - larb0: larb@14016000 { - compatible = "mediatek,mt8167-smi-larb"; - reg = <0 0x14016000 0 0x1000>; - mediatek,smi = <&smi_common>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + imgsys: syscon@15000000 { + compatible = "mediatek,mt8167-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; }; larb1: larb@15001000 {
@@ -159,6 +161,12 @@ larb1: larb@15001000 { power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; }; + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8167-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + larb2: larb@16010000 { compatible = "mediatek,mt8167-smi-larb"; reg = <0 0x16010000 0 0x1000>;
@@ -168,13 +176,5 @@ larb2: larb@16010000 { clock-names = "apb", "smi"; power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; }; - - iommu: m4u@10203000 { - compatible = "mediatek,mt8167-m4u"; - reg = <0 0x10203000 0 0x1000>; - mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; - #iommu-cells = <1>; - }; }; };
Signature · 1 line
2.43.0
PATCH v3 2/6 dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
In reply to Luca Leonardo ScorciaAdd compatibles for various display-related blocks of MediaTek mt8167.
--- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml | 4 +++- 7 files changed, 11 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +1 -0
@@ -33,6 +33,7 @@ properties: - enum: - mediatek,mt2712-disp-aal - mediatek,mt6795-disp-aal + - mediatek,mt8167-disp-aal - const: mediatek,mt8173-disp-aal - items: - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +3 -1
@@ -25,7 +25,9 @@ properties: - mediatek,mt8183-disp-ccorr - mediatek,mt8192-disp-ccorr - items: - - const: mediatek,mt8365-disp-ccorr + - enum: + - mediatek,mt8167-disp-ccorr + - mediatek,mt8365-disp-ccorr - const: mediatek,mt8183-disp-ccorr - items: - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +1 -0
@@ -26,6 +26,7 @@ properties: - mediatek,mt8183-disp-dither - items: - enum: + - mediatek,mt8167-disp-dither - mediatek,mt8186-disp-dither - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +1 -0
@@ -28,6 +28,7 @@ properties: - items: - enum: - mediatek,mt6795-disp-gamma + - mediatek,mt8167-disp-gamma - const: mediatek,mt8173-disp-gamma - items: - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +1 -0
@@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt2701-disp-ovl + - mediatek,mt8167-disp-ovl - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +1 -0
@@ -36,6 +36,7 @@ properties: - enum: - mediatek,mt7623-disp-rdma - mediatek,mt2712-disp-rdma + - mediatek,mt8167-disp-rdma - const: mediatek,mt2701-disp-rdma - items: - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +3 -1
@@ -24,7 +24,9 @@ properties: - enum: - mediatek,mt8173-disp-wdma - items: - - const: mediatek,mt6795-disp-wdma + - enum: + - mediatek,mt6795-disp-wdma + - mediatek,mt8167-disp-wdma - const: mediatek,mt8173-disp-wdma reg:
Signature · 1 line
2.43.0
Re: [PATCH v3 2/6] dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
Quoted 4 lines · Luca Leonardo Scorcia
External email : Please do not click links or open attachments until you have verified the sender or the content.
Add compatibles for various display-related blocks of MediaTek mt8167.
Quoted 108 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>Reviewed-by Krzysztof Kozlowski <[email protected]>Reviewed-by AngeloGioacchino Del Regno <[email protected]>--- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml | 4 +++- 7 files changed, 11 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +1
-0@@ -33,6 +33,7 @@ properties: - enum: - mediatek,mt2712-disp-aal - mediatek,mt6795-disp-aal + - mediatek,mt8167-disp-aal - const: mediatek,mt8173-disp-aal - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +3
-1@@ -25,7 +25,9 @@ properties: - mediatek,mt8183-disp-ccorr - mediatek,mt8192-disp-ccorr - items: - - const: mediatek,mt8365-disp-ccorr + - enum: + - mediatek,mt8167-disp-ccorr + - mediatek,mt8365-disp-ccorr - const: mediatek,mt8183-disp-ccorr - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +1
-0@@ -26,6 +26,7 @@ properties: - mediatek,mt8183-disp-dither - items: - enum: + - mediatek,mt8167-disp-dither - mediatek,mt8186-disp-dither - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-ditherDocumentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +1
-0@@ -28,6 +28,7 @@ properties: - items: - enum: - mediatek,mt6795-disp-gamma + - mediatek,mt8167-disp-gamma - const: mediatek,mt8173-disp-gamma - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +1
-0@@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt2701-disp-ovl + - mediatek,mt8167-disp-ovl - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovlDocumentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +1
-0@@ -36,6 +36,7 @@ properties: - enum: - mediatek,mt7623-disp-rdma - mediatek,mt2712-disp-rdma + - mediatek,mt8167-disp-rdma - const: mediatek,mt2701-disp-rdma - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +3
-2@@ -24,7 +24,9 @@ properties: - enum: - mediatek,mt8173-disp-wdma - items: - - const: mediatek,mt6795-disp-wdma + - enum: + - mediatek,mt6795-disp-wdma + - mediatek,mt8167-disp-wdma - const: mediatek,mt8173-disp-wdma reg: --2.43.0
Re: [PATCH v3 2/6] dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
In reply to Luca Leonardo ScorciaHi, Luca:
Luca Leonardo Scorcia <[email protected]> 於 2026年2月23日週一 下午4:26寫道：
Quoted 2 lines
Add compatibles for various display-related blocks of MediaTek mt8167.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
Quoted 107 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>Reviewed-by Krzysztof Kozlowski <[email protected]>Reviewed-by AngeloGioacchino Del Regno <[email protected]>--- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++- .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml | 4 +++- 7 files changed, 11 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +1
-0@@ -33,6 +33,7 @@ properties: - enum: - mediatek,mt2712-disp-aal - mediatek,mt6795-disp-aal + - mediatek,mt8167-disp-aal - const: mediatek,mt8173-disp-aal - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +3
-1@@ -25,7 +25,9 @@ properties: - mediatek,mt8183-disp-ccorr - mediatek,mt8192-disp-ccorr - items: - - const: mediatek,mt8365-disp-ccorr + - enum: + - mediatek,mt8167-disp-ccorr + - mediatek,mt8365-disp-ccorr - const: mediatek,mt8183-disp-ccorr - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +1
-0@@ -26,6 +26,7 @@ properties: - mediatek,mt8183-disp-dither - items: - enum: + - mediatek,mt8167-disp-dither - mediatek,mt8186-disp-dither - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-ditherDocumentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +1
-0@@ -28,6 +28,7 @@ properties: - items: - enum: - mediatek,mt6795-disp-gamma + - mediatek,mt8167-disp-gamma - const: mediatek,mt8173-disp-gamma - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +1
-0@@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt2701-disp-ovl + - mediatek,mt8167-disp-ovl - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovlDocumentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +1
-0@@ -36,6 +36,7 @@ properties: - enum: - mediatek,mt7623-disp-rdma - mediatek,mt2712-disp-rdma + - mediatek,mt8167-disp-rdma - const: mediatek,mt2701-disp-rdma - items: - enum:Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +3
-2@@ -24,7 +24,9 @@ properties: - enum: - mediatek,mt8173-disp-wdma - items: - - const: mediatek,mt6795-disp-wdma + - enum: + - mediatek,mt6795-disp-wdma + - mediatek,mt8167-disp-wdma - const: mediatek,mt8173-disp-wdma reg: --2.43.0
PATCH v3 3/6 dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
In reply to Luca Leonardo ScorciaAdd support for the MediaTek mt8167 SoC: the DSI PHY found in this chip is fully compatible with the one found in the mt2701 SoC.
--- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +1 -0
@@ -23,6 +23,7 @@ properties: - items: - enum: - mediatek,mt7623-mipi-tx + - mediatek,mt8167-mipi-tx - const: mediatek,mt2701-mipi-tx - items: - enum:
Signature · 1 line
2.43.0
Re: [PATCH v3 3/6] dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
Quoted 5 lines · Luca Leonardo Scorcia
External email : Please do not click links or open attachments until you have verified the sender or the content.
Add support for the MediaTek mt8167 SoC: the DSI PHY found in this chip is fully compatible with the one found in the mt2701 SoC.
Quoted 24 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>Reviewed-by AngeloGioacchino Del Regno <[email protected]>--- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +1
-1@@ -23,6 +23,7 @@ properties: - items: - enum: - mediatek,mt7623-mipi-tx + - mediatek,mt8167-mipi-tx - const: mediatek,mt2701-mipi-tx - items: - enum: --2.43.0
Re: [PATCH v3 3/6] dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
In reply to Luca Leonardo ScorciaHi, Luca:
Luca Leonardo Scorcia <[email protected]> 於 2026年2月23日週一 下午4:26寫道：
Quoted 3 lines
Add support for the MediaTek mt8167 SoC: the DSI PHY found in this chip is fully compatible with the one found in the mt2701 SoC.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
Quoted 23 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>Reviewed-by AngeloGioacchino Del Regno <[email protected]>--- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +1
-1@@ -23,6 +23,7 @@ properties: - items: - enum: - mediatek,mt7623-mipi-tx + - mediatek,mt8167-mipi-tx - const: mediatek,mt2701-mipi-tx - items: - enum: --2.43.0
PATCH v3 4/6 arm64: dts: mediatek: mt8167: Add DRM nodes
In reply to Luca Leonardo ScorciaAdd all the DRM nodes required to get DSI to work on MT8167 SoC.
--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 317 +++++++++++++++++++++++ 1 file changed, 317 insertions(+)
arch/arm64/boot/dts/mediatek/mt8167.dtsi +317 -0
@@ -16,6 +16,20 @@ / { compatible = "mediatek,mt8167"; + aliases { + aal0 = &aal; + ccorr0 = &ccorr; + color0 = &color; + dither0 = &dither; + dsi0 = &dsi; + gamma0 = γ + ovl0 = &ovl0; + pwm0 = &disp_pwm; + rdma0 = &rdma0; + rdma1 = &rdma1; + wdma0 = &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible = "mediatek,mt8167-topckgen", "syscon";
@@ -120,10 +134,303 @@ iommu: m4u@10203000 { #iommu-cells = <1>; }; + disp_pwm: pwm@1100f000 { + compatible = "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_PWM_26M>, <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names = "main", "mm"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + status = "disabled"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; #clock-cells = <1>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; + }; + + ovl0: ovl0@14007000 { + compatible = "mediatek,mt8167-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&color_in>; + }; + }; + }; + }; + + rdma0: rdma0@14009000 { + compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg = <0 0x14009000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&dither_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + + rdma1: rdma1@1400a000 { + compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma"; + reg = <0 0x1400a000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { }; + }; + }; + }; + + wdma: wdma0@1400b000 { + compatible = "mediatek,mt8167-disp-wdma", "mediatek,mt8173-disp-wdma"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + color: color@1400c000 { + compatible = "mediatek,mt8167-disp-color"; + reg = <0 0x1400c000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + color_out: endpoint { + remote-endpoint = <&ccorr_in>; + }; + }; + }; + }; + + ccorr: ccorr@1400d000 { + compatible = "mediatek,mt8167-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_CCORR>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr_in: endpoint { + remote-endpoint = <&color_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr_out: endpoint { + remote-endpoint = <&aal_in>; + }; + }; + }; + }; + + aal: aal@1400e000 { + compatible = "mediatek,mt8167-disp-aal", "mediatek,mt8173-disp-aal"; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal_in: endpoint { + remote-endpoint = <&ccorr_out>; + }; + }; + + port@1 { + reg = <1>; + aal_out: endpoint { + remote-endpoint = <&gamma_in>; + }; + }; + }; + }; + + gamma: gamma@1400f000 { + compatible = "mediatek,mt8167-disp-gamma", "mediatek,mt8173-disp-gamma"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma_in: endpoint { + remote-endpoint = <&aal_out>; + }; + }; + + port@1 { + reg = <1>; + gamma_out: endpoint { + remote-endpoint = <&dither_in>; + }; + }; + }; + }; + + dither: dither@14010000 { + compatible = "mediatek,mt8167-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_DITHER>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither_in: endpoint { + remote-endpoint = <&gamma_out>; + }; + }; + + port@1 { + reg = <1>; + dither_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + dsi: dsi@14012000 { + compatible = "mediatek,mt8167-dsi"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names = "engine", "digital", "hs"; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>; + phys = <&mipi_tx>; + phy-names = "dphy"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { }; + }; + }; + }; + + mutex: mutex@14015000 { + compatible = "mediatek,mt8167-disp-mutex"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; larb0: larb@14016000 {
@@ -145,6 +452,16 @@ smi_common: smi@14017000 { power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; + mipi_tx: dsi-phy@14018000 { + compatible = "mediatek,mt8167-mipi-tx", "mediatek,mt2701-mipi-tx"; + reg = <0 0x14018000 0 0x90>; + clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8167-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>;
Signature · 1 line
2.43.0
PATCH v3 5/6 drm/mediatek: dsi: Add compatible for mt8167-dsi
In reply to Luca Leonardo ScorciaThe mt8167 DSI controller is fully compatible with the one found in mt2701. Device tree documentation is already present upstream.
--- drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 1 file changed, 1 insertion(+)
drivers/gpu/drm/mediatek/mtk_dsi.c +1 -0
@@ -1301,6 +1301,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {static const struct of_device_id mtk_dsi_of_match[] = { { .compatible ="mediatek,mt2701-dsi" , .data = &mt2701_dsi_driver_data }, + { .compatible ="mediatek,mt8167-dsi" , .data = &mt2701_dsi_driver_data }, { .compatible ="mediatek,mt8173-dsi" , .data = &mt8173_dsi_driver_data }, { .compatible ="mediatek,mt8183-dsi" , .data = &mt8183_dsi_driver_data }, { .compatible ="mediatek,mt8186-dsi" , .data = &mt8186_dsi_driver_data },
Signature · 1 line
2.43.0
Re: [PATCH v3 5/6] drm/mediatek: dsi: Add compatible for mt8167-dsi
Il 23/02/26 17:22, Luca Leonardo Scorcia ha scritto:
Quoted 4 lines
The mt8167 DSI controller is fully compatible with the one found in mt2701. Device tree documentation is already present upstream.
Signed-off-by Luca Leonardo Scorcia <[email protected]>
Re: [PATCH v3 5/6] drm/mediatek: dsi: Add compatible for mt8167-dsi
In reply to Luca Leonardo ScorciaQuoted 5 lines · Luca Leonardo Scorcia
External email : Please do not click links or open attachments until you have verified the sender or the content.
The mt8167 DSI controller is fully compatible with the one found in mt2701. Device tree documentation is already present upstream.
If mt8167 DSI is fully compatible with mt2701 DSI, I think the binding document and device tree should be modified. In device tree,
compatible = "mediatek,mt8167-dsi", "mediatek,mt2701-dsi";
And this patch is not necessary.
Quoted 22 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 1 file changed, 1 insertion(+)drivers/gpu/drm/mediatek/mtk_dsi.c +1
-1@@ -1301,6 +1301,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {static const struct of_device_id mtk_dsi_of_match[] = { { .compatible ="mediatek,mt2701-dsi" , .data = &mt2701_dsi_driver_data }, + { .compatible ="mediatek,mt8167-dsi" , .data = &mt2701_dsi_driver_data }, { .compatible ="mediatek,mt8173-dsi" , .data = &mt8173_dsi_driver_data }, { .compatible ="mediatek,mt8183-dsi" , .data = &mt8183_dsi_driver_data }, { .compatible ="mediatek,mt8186-dsi" , .data = &mt8186_dsi_driver_data }, --2.43.0
Re: [PATCH v3 5/6] drm/mediatek: dsi: Add compatible for mt8167-dsi
Quoted 9 lines
Quoted 2 lines
The mt8167 DSI controller is fully compatible with the one found in mt2701. Device tree documentation is already present upstream.
If mt8167 DSI is fully compatible with mt2701 DSI, I think the binding document and device tree should be modified. In device tree,
compatible = "mediatek,mt8167-dsi", "mediatek,mt2701-dsi";And this patch is not necessary.
Hi, if I understand your review correctly that's what v2 [1] of this patch did, but the change was rejected during review.
As far as I can see there is no win-win solution here. This tricky situation derives from the fact that in last year's submissions the change was only partially merged - the bindings went upstream while the driver did not, and now we have to work around this. In v3 I tried to address the issue by actually implementing what the binding document says.
I'll be happy to resubmit v4 but I need to know what's the consensus here.
Thanks!
Quoted 22 lines
Quoted 22 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 1 file changed, 1 insertion(+)drivers/gpu/drm/mediatek/mtk_dsi.c +1
-1@@ -1301,6 +1301,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {static const struct of_device_id mtk_dsi_of_match[] = { { .compatible ="mediatek,mt2701-dsi" , .data = &mt2701_dsi_driver_data }, + { .compatible ="mediatek,mt8167-dsi" , .data = &mt2701_dsi_driver_data }, { .compatible ="mediatek,mt8173-dsi" , .data = &mt8173_dsi_driver_data }, { .compatible ="mediatek,mt8183-dsi" , .data = &mt8183_dsi_driver_data }, { .compatible ="mediatek,mt8186-dsi" , .data = &mt8186_dsi_driver_data }, --2.43.0
Signature · 2 lines
Luca Leonardo Scorcia [email protected]
Re: [PATCH v3 5/6] drm/mediatek: dsi: Add compatible for mt8167-dsi
Quoted 16 lines · Luca Leonardo Scorcia
External email : Please do not click links or open attachments until you have verified the sender or the content.
Quoted 9 lines
Quoted 2 lines
The mt8167 DSI controller is fully compatible with the one found in mt2701. Device tree documentation is already present upstream.
If mt8167 DSI is fully compatible with mt2701 DSI, I think the binding document and device tree should be modified. In device tree,
compatible = "mediatek,mt8167-dsi", "mediatek,mt2701-dsi";And this patch is not necessary.
Hi, if I understand your review correctly that's what v2 [1] of this patch did, but the change was rejected during review.
Quoted 7 lines
As far as I can see there is no win-win solution here. This tricky situation derives from the fact that in last year's submissions the change was only partially merged - the bindings went upstream while the driver did not, and now we have to work around this. In v3 I tried to address the issue by actually implementing what the binding document says.
I'll be happy to resubmit v4 but I need to know what's the consensus here.
You mean Krzysztof's comment?
He has two comment.
The first is 'remove'. You actually not remove "mediatek,mt8167-dsi". You change it.
The second is about fallback. I'm also not sure why he says it's NAK. Also a bad wording? After Angelo's comment, Krzysztof does not response.
I also do not know what Krzysztof think.
I agree with Angelo. Single "mediatek,mt8167-dsi" does not reflect the hardware compatible but fallback does. Maybe describe more information (hardware) to Krzysztof, and ask what's the better way to do.
Regards,
CK
Quoted 30 lines
Thanks!
Quoted 12 lines
Quoted 12 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 1 file changed, 1 insertion(+)drivers/gpu/drm/mediatek/mtk_dsi.c +0
-0@@ -1301,6 +1301,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {Quoted 10 lines
Quoted 10 lines
drivers/gpu/drm/mediatek/mtk_dsi.c +1
-1static const struct of_device_id mtk_dsi_of_match[] = { { .compatible ="mediatek,mt2701-dsi" , .data = &mt2701_dsi_driver_data }, + { .compatible ="mediatek,mt8167-dsi" , .data = &mt2701_dsi_driver_data }, { .compatible ="mediatek,mt8173-dsi" , .data = &mt8173_dsi_driver_data }, { .compatible ="mediatek,mt8183-dsi" , .data = &mt8183_dsi_driver_data }, { .compatible ="mediatek,mt8186-dsi" , .data = &mt8186_dsi_driver_data }, --2.43.0
--
Luca Leonardo Scorcia
[email protected]
AngeloGioacchino Del Regno
maintainerRe: [PATCH v3 5/6] drm/mediatek: dsi: Add compatible for mt8167-dsi
Il 03/03/26 08:56, CK Hu (胡俊光) ha scritto:
Quoted 25 lines · Luca Leonardo Scorcia
Quoted 16 lines
External email : Please do not click links or open attachments until you have verified the sender or the content.
Quoted 9 lines
Quoted 2 lines
The mt8167 DSI controller is fully compatible with the one found in mt2701. Device tree documentation is already present upstream.
If mt8167 DSI is fully compatible with mt2701 DSI, I think the binding document and device tree should be modified. In device tree,
compatible = "mediatek,mt8167-dsi", "mediatek,mt2701-dsi";And this patch is not necessary.
Hi, if I understand your review correctly that's what v2 [1] of this patch did, but the change was rejected during review.
Quoted 7 lines
As far as I can see there is no win-win solution here. This tricky situation derives from the fact that in last year's submissions the change was only partially merged - the bindings went upstream while the driver did not, and now we have to work around this. In v3 I tried to address the issue by actually implementing what the binding document says.
I'll be happy to resubmit v4 but I need to know what's the consensus here.
Quoted 9 lines
You mean Krzysztof's comment?
He has two comment.
The first is 'remove'. You actually not remove "mediatek,mt8167-dsi". You change it.
The second is about fallback. I'm also not sure why he says it's NAK. Also a bad wording? After Angelo's comment, Krzysztof does not response.
I also do not know what Krzysztof think.
I agree with Angelo. Single "mediatek,mt8167-dsi" does not reflect the hardware compatible but fallback does. Maybe describe more information (hardware) to Krzysztof, and ask what's the better way to do.
First of all: I would be happy with having
compatible = "mediatek,mt8167-dsi", "mediatek,mt2701-dsi";
in the devicetree, and to drop this patch - but that's not possible, check below.
The problem that Krzysztof was raising is that the bindings currently define the "mediatek,mt8167-dsi" as single compatible with no fallback, and removing it would break the ABI (as the bindings are not used only for Linux, but also for bootloaders).
Even though I can try my best to convince him, this is a real problem: mistakes were made in the past, and the only way to get the mt8167-dsi supported right now is to, unfortunately, add the compatible in mtk_dsi.c.
I don't like that, and I see that you (CK) don't as well, but that's the result of past mistakes... and apparently we can't do anything about this if not to *uselessly clutter the driver* with that.
So, that said...
I'm sad to say that this patch is the only way to get this SoC probed by mtk_dsi and that there's no other way around it, because the bindings maintainers are forbidding us from removing the bad compatible (which was *never* used anyway) from there and making it right with allowing it only under 2701 fallback.
I'm moving krzk to the To: field of this email in hope to get back a reply that sounds like "you misunderstood me, you can do it", but I'm not positive about this.
Krzysztof, please confirm or deny what I said.
Regards,
Angelo
Quoted 34 lines
Regards,
CKQuoted 30 lines
Thanks!
Quoted 12 lines
Quoted 12 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- drivers/gpu/drm/mediatek/mtk_dsi.c | 1 + 1 file changed, 1 insertion(+)drivers/gpu/drm/mediatek/mtk_dsi.c +0
-0@@ -1301,6 +1301,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {Quoted 10 lines
Quoted 10 lines
drivers/gpu/drm/mediatek/mtk_dsi.c +1
-1static const struct of_device_id mtk_dsi_of_match[] = { { .compatible ="mediatek,mt2701-dsi" , .data = &mt2701_dsi_driver_data }, + { .compatible ="mediatek,mt8167-dsi" , .data = &mt2701_dsi_driver_data }, { .compatible ="mediatek,mt8173-dsi" , .data = &mt8173_dsi_driver_data }, { .compatible ="mediatek,mt8183-dsi" , .data = &mt8183_dsi_driver_data }, { .compatible ="mediatek,mt8186-dsi" , .data = &mt8186_dsi_driver_data }, --2.43.0
--
Luca Leonardo Scorcia
[email protected]
PATCH v3 6/6 gpu: drm: mediatek: ovl: add specific entry for mt8167
In reply to Luca Leonardo ScorciaFrom: Val Packett <[email protected]>
While this configuration is otherwise identical to mt8173, according to Android kernel sources, this SoC does need smi_id_en.
--- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
drivers/gpu/drm/mediatek/mtk_disp_ovl.c +12 -0
@@ -671,6 +671,16 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), }; +static const struct mtk_disp_ovl_data mt8167_ovl_driver_data = { + .addr =DISP_REG_OVL_ADDR_MT8173 , + .gmc_bits =8 , + .layer_nr =4 , + .fmt_rgb565_is_0 = true, + .smi_id_en = true, + .formats = mt8173_formats, + .num_formats =ARRAY_SIZE (mt8173_formats), +}; +static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .addr =DISP_REG_OVL_ADDR_MT8173 , .gmc_bits =8 ,
@@ -742,6 +752,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible ="mediatek,mt2701-disp-ovl" , .data = &mt2701_ovl_driver_data}, + { .compatible ="mediatek,mt8167-disp-ovl" , + .data = &mt8167_ovl_driver_data}, { .compatible ="mediatek,mt8173-disp-ovl" , .data = &mt8173_ovl_driver_data}, { .compatible ="mediatek,mt8183-disp-ovl" ,
Signature · 1 line
2.43.0
Re: [PATCH v3 6/6] gpu: drm: mediatek: ovl: add specific entry for mt8167
title:
drm/mediatek: ovl: add specific entry for mt8167
After this modification,
Quoted 48 lines · Luca Leonardo Scorcia
External email : Please do not click links or open attachments until you have verified the sender or the content.
From: Val Packett <[email protected]>
While this configuration is otherwise identical to mt8173, according to Android kernel sources, this SoC does need
smi_id_en.Signed-off-by Val Packett <[email protected]>Signed-off-by Luca Leonardo Scorcia <[email protected]>Reviewed-by AngeloGioacchino Del Regno <[email protected]>--- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/mediatek/mtk_disp_ovl.c +12
-1@@ -671,6 +671,16 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), }; +static const struct mtk_disp_ovl_data mt8167_ovl_driver_data = { + .addr =DISP_REG_OVL_ADDR_MT8173 , + .gmc_bits =8 , + .layer_nr =4 , + .fmt_rgb565_is_0 = true, + .smi_id_en = true, + .formats = mt8173_formats, + .num_formats =ARRAY_SIZE (mt8173_formats), +}; +static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .addr =DISP_REG_OVL_ADDR_MT8173 , .gmc_bits =8 ,@@ -742,6 +752,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible ="mediatek,mt2701-disp-ovl" , .data = &mt2701_ovl_driver_data}, + { .compatible ="mediatek,mt8167-disp-ovl" , + .data = &mt8167_ovl_driver_data}, { .compatible ="mediatek,mt8173-disp-ovl" , .data = &mt8173_ovl_driver_data}, { .compatible ="mediatek,mt8183-disp-ovl" , --2.43.0
Re: [PATCH v3 6/6] gpu: drm: mediatek: ovl: add specific entry for mt8167
In reply to Luca Leonardo ScorciaHi, Luca:
Luca Leonardo Scorcia <[email protected]> 於 2026年2月23日週一 下午4:26寫道：
Quoted 5 lines
From: Val Packett <[email protected]>
While this configuration is otherwise identical to mt8173, according to Android kernel sources, this SoC does need
smi_id_en.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
Quoted 41 lines
Signed-off-by Val Packett <[email protected]>Signed-off-by Luca Leonardo Scorcia <[email protected]>Reviewed-by AngeloGioacchino Del Regno <[email protected]>--- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/mediatek/mtk_disp_ovl.c +12
-1@@ -671,6 +671,16 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { .num_formats = ARRAY_SIZE(mt8173_formats), }; +static const struct mtk_disp_ovl_data mt8167_ovl_driver_data = { + .addr =DISP_REG_OVL_ADDR_MT8173 , + .gmc_bits =8 , + .layer_nr =4 , + .fmt_rgb565_is_0 = true, + .smi_id_en = true, + .formats = mt8173_formats, + .num_formats =ARRAY_SIZE (mt8173_formats), +}; +static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .addr =DISP_REG_OVL_ADDR_MT8173 , .gmc_bits =8 ,@@ -742,6 +752,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible ="mediatek,mt2701-disp-ovl" , .data = &mt2701_ovl_driver_data}, + { .compatible ="mediatek,mt8167-disp-ovl" , + .data = &mt8167_ovl_driver_data}, { .compatible ="mediatek,mt8173-disp-ovl" , .data = &mt8173_ovl_driver_data}, { .compatible ="mediatek,mt8183-disp-ovl" , --2.43.0
Re: (subset) [PATCH v3 0/6] Add support for mt8167 display blocks
In reply to Luca Leonardo ScorciaQuoted 11 lines · Luca Leonardo Scorcia
This series adds support for the display blocks on MediaTek mt8167. Tested on Xiaomi Mi Smart Clock x04g.
The first patch just does some reordering of dts nodes with no other changes as this makes later patches cleaner and easier to follow.
v3:
- Added mt8167-dsi compatible to driver instead of changing the binding;
- Resolved patch formatting issues.[...]
Applied to v7.0-next/dts64, thanks!
[1/6] arm64: dts: mt8167: Reorder nodes according to mmio address
commit: d51b7191f2072e11259edd2bff88385891d0ae56
Cheers,
Angelo
Re: (subset) [PATCH v3 0/6] Add support for mt8167 display blocks
In reply to Luca Leonardo ScorciaQuoted 11 lines · Luca Leonardo Scorcia
This series adds support for the display blocks on MediaTek mt8167. Tested on Xiaomi Mi Smart Clock x04g.
The first patch just does some reordering of dts nodes with no other changes as this makes later patches cleaner and easier to follow.
v3:
- Added mt8167-dsi compatible to driver instead of changing the binding;
- Resolved patch formatting issues.[...]
Applied, thanks!
[3/6] dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
commit: 7df891f2c39442c120fb4f9bfdd7c80e6de84015
Best regards,
Signature · 1 line
~Vinod