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Add support for mt8167 display blocks

PATCH Superseded Luca Leonardo Scorcia 3 participants 10 messages Feb 15 – Feb 16

Subsystems (7)
Device tree bindings DRM drivers DRM misc Arm MediaTek +3 more subsystems

v1 of 4 Superseded Latest is v4 →

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Luca Leonardo Scorcia

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#0 lore raw

cover Add support for mt8167 display blocks

This series adds support for the display blocks on MediaTek mt8167. Tested on Xiaomi Mi Smart Clock x04g.

The first patch just does some reordering of dts nodes with no other changes as this makes later patches cleaner and easier to follow.

Luca Leonardo Scorcia (3):
arm64: dts: mt8167: Reorder nodes according to mmio address
dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
arm64: dts: mediatek: mt8167: Add DRM nodes

Val Packett (1):
gpu: drm: mediatek: ovl: add specific entry for mt8167

 .../display/mediatek/mediatek,aal.yaml        |   1 +
 .../display/mediatek/mediatek,ccorr.yaml      |   4 +-
 .../display/mediatek/mediatek,dither.yaml     |   1 +
 .../display/mediatek/mediatek,dsi.yaml        |   5 +-
 .../display/mediatek/mediatek,gamma.yaml      |   1 +
 .../display/mediatek/mediatek,ovl.yaml        |   1 +
 .../display/mediatek/mediatek,rdma.yaml       |   1 +
 .../display/mediatek/mediatek,wdma.yaml       |   4 +-
 .../bindings/phy/mediatek,dsi-phy.yaml        |   1 +
 arch/arm64/boot/dts/mediatek/mt8167.dtsi      | 450 ++++++++++++++++--
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c       |  12 +
 11 files changed, 446 insertions(+), 35 deletions(-)
Signature · 1 line
2.43.0
author
#1 lore raw

PATCH 1/4 arm64: dts: mt8167: Reorder nodes according to mmio address

In preparation for adding display nodes. No other changes.

Signed-off-by Luca Leonardo Scorcia <[email protected]>
---
 arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++------------
 1 file changed, 34 insertions(+), 34 deletions(-)
arch/arm64/boot/dts/mediatek/mt8167.dtsi +34 -34
index 2374c0953057..27cf32d7ae35 100644
@@ -29,12 +29,6 @@ infracfg: infracfg@10001000 {
 			#clock-cells = <1>;
 		};
 
-		apmixedsys: apmixedsys@10018000 {
-			compatible = "mediatek,mt8167-apmixedsys", "syscon";
-			reg = <0 0x10018000 0 0x710>;
-			#clock-cells = <1>;
-		};
-
 		scpsys: syscon@10006000 {
 			compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
 			reg = <0 0x10006000 0 0x1000>;

@@ -101,18 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN {
 			};
 		};
 
-		imgsys: syscon@15000000 {
-			compatible = "mediatek,mt8167-imgsys", "syscon";
-			reg = <0 0x15000000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
-		vdecsys: syscon@16000000 {
-			compatible = "mediatek,mt8167-vdecsys", "syscon";
-			reg = <0 0x16000000 0 0x1000>;
-			#clock-cells = <1>;
-		};
-
 		pio: pinctrl@1000b000 {
 			compatible = "mediatek,mt8167-pinctrl";
 			reg = <0 0x1000b000 0 0x1000>;

@@ -124,12 +106,36 @@ pio: pinctrl@1000b000 {
 			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		apmixedsys: apmixedsys@10018000 {
+			compatible = "mediatek,mt8167-apmixedsys", "syscon";
+			reg = <0 0x10018000 0 0x710>;
+			#clock-cells = <1>;
+		};
+
+		iommu: m4u@10203000 {
+			compatible = "mediatek,mt8167-m4u";
+			reg = <0 0x10203000 0 0x1000>;
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+			#iommu-cells = <1>;
+		};
+
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8167-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb0: larb@14016000 {
+			compatible = "mediatek,mt8167-smi-larb";
+			reg = <0 0x14016000 0 0x1000>;
+			mediatek,smi = <&smi_common>;
+			clocks = <&mmsys CLK_MM_SMI_LARB0>,
+				 <&mmsys CLK_MM_SMI_LARB0>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+		};
+
 		smi_common: smi@14017000 {
 			compatible = "mediatek,mt8167-smi-common";
 			reg = <0 0x14017000 0 0x1000>;

@@ -139,14 +145,10 @@ smi_common: smi@14017000 {
 			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
 		};
 
-		larb0: larb@14016000 {
-			compatible = "mediatek,mt8167-smi-larb";
-			reg = <0 0x14016000 0 0x1000>;
-			mediatek,smi = <&smi_common>;
-			clocks = <&mmsys CLK_MM_SMI_LARB0>,
-				 <&mmsys CLK_MM_SMI_LARB0>;
-			clock-names = "apb", "smi";
-			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+		imgsys: syscon@15000000 {
+			compatible = "mediatek,mt8167-imgsys", "syscon";
+			reg = <0 0x15000000 0 0x1000>;
+			#clock-cells = <1>;
 		};
 
 		larb1: larb@15001000 {

@@ -159,6 +161,12 @@ larb1: larb@15001000 {
 			power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
 		};
 
+		vdecsys: syscon@16000000 {
+			compatible = "mediatek,mt8167-vdecsys", "syscon";
+			reg = <0 0x16000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		larb2: larb@16010000 {
 			compatible = "mediatek,mt8167-smi-larb";
 			reg = <0 0x16010000 0 0x1000>;

@@ -168,13 +176,5 @@ larb2: larb@16010000 {
 			clock-names = "apb", "smi";
 			power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
 		};
-
-		iommu: m4u@10203000 {
-			compatible = "mediatek,mt8167-m4u";
-			reg = <0 0x10203000 0 0x1000>;
-			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
-			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
-			#iommu-cells = <1>;
-		};
 	};
 };
Signature · 1 line
2.43.0
author
#3 lore raw

PATCH 2/4 dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167

In reply to Luca Leonardo Scorcia

Add compatibles for various display-related blocks of MediaTek mt8167.

Signed-off-by Luca Leonardo Scorcia <[email protected]>
---
 .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++-
 .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml   | 5 ++++-
 .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml  | 4 +++-
 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml  | 1 +
 9 files changed, 16 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +1 -0
index daf90ebb39bf..4bbea72b292a 100644
@@ -33,6 +33,7 @@ properties:
           - enum:
               - mediatek,mt2712-disp-aal
               - mediatek,mt6795-disp-aal
+              - mediatek,mt8167-disp-aal
           - const: mediatek,mt8173-disp-aal
       - items:
           - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +3 -1
index fca8e7bb0cbc..5c5068128d0c 100644
@@ -25,7 +25,9 @@ properties:
           - mediatek,mt8183-disp-ccorr
           - mediatek,mt8192-disp-ccorr
       - items:
-          - const: mediatek,mt8365-disp-ccorr
+          - enum:
+              - mediatek,mt8167-disp-ccorr
+              - mediatek,mt8365-disp-ccorr
           - const: mediatek,mt8183-disp-ccorr
       - items:
           - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +1 -0
index abaf27916d13..891c95be15b9 100644
@@ -26,6 +26,7 @@ properties:
           - mediatek,mt8183-disp-dither
       - items:
           - enum:
+              - mediatek,mt8167-disp-dither
               - mediatek,mt8186-disp-dither
               - mediatek,mt8188-disp-dither
               - mediatek,mt8192-disp-dither
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +4 -1
index 27ffbccc2a08..bcbde16648c0 100644
@@ -25,11 +25,14 @@ properties:
       - enum:
           - mediatek,mt2701-dsi
           - mediatek,mt7623-dsi
-          - mediatek,mt8167-dsi
           - mediatek,mt8173-dsi
           - mediatek,mt8183-dsi
           - mediatek,mt8186-dsi
           - mediatek,mt8188-dsi
+      - items:
+          - enum:
+              - mediatek,mt8167-dsi
+          - const: mediatek,mt2701-dsi
       - items:
           - enum:
               - mediatek,mt6795-dsi
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +1 -0
index 48542dc7e784..ec1054bb06d4 100644
@@ -28,6 +28,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt6795-disp-gamma
+              - mediatek,mt8167-disp-gamma
           - const: mediatek,mt8173-disp-gamma
       - items:
           - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +1 -0
index 4f110635afb6..679f731f0f15 100644
@@ -23,6 +23,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt2701-disp-ovl
+          - mediatek,mt8167-disp-ovl
           - mediatek,mt8173-disp-ovl
           - mediatek,mt8183-disp-ovl
           - mediatek,mt8192-disp-ovl
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +1 -0
index 878f676b581f..cb187a95c11e 100644
@@ -36,6 +36,7 @@ properties:
           - enum:
               - mediatek,mt7623-disp-rdma
               - mediatek,mt2712-disp-rdma
+              - mediatek,mt8167-disp-rdma
           - const: mediatek,mt2701-disp-rdma
       - items:
           - enum:
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +3 -1
index a3a2b71a4523..816841a96133 100644
@@ -24,7 +24,9 @@ properties:
       - enum:
           - mediatek,mt8173-disp-wdma
       - items:
-          - const: mediatek,mt6795-disp-wdma
+          - enum:
+              - mediatek,mt6795-disp-wdma
+              - mediatek,mt8167-disp-wdma
           - const: mediatek,mt8173-disp-wdma
 
   reg:
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +1 -0
index acdbce937b0a..c6d0bbdbe0e2 100644
@@ -23,6 +23,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt7623-mipi-tx
+              - mediatek,mt8167-mipi-tx
           - const: mediatek,mt2701-mipi-tx
       - items:
           - enum:
Signature · 1 line
2.43.0
Reviewed-by on v1 2/4
#4 lore raw

Re: [PATCH 2/4] dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167

Quoted 14 lines · Luca Leonardo Scorcia

Add compatibles for various display-related blocks of MediaTek mt8167.

Signed-off-by Luca Leonardo Scorcia <[email protected]>
---
 .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++-
 .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml   | 5 ++++-
 .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml  | 4 +++-
 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml  | 1 +
 9 files changed, 16 insertions(+), 3 deletions(-)
Reviewed-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

maintainer
#5 lore raw

Re: [PATCH 2/4] dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167

In reply to Luca Leonardo Scorcia

Il 15/02/26 09:53, Luca Leonardo Scorcia ha scritto:

Quoted 3 lines

Add compatibles for various display-related blocks of MediaTek mt8167.

Signed-off-by Luca Leonardo Scorcia <[email protected]>

Awesome. I'd give you my R-b seal of approval, but there's a few nitpicks that you have to address. Please check below.

Quoted 16 lines
---
  .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
  .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++-
  .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
  .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml   | 5 ++++-
  .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
  .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 1 +
  .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 1 +
  .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml  | 4 +++-
  Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml  | 1 +
  9 files changed, 16 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +0 -0
index daf90ebb39bf..4bbea72b292a 100644

...snip...

Quoted 7 lines
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +0 -0
index 27ffbccc2a08..bcbde16648c0 100644
@@ -25,11 +25,14 @@ properties:
        - enum:
            - mediatek,mt2701-dsi

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml properties: · line 35

Quoted 10 lines
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +4 -1
            - mediatek,mt7623-dsi
-          - mediatek,mt8167-dsi
            - mediatek,mt8173-dsi
            - mediatek,mt8183-dsi
            - mediatek,mt8186-dsi
            - mediatek,mt8188-dsi
+      - items:
+          - enum:
+              - mediatek,mt8167-dsi
+          - const: mediatek,mt2701-dsi

This needs its own patch with its own commit description - as this change is not really "normal".

You have to mention that you're removing the "mediatek,mt8167-dsi" compatible from that list and that it is safe to do so because:
- Bootloader doesn't rely on this single compatible; and
- There was never any upstreamed devicetree using this single compatible; and
- The MT8167 DSI Controller is fully compatible with the one found in MT2701.

So, please, split this one out of the entire batch.

Quoted 5 lines
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +0 -0
        - items:
            - enum:
                - mediatek,mt6795-dsi
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +0 -0
index 48542dc7e784..ec1054bb06d4 100644

...snip...

Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml properties: · line 29

Quoted 12 lines
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +1 -0
index acdbce937b0a..c6d0bbdbe0e2 100644
@@ -23,6 +23,7 @@ properties:
        - items:
            - enum:
                - mediatek,mt7623-mipi-tx
+              - mediatek,mt8167-mipi-tx
            - const: mediatek,mt2701-mipi-tx
        - items:
            - enum:

The PHY bindings are not applied by the same maintainer as the display bindings:
please split that out in a different patch, so that each maintainer can apply the relevant patch(es).

Besides - apart from those nits, everything in here looks great.

Cheers,
Angelo

author
#6 lore raw

PATCH 3/4 arm64: dts: mediatek: mt8167: Add DRM nodes

In reply to Luca Leonardo Scorcia

Add all the DRM nodes required to get DSI to work on MT8167 SoC.

Signed-off-by Luca Leonardo Scorcia <[email protected]>
---
 arch/arm64/boot/dts/mediatek/mt8167.dtsi | 386 +++++++++++++++++++++++
 1 file changed, 386 insertions(+)
arch/arm64/boot/dts/mediatek/mt8167.dtsi +386 -0
index 27cf32d7ae35..c6306234e592 100644
@@ -16,6 +16,20 @@
 / {
 	compatible = "mediatek,mt8167";
 
+	aliases {
+		aal0 = &aal;
+		ccorr0 = &ccorr;
+		color0 = &color;
+		dither0 = &dither;
+		dsi0 = &dsi;
+		gamma0 = &gamma;
+		ovl0 = &ovl0;
+		pwm0 = &disp_pwm;
+		rdma0 = &rdma0;
+		rdma1 = &rdma1;
+		wdma0 = &wdma;
+	};
+
 	soc {
 		topckgen: topckgen@10000000 {
 			compatible = "mediatek,mt8167-topckgen", "syscon";

@@ -120,10 +134,371 @@ iommu: m4u@10203000 {
 			#iommu-cells = <1>;
 		};
 
+		disp_pwm: pwm@1100f000 {
+			compatible = "mediatek,mt8167-disp-pwm",
+				     "mediatek,mt8173-disp-pwm";
+			reg = <0 0x1100f000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_PWM_26M>,
+				 <&mmsys CLK_MM_DISP_PWM_MM>;
+			clock-names = "main",
+				      "mm";
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8167-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
 			#clock-cells = <1>;
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mmsys_main: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&ovl0_in>;
+				};
+
+				mmsys_ext: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&rdma1_in>;
+				};
+			};
+		};
+
+		ovl0: ovl0@14007000 {
+			compatible = "mediatek,mt8167-disp-ovl";
+			reg = <0 0x14007000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
+			iommus = <&iommu M4U_PORT_DISP_OVL0>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					ovl0_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mmsys_main>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					ovl0_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&color_in>;
+					};
+				};
+			};
+		};
+
+		rdma0: rdma0@14009000 {
+			compatible = "mediatek,mt8167-disp-rdma",
+				     "mediatek,mt2701-disp-rdma";
+			reg = <0 0x14009000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					rdma0_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&dither_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					rdma0_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&dsi_in>;
+					};
+				};
+			};
+		};
+
+		rdma1: rdma1@1400a000 {
+			compatible = "mediatek,mt8167-disp-rdma",
+				     "mediatek,mt2701-disp-rdma";
+			reg = <0 0x1400a000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
+			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					rdma1_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mmsys_ext>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					rdma1_out: endpoint@0 {
+						reg = <0>;
+					};
+				};
+			};
+		};
+
+		wdma: wdma0@1400b000 {
+			compatible = "mediatek,mt8167-disp-wdma",
+				     "mediatek,mt8173-disp-wdma";
+			reg = <0 0x1400b000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_WDMA>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+			iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+		};
+
+		color: color@1400c000 {
+			compatible = "mediatek,mt8167-disp-color";
+			reg = <0 0x1400c000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_COLOR>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					color_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&ovl0_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					color_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&ccorr_in>;
+					};
+				};
+			};
+		};
+
+		ccorr: ccorr@1400d000 {
+			compatible = "mediatek,mt8167-disp-ccorr",
+				     "mediatek,mt8183-disp-ccorr";
+			reg = <0 0x1400d000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_CCORR>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					ccorr_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&color_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					ccorr_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&aal_in>;
+					};
+				};
+			};
+		};
+
+		aal: aal@1400e000 {
+			compatible = "mediatek,mt8167-disp-aal",
+				     "mediatek,mt8173-disp-aal";
+			reg = <0 0x1400e000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_AAL>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					aal_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&ccorr_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					aal_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&gamma_in>;
+					};
+				};
+			};
+		};
+
+		gamma: gamma@1400f000 {
+			compatible = "mediatek,mt8167-disp-gamma",
+				     "mediatek,mt8173-disp-gamma";
+			reg = <0 0x1400f000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					gamma_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&aal_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					gamma_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&dither_in>;
+					};
+				};
+			};
+		};
+
+		dither: dither@14010000 {
+			compatible = "mediatek,mt8167-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x14010000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_DITHER>;
+			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					dither_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&gamma_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					dither_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&rdma0_in>;
+					};
+				};
+			};
+		};
+
+		dsi: dsi@14012000 {
+			compatible = "mediatek,mt8167-dsi",
+				     "mediatek,mt2701-dsi";
+			reg = <0 0x14012000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DSI_ENGINE>,
+				 <&mmsys CLK_MM_DSI_DIGITAL>,
+				 <&mipi_tx>;
+			clock-names = "engine", "digital", "hs";
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
+			phys = <&mipi_tx>;
+			phy-names = "dphy";
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					dsi_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&rdma0_out>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					dsi_out: endpoint@0 {
+						reg = <0>;
+					};
+				};
+			};
+		};
+
+		mutex: mutex@14015000 {
+			compatible = "mediatek,mt8167-disp-mutex";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
 		};
 
 		larb0: larb@14016000 {

@@ -145,6 +520,17 @@ smi_common: smi@14017000 {
 			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
 		};
 
+		mipi_tx: dsi-phy@14018000 {
+			compatible = "mediatek,mt8167-mipi-tx",
+				     "mediatek,mt2701-mipi-tx";
+			reg = <0 0x14018000 0 0x90>;
+			clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>;
+			clock-output-names = "mipi_tx0_pll";
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		imgsys: syscon@15000000 {
 			compatible = "mediatek,mt8167-imgsys", "syscon";
 			reg = <0 0x15000000 0 0x1000>;
Signature · 1 line
2.43.0
maintainer
#7 lore raw

Re: [PATCH 3/4] arm64: dts: mediatek: mt8167: Add DRM nodes

Il 15/02/26 09:53, Luca Leonardo Scorcia ha scritto:

Quoted 33 lines

Add all the DRM nodes required to get DSI to work on MT8167 SoC.

Signed-off-by Luca Leonardo Scorcia <[email protected]>
---
  arch/arm64/boot/dts/mediatek/mt8167.dtsi | 386 +++++++++++++++++++++++
  1 file changed, 386 insertions(+)
arch/arm64/boot/dts/mediatek/mt8167.dtsi +14 -0
index 27cf32d7ae35..c6306234e592 100644
@@ -16,6 +16,20 @@
  / {
  	compatible = "mediatek,mt8167";
 
+	aliases {
+		aal0 = &aal;
+		ccorr0 = &ccorr;
+		color0 = &color;
+		dither0 = &dither;
+		dsi0 = &dsi;
+		gamma0 = &gamma;
+		ovl0 = &ovl0;
+		pwm0 = &disp_pwm;
+		rdma0 = &rdma0;
+		rdma1 = &rdma1;
+		wdma0 = &wdma;
+	};
+
  	soc {
  		topckgen: topckgen@10000000 {
  			compatible = "mediatek,mt8167-topckgen", "syscon";

arch/arm64/boot/dts/mediatek/mt8167.dtsi iommu: m4u@10203000 { · line 139

Quoted 6 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +3 -0
@@ -120,10 +134,371 @@ iommu: m4u@10203000 {
  			#iommu-cells = <1>;
  		};
 
+		disp_pwm: pwm@1100f000 {
+			compatible = "mediatek,mt8167-disp-pwm",
+				     "mediatek,mt8173-disp-pwm";

The compatible strings fit in a single line. Up to 100 columns it's fine: for every node additions that you're doing, please use a single line wherever you can.

arch/arm64/boot/dts/mediatek/mt8167.dtsi iommu: m4u@10203000 { · line 144

Quoted 5 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +5 -0
+			reg = <0 0x1100f000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_PWM_26M>,
+				 <&mmsys CLK_MM_DISP_PWM_MM>;
+			clock-names = "main",
+				      "mm";

That also includes clock-names and, where possible, also clocks and anything else really.

Quoted 14 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +10 -0
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
  		mmsys: syscon@14000000 {
  			compatible = "mediatek,mt8167-mmsys", "syscon";
  			reg = <0 0x14000000 0 0x1000>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
  			#clock-cells = <1>;
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;

arch/arm64/boot/dts/mediatek/mt8167.dtsi iommu: m4u@10203000 { · line 168

Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +10 -0
+
+				mmsys_main: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&ovl0_in>;
+				};
+
+				mmsys_ext: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&rdma1_in>;
+				};

Nice! Thanks for expressing those connections with an OF Graph. That makes things simpler for other devices based on the same SoC.

Quoted 9 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +9 -0
+			};
+		};
+
+		ovl0: ovl0@14007000 {
+			compatible = "mediatek,mt8167-disp-ovl";
+			reg = <0 0x14007000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
+			iommus = <&iommu M4U_PORT_DISP_OVL0>;

arch/arm64/boot/dts/mediatek/mt8167.dtsi iommu: m4u@10203000 { · line 187

Quoted 10 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +10 -0
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;

For OVL, RDMA, COLOR, CCORR, and others, you have only one endpoint.

Since there is only one, you can compress the nodes and avoid the text bloat (and please do), by declaring the nodes like:

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					ovl0_in: endpoint {
						remote-endpoint = <&mmsys_main>;
					};
				};

				port@1 {
					reg = <1>;
					ovl0_out: endpoint {
						remote-endpoint = <&color_in>;
					};
				};
			};

Please do this for all nodes where you have only a single endpoint (so, for everything but mmsys).

Quoted 17 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +17 -0
+					ovl0_in: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mmsys_main>;
+					};
+				};
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					ovl0_out: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&color_in>;
+					};
+				};
+			};
+		};

...snip...

Quoted 21 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +21 -0
+
+		dsi: dsi@14012000 {
+			compatible = "mediatek,mt8167-dsi",
+				     "mediatek,mt2701-dsi";
+			reg = <0 0x14012000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DSI_ENGINE>,
+				 <&mmsys CLK_MM_DSI_DIGITAL>,
+				 <&mipi_tx>;
+			clock-names = "engine", "digital", "hs";
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
+			phys = <&mipi_tx>;
+			phy-names = "dphy";
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;

..snip..

arch/arm64/boot/dts/mediatek/mt8167.dtsi iommu: m4u@10203000 { · line 493

Quoted 9 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +9 -0
+
+				port@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					dsi_out: endpoint@0 {
+						reg = <0>;
+					};
+				};

That's shorter, and simpler:

				port@1 {
					reg = <1>;
					dsi_out: endpoint { };
				};
Quoted 12 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +8 -0
+			};
+		};
+
+		mutex: mutex@14015000 {
+			compatible = "mediatek,mt8167-disp-mutex";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
  		};
 
  		larb0: larb@14016000 {

arch/arm64/boot/dts/mediatek/mt8167.dtsi smi_common: smi@14017000 { · line 525

Quoted 6 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +3 -0
@@ -145,6 +520,17 @@ smi_common: smi@14017000 {
  			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
  		};
 
+		mipi_tx: dsi-phy@14018000 {
+			compatible = "mediatek,mt8167-mipi-tx",
+				     "mediatek,mt2701-mipi-tx";

Fits in a single line :-)

arch/arm64/boot/dts/mediatek/mt8167.dtsi smi_common: smi@14017000 { · line 536

Quoted 11 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +8 -0
+			reg = <0 0x14018000 0 0x90>;
+			clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>;
+			clock-output-names = "mipi_tx0_pll";
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
  		imgsys: syscon@15000000 {
  			compatible = "mediatek,mt8167-imgsys", "syscon";
  			reg = <0 0x15000000 0 0x1000>;

Nice job, btw.

Cheers,
Angelo

author
#8 lore raw

PATCH 4/4 gpu: drm: mediatek: ovl: add specific entry for mt8167

In reply to Luca Leonardo Scorcia

From: Val Packett <[email protected]>

While this configuration is otherwise identical to mt8173, according to Android kernel sources, this SoC does need smi_id_en.

Signed-off-by Val Packett <[email protected]>
Signed-off-by Luca Leonardo Scorcia <[email protected]>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
drivers/gpu/drm/mediatek/mtk_disp_ovl.c +12 -0
index e0236353d499..97a899e4bd99 100644
@@ -671,6 +671,16 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
 
+static const struct mtk_disp_ovl_data mt8167_ovl_driver_data = {
+	.addr = DISP_REG_OVL_ADDR_MT8173,
+	.gmc_bits = 8,
+	.layer_nr = 4,
+	.fmt_rgb565_is_0 = true,
+	.smi_id_en = true,
+	.formats = mt8173_formats,
+	.num_formats = ARRAY_SIZE(mt8173_formats),
+};
+
 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
 	.addr = DISP_REG_OVL_ADDR_MT8173,
 	.gmc_bits = 8,

@@ -742,6 +752,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-ovl",
 	  .data = &mt2701_ovl_driver_data},
+	{ .compatible = "mediatek,mt8167-disp-ovl",
+	  .data = &mt8167_ovl_driver_data},
 	{ .compatible = "mediatek,mt8173-disp-ovl",
 	  .data = &mt8173_ovl_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-ovl",
Signature · 1 line
2.43.0
maintainer Reviewed-by on v1 4/4
#9 lore raw

Re: [PATCH 4/4] gpu: drm: mediatek: ovl: add specific entry for mt8167

Il 15/02/26 09:53, Luca Leonardo Scorcia ha scritto:

Quoted 7 lines

From: Val Packett <[email protected]>

While this configuration is otherwise identical to mt8173, according to Android kernel sources, this SoC does need smi_id_en.

Signed-off-by Val Packett <[email protected]>
Signed-off-by Luca Leonardo Scorcia <[email protected]>

Okay, sure.

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Quoted 34 lines
---
  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
  1 file changed, 12 insertions(+)
drivers/gpu/drm/mediatek/mtk_disp_ovl.c +12 -0
index e0236353d499..97a899e4bd99 100644
@@ -671,6 +671,16 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
  	.num_formats = ARRAY_SIZE(mt8173_formats),
  };
 
+static const struct mtk_disp_ovl_data mt8167_ovl_driver_data = {
+	.addr = DISP_REG_OVL_ADDR_MT8173,
+	.gmc_bits = 8,
+	.layer_nr = 4,
+	.fmt_rgb565_is_0 = true,
+	.smi_id_en = true,
+	.formats = mt8173_formats,
+	.num_formats = ARRAY_SIZE(mt8173_formats),
+};
+
  static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
  	.addr = DISP_REG_OVL_ADDR_MT8173,
  	.gmc_bits = 8,

@@ -742,6 +752,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
  static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
  	{ .compatible = "mediatek,mt2701-disp-ovl",
  	  .data = &mt2701_ovl_driver_data},
+	{ .compatible = "mediatek,mt8167-disp-ovl",
+	  .data = &mt8167_ovl_driver_data},
  	{ .compatible = "mediatek,mt8173-disp-ovl",
  	  .data = &mt8173_ovl_driver_data},
  	{ .compatible = "mediatek,mt8183-disp-ovl",