ARM: dts: aspeed: quanta: Enable pwm fans
Subsystems (2)
PATCH 1/1 ARM: dts: aspeed: quanta: Enable pwm fans
Signed-off-by Patrick Venture <[email protected]>
--- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 51 ++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++ 2 files changed, 57 insertions(+)
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +51 -0
@@ -46,6 +46,57 @@ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; }; }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x1000>; + compatible = "aspeed,ast2500-pwm-tacho"; + clocks = <&pwm_tacho_fixed_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + }; }; &fmc {
arch/arm/boot/dts/aspeed-g4.dtsi +6 -0
@@ -184,6 +184,12 @@ reg = <0x2c>; }; + pwm_tacho_fixed_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + hwrng@1e6e2078 { compatible = "timeriomem_rng"; reg = <0x1e6e2078 0x4>;
Signature · 1 line
2.13.1.611.g7e3b11ae1-goog
Joel Stanley
maintainerQuoted 73 lines · Patrick Venture
Signed-off-by Patrick Venture <[email protected]>--- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 51 ++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++ 2 files changed, 57 insertions(+)arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +51
-0@@ -46,6 +46,57 @@ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; }; }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x1000>; + compatible = "aspeed,ast2500-pwm-tacho"; + clocks = <&pwm_tacho_fixed_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + }; }; &fmc {arch/arm/boot/dts/aspeed-g4.dtsi +0
-0
arch/arm/boot/dts/aspeed-g4.dtsi line 191
Quoted 8 lines
arch/arm/boot/dts/aspeed-g4.dtsi +5
-0@@ -184,6 +184,12 @@ reg = <0x2c>; }; + pwm_tacho_fixed_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + };
This is a bit strange. I don't think it should live at this spot in the device tree.
Quoted 7 lines
arch/arm/boot/dts/aspeed-g4.dtsi +1
-1+ hwrng@1e6e2078 { compatible = "timeriomem_rng"; reg = <0x1e6e2078 0x4>; --2.13.1.611.g7e3b11ae1-goog
If you're referring strictly to the clock, maybe I should put it under:
https://github.com/openbmc/linux/blob/dev-4.10/arch/arm/boot/dts/aspeed-g4.dtsi#L38
Which I didn't notice before :)
Patrick
Quoted 100 lines · Joel Stanley
Quoted 3 lines · Patrick Venture
Signed-off-by Patrick Venture <[email protected]>--- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 51++++++++++++++++++++++++++++
Review
Quoted 4 lines
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++ 2 files changed, 57 insertions(+)(quoted diff) +0
-0
b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dtsarch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 46
Quoted 5 lines
index
e609c53d58f5..3abc2954d26e100644arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +0
-0@@ -46,6 +46,57 @@ gpios = <&gpio ASPEED_GPIO(B, 3)
GPIO_ACTIVE_LOW>;Review
Quoted 57 lines
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +51
-0}; }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x1000>; + compatible = "aspeed,ast2500-pwm-tacho"; + clocks = <&pwm_tacho_fixed_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + }; }; &fmc {(quoted diff) +0
-0
b/arch/arm/boot/dts/aspeed-g4.dtsiarch/arm/boot/dts/aspeed-g4.dtsi line 191
Quoted 12 lines
index
a998a00a2728..c93b0460cada100644arch/arm/boot/dts/aspeed-g4.dtsi +5
-0@@ -184,6 +184,12 @@ reg = <0x2c>; }; + pwm_tacho_fixed_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + };This is a bit strange. I don't think it should live at this spot in the device tree.
Quoted 7 lines
arch/arm/boot/dts/aspeed-g4.dtsi +1
-1+ hwrng@1e6e2078 { compatible = "timeriomem_rng"; reg = <0x1e6e2078 0x4>; --2.13.1.611.g7e3b11ae1-goog
Joel Stanley
maintainerQuoted 5 lines · Patrick Venture
If you're referring strictly to the clock, maybe I should put it under:
https://github.com/openbmc/linux/blob/dev-4.10/arch/arm/boot/dts/aspeed-g4.dtsi#L38
Which I didn't notice before :)
Yep. Lets stick it there.
Quoted 106 lines
Patrick
Quoted 100 lines · Joel Stanley
Quoted 77 lines · Patrick Venture
Signed-off-by Patrick Venture <[email protected]>--- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 51 ++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++ 2 files changed, 57 insertions(+)arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +51
-0@@ -46,6 +46,57 @@ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; }; }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1E786000 0x1000>; + compatible = "aspeed,ast2500-pwm-tacho"; + clocks = <&pwm_tacho_fixed_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + }; };&fmc {
arch/arm/boot/dts/aspeed-g4.dtsi +0
-0arch/arm/boot/dts/aspeed-g4.dtsi line 191
Quoted 8 lines
arch/arm/boot/dts/aspeed-g4.dtsi +5
-0@@ -184,6 +184,12 @@ reg = <0x2c>; }; + pwm_tacho_fixed_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + };This is a bit strange. I don't think it should live at this spot in the device tree.
Quoted 7 lines
arch/arm/boot/dts/aspeed-g4.dtsi +1
-1+ hwrng@1e6e2078 { compatible = "timeriomem_rng"; reg = <0x1e6e2078 0x4>; --2.13.1.611.g7e3b11ae1-goog