ARM: dts: aspeed: quanta: Enable pwm fans
Subsystems (2)
PATCH v3 1/1 ARM: dts: aspeed: quanta: Enable pwm fans
---
v3: lowercased hex address
v2: Moved pwm_tacho_fixed_clk to clocks.
--- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 51 ++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++ 2 files changed, 56 insertions(+)
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +51 -0
@@ -46,6 +46,57 @@ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; }; }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1e786000 0x1000>; + compatible = "aspeed,ast2500-pwm-tacho"; + clocks = <&pwm_tacho_fixed_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + }; }; &fmc {
arch/arm/boot/dts/aspeed-g4.dtsi +5 -0
@@ -36,6 +36,11 @@ }; clocks { + pwm_tacho_fixed_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; ahb {
Signature · 1 line
2.13.1.611.g7e3b11ae1-goog
Joel Stanley
maintainerarch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts line 52
Quoted 4 lines · Patrick Venture
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +4
-0+ + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>;
Oops, this should have been #size-cells = <0>.
This is because the child fan nodes have one cell for the address <0x??> and nothing else (no size).
I fixed this up for you and applied to dev-4.10.
Cheers,
Joel
Hi!
We want to add pwm_tacho for msn platform too.
Is there some special reason why you add pwm_tacho: pwm-tacho-controller@1e786000 to .dts not .dtsi file?
What about add this:
pwm_tacho: pwm-tacho-controller@1e786000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1e786000 0x1000>;
compatible = "aspeed,ast2500-pwm-tacho";
clocks = <&pwm_tacho_fixed_clk>;
pinctrl-names = "default";to aspeed-g5.dtsi?
And specific like pinctrl and fan:
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};to .dts file.
Thanks.
Best regards, Mykola Kostenok.
________________________________
От: openbmc <[email protected]> от имени Patrick Venture <[email protected]> Отправлено: 28 июня 2017 г. 17:23:04
Кому: [email protected]; [email protected]; [email protected]
Тема: [PATCH linux dev-4.10 v3] ARM: dts: aspeed: quanta: Enable pwm fans
---
v3: lowercased hex address
v2: Moved pwm_tacho_fixed_clk to clocks.
--- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 51 ++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++ 2 files changed, 56 insertions(+)
arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +51 -0
@@ -46,6 +46,57 @@ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; }; }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1e786000 0x1000>; + compatible = "aspeed,ast2500-pwm-tacho"; + clocks = <&pwm_tacho_fixed_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + }; }; &fmc {
arch/arm/boot/dts/aspeed-g4.dtsi +5 -0
@@ -36,6 +36,11 @@ }; clocks { + pwm_tacho_fixed_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; ahb {
--
2.13.1.611.g7e3b11ae1-goog
Quoted 20 lines · Mykola Kostenok
Hi!
We want to add
pwm_tachofor msn platform too.Is there some special reason why you add
pwm_tacho:
pwm-tacho-controller@1e786000 to .dts not .dtsi file?What about add this:
pwm_tacho: pwm-tacho-controller@1e786000 { #address-cells = <1>; #size-cells = <1>; reg = <0x1e786000 0x1000>; compatible = "aspeed,ast2500-pwm-tacho"; clocks = <&pwm_tacho_fixed_clk>; pinctrl-names = "default";
Quoted 2 lines
to
aspeed-g5.dtsi?
I believe that's completely do-able. I submitted patches for the way we had it configured here. Defining the fans in a big group with the pwm specific to the platform. But you're right, I do believe the primary details are the same across all aspeed-g4/g5 for the pwm-tacho-controller.
Quoted 119 lines
And specific like pinctrl and fan:
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default &pinctrl_pwm2_default &pinctrl_pwm3_default>; fan@0 { reg = <0x00>; aspeed,fan-tach-ch = /bits/ 8 <0x00>; };to .dts file.
Thanks.
Best regards, Mykola Kostenok.
________________________________
От: openbmc <[email protected]> от имени Patrick Venture <[email protected]>
Отправлено: 28 июня 2017 г. 17:23:04
Кому: [email protected]; [email protected]; [email protected] Тема: [PATCH linux dev-4.10 v3] ARM: dts: aspeed: quanta: Enable pwm fansSigned-off-by Patrick Venture <[email protected]>---
v3: lowercased hex address
v2: Movedpwm_tacho_fixed_clkto clocks.--- arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts | 51 ++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++ 2 files changed, 56 insertions(+)arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts +51
-0@@ -46,6 +46,57 @@ gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>; }; }; + + pwm_tacho: pwm-tacho-controller@1e786000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1e786000 0x1000>; + compatible = "aspeed,ast2500-pwm-tacho"; + clocks = <&pwm_tacho_fixed_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + }; }; &fmc {arch/arm/boot/dts/aspeed-g4.dtsi +5
-1@@ -36,6 +36,11 @@ }; clocks { + pwm_tacho_fixed_clk: fixedclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; ahb { --2.13.1.611.g7e3b11ae1-goog