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arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs

PATCH Superseded Bartosz Golaszewski 2 participants 17 messages Feb 16, 2023 – Mar 6, 2023

Subsystems (3)
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Bartosz Golaszewski

author
#0 lore raw

v3 cover arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs

From: Bartosz Golaszewski <[email protected]>

This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
board: I2C, SPI and the Bluetooth and GNSS UART ports.

v2 -> v3:
- fix the interrupt number for uart12
- replace underscores with hyphens in DT node names (although make dtbs_check does not raise warnings about this)
- rearrange the commits so that they're more fine-grained with separate patches for adding nodes to dtsi and enabling them for the board

v1 -> v2:
- uart17 is the Bluetooth port, not GNSS
- add uart12 for GNSS too in that case

Bartosz Golaszewski (9):
arm64: dts: qcom: sa8775p: add the QUPv3 #2 node
arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
arm64: dts: qcom: sa8775p: add the i2c18 node
arm64: dts: qcom: sa8775p-ride: enable i2c18
arm64: dts: qcom: sa8775p: add the spi16 node
arm64: dts: qcom: sa8775p-ride: enable the SPI node
arm64: dts: qcom: sa8775p: add high-speed UART nodes
arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
arm64: dts: qcom: sa8775p-ride: enable the BT UART port

 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 100 ++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8775p.dtsi     |  86 +++++++++++++++++++
 2 files changed, 186 insertions(+)
Signature · 1 line
2.37.2
author
#1 lore raw

PATCH v3 1/9 arm64: dts: qcom: sa8775p: add the QUPv3 #2 node

From: Bartosz Golaszewski <[email protected]>

Add the second instance of the QUPv3 engine to the sa8775p.dtsi.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +13 -0
index 565c1376073e..894c0662afb4 100644
@@ -491,6 +491,19 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
 			};
 		};
 
+		qupv3_id_2: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x8c0000 0x0 0x6000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+			clock-names = "m-ahb", "s-ahb";
+			iommus = <&apps_smmu 0x5a3 0x0>;
+			status = "disabled";
+		};
+
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
Signature · 1 line
2.37.2
author
#2 lore raw

PATCH v3 2/9 arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the second instance of the QUPv3 engine on the sa8775p-ride board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +4 -0
index 3adf7349f4e5..a538bb79c04a 100644
@@ -24,6 +24,10 @@ &qupv3_id_1 {
 	status = "okay";
 };
 
+&qupv3_id_2 {
+	status = "okay";
+};
+
 &sleep_clk {
 	clock-frequency = <32764>;
 };
Signature · 1 line
2.37.2
author
#3 lore raw

PATCH v3 3/9 arm64: dts: qcom: sa8775p: add the i2c18 node

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add a disabled node for the I2C interface that's exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +21 -0
index 894c0662afb4..4666e5341922 100644
@@ -502,6 +502,27 @@ qupv3_id_2: geniqup@8c0000 {
 			clock-names = "m-ahb", "s-ahb";
 			iommus = <&apps_smmu 0x5a3 0x0>;
 			status = "disabled";
+
+			i2c18: i2c@890000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x890000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+						 &clk_virt SLAVE_QUP_CORE_2 0>,
+						<&gem_noc MASTER_APPSS_PROC 0
+						 &config_noc SLAVE_QUP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0
+						 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
 		};
 
 		intc: interrupt-controller@17a00000 {
Signature · 1 line
2.37.2
author
#4 lore raw

PATCH v3 4/9 arm64: dts: qcom: sa8775p-ride: enable i2c18

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

This enables the I2C interface on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +15 -0
index a538bb79c04a..5fdce8279537 100644
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart10;
+		i2c18 = &i2c18;
 	};
 
 	chosen {

@@ -20,6 +21,13 @@ chosen {
 	};
 };
 
+&i2c18 {
+	clock-frequency = <400000>;
+	pinctrl-0 = <&qup_i2c18_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };

@@ -37,6 +45,13 @@ qup_uart10_default: qup-uart10-state {
 		pins = "gpio46", "gpio47";
 		function = "qup1_se3";
 	};
+
+	qup_i2c18_default: qup-i2c18-state {
+		pins = "gpio95", "gpio96";
+		function = "qup2_se4";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
 };
 
 &uart10 {
Signature · 1 line
2.37.2
Reviewed-by on v3 4/9
#5 lore raw

Re: [PATCH v3 4/9] arm64: dts: qcom: sa8775p-ride: enable i2c18

Quoted 6 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

This enables the I2C interface on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>

---

Reviewed-by Konrad Dybcio <[email protected]>

Konrad

Quoted 43 lines
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +15 -0
index a538bb79c04a..5fdce8279537 100644
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart10;
+		i2c18 = &i2c18;
 	};
 
 	chosen {

@@ -20,6 +21,13 @@ chosen {
 	};
 };
 
+&i2c18 {
+	clock-frequency = <400000>;
+	pinctrl-0 = <&qup_i2c18_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };

@@ -37,6 +45,13 @@ qup_uart10_default: qup-uart10-state {
 		pins = "gpio46", "gpio47";
 		function = "qup1_se3";
 	};
+
+	qup_i2c18_default: qup-i2c18-state {
+		pins = "gpio95", "gpio96";
+		function = "qup2_se4";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
 };
 
 &uart10 {
author
#6 lore raw

PATCH v3 5/9 arm64: dts: qcom: sa8775p: add the spi16 node

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add the SPI controller node for the interface exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +21 -0
index 4666e5341922..eda5d107961b 100644
@@ -503,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 {
 			iommus = <&apps_smmu 0x5a3 0x0>;
 			status = "disabled";
 
+			spi16: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x888000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+						 &clk_virt SLAVE_QUP_CORE_2 0>,
+						<&gem_noc MASTER_APPSS_PROC 0
+						 &config_noc SLAVE_QUP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0
+						 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
+
 			i2c18: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x890000 0x0 0x4000>;
Signature · 1 line
2.37.2
#7 lore raw

Re: [PATCH v3 5/9] arm64: dts: qcom: sa8775p: add the spi16 node

Quoted 15 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add the SPI controller node for the interface exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +0 -0
index 4666e5341922..eda5d107961b 100644

arch/arm64/boot/dts/qcom/sa8775p.dtsi qupv3_id_2: geniqup@8c0000 { · line 510

Quoted 8 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +5 -0
@@ -503,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 {
 			iommus = <&apps_smmu 0x5a3 0x0>;
 			status = "disabled";
 
+			spi16: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x888000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;

Meh, I sorta frown upon placing it here but it's been like that everywhere else.. If nobody else complains, I won't either.

arch/arm64/boot/dts/qcom/sa8775p.dtsi qupv3_id_2: geniqup@8c0000 { · line 514

Quoted 4 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +4 -0
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 0

#include <dt-bindings/interconnect/qcom,icc.h>

0 -> QCOM_ICC_TAG_ALWAYS

Konrad

Quoted 15 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +12 -0
+						 &clk_virt SLAVE_QUP_CORE_2 0>,
+						<&gem_noc MASTER_APPSS_PROC 0
+						 &config_noc SLAVE_QUP_2 0>,
+						<&aggre2_noc MASTER_QUP_2 0
+						 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
+
 			i2c18: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x890000 0x0 0x4000>;
author
#8 lore raw

PATCH v3 6/9 arm64: dts: qcom: sa8775p-ride: enable the SPI node

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the SPI interface exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +14 -0
index 5fdce8279537..d01ca3a9ee37 100644
@@ -14,6 +14,7 @@ / {
 	aliases {
 		serial0 = &uart10;
 		i2c18 = &i2c18;
+		spi16 = &spi16;
 	};
 
 	chosen {

@@ -40,12 +41,25 @@ &sleep_clk {
 	clock-frequency = <32764>;
 };
 
+&spi16 {
+	pinctrl-0 = <&qup_spi16_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &tlmm {
 	qup_uart10_default: qup-uart10-state {
 		pins = "gpio46", "gpio47";
 		function = "qup1_se3";
 	};
 
+	qup_spi16_default: qup-spi16-state {
+		pins = "gpio86", "gpio87", "gpio88", "gpio89";
+		function = "qup2_se2";
+		drive-strength = <6>;
+		bias-disable;
+	};
+
 	qup_i2c18_default: qup-i2c18-state {
 		pins = "gpio95", "gpio96";
 		function = "qup2_se4";
Signature · 1 line
2.37.2
Reviewed-by on v3 6/9
#9 lore raw

Re: [PATCH v3 6/9] arm64: dts: qcom: sa8775p-ride: enable the SPI node

Quoted 6 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the SPI interface exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>

---

Reviewed-by Konrad Dybcio <[email protected]>

Konrad

Quoted 41 lines
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +14 -0
index 5fdce8279537..d01ca3a9ee37 100644
@@ -14,6 +14,7 @@ / {
 	aliases {
 		serial0 = &uart10;
 		i2c18 = &i2c18;
+		spi16 = &spi16;
 	};
 
 	chosen {

@@ -40,12 +41,25 @@ &sleep_clk {
 	clock-frequency = <32764>;
 };
 
+&spi16 {
+	pinctrl-0 = <&qup_spi16_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &tlmm {
 	qup_uart10_default: qup-uart10-state {
 		pins = "gpio46", "gpio47";
 		function = "qup1_se3";
 	};
 
+	qup_spi16_default: qup-spi16-state {
+		pins = "gpio86", "gpio87", "gpio88", "gpio89";
+		function = "qup2_se2";
+		drive-strength = <6>;
+		bias-disable;
+	};
+
 	qup_i2c18_default: qup-i2c18-state {
 		pins = "gpio95", "gpio96";
 		function = "qup2_se4";
author
#10 lore raw

PATCH v3 7/9 arm64: dts: qcom: sa8775p: add high-speed UART nodes

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add two UART nodes that are known to be used by existing development boards with this SoC.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 31 +++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +31 -0
index eda5d107961b..ce5976e36aee 100644
@@ -489,6 +489,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
 				operating-points-v2 = <&qup_opp_table_100mhz>;
 				status = "disabled";
 			};
+
+			uart12: serial@a94000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa94000 0x0 0x4000>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0
+						 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0
+						 &config_noc SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
 		};
 
 		qupv3_id_2: geniqup@8c0000 {

@@ -524,6 +539,22 @@ &config_noc SLAVE_QUP_2 0>,
 				status = "disabled";
 			};
 
+			uart17: serial@88c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x88c000 0x0 0x4000>;
+				interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+						      <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+						 &clk_virt SLAVE_QUP_CORE_2 0>,
+						<&gem_noc MASTER_APPSS_PROC 0
+						 &config_noc SLAVE_QUP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
+
 			i2c18: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x890000 0x0 0x4000>;
Signature · 1 line
2.37.2
#11 lore raw

Re: [PATCH v3 7/9] arm64: dts: qcom: sa8775p: add high-speed UART nodes

Quoted 15 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add two UART nodes that are known to be used by existing development boards with this SoC.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 31 +++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +0 -0
index eda5d107961b..ce5976e36aee 100644

arch/arm64/boot/dts/qcom/sa8775p.dtsi &clk_virt SLAVE_QUP_CORE_1 0>, · line 495

Quoted 7 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +4 -0
@@ -489,6 +489,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
 				operating-points-v2 = <&qup_opp_table_100mhz>;
 				status = "disabled";
 			};
+
+			uart12: serial@a94000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa94000 0x0 0x4000>;

The address part ought to be padded to 8 hex digits

arch/arm64/boot/dts/qcom/sa8775p.dtsi &clk_virt SLAVE_QUP_CORE_1 0>, · line 499

Quoted 4 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +4 -0
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0

Please use the bindings constants as pointed out in the previous replies.

Quoted 11 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +7 -0
+						 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0
+						 &config_noc SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
 		};
 
 		qupv3_id_2: geniqup@8c0000 {

arch/arm64/boot/dts/qcom/sa8775p.dtsi &config_noc SLAVE_QUP_2 0>, · line 544

Quoted 6 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +3 -0
@@ -524,6 +539,22 @@ &config_noc SLAVE_QUP_2 0>,
 				status = "disabled";
 			};
 
+			uart17: serial@88c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x88c000 0x0 0x4000>;

Ditto

arch/arm64/boot/dts/qcom/sa8775p.dtsi &config_noc SLAVE_QUP_2 0>, · line 550

Quoted 6 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +6 -0
+				interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+						      <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+						 &clk_virt SLAVE_QUP_CORE_2 0>,

Ditto

Konrad

Quoted 10 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +7 -0
+						<&gem_noc MASTER_APPSS_PROC 0
+						 &config_noc SLAVE_QUP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
+
 			i2c18: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x890000 0x0 0x4000>;
author
#12 lore raw

PATCH v3 8/9 arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
 1 file changed, 34 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +34 -0
index d01ca3a9ee37..6f96907b335c 100644
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart10;
+		serial1 = &uart12;
 		i2c18 = &i2c18;
 		spi16 = &spi16;
 	};

@@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
 		drive-strength = <2>;
 		bias-pull-up;
 	};
+
+	qup_uart12_cts: qup-uart12-cts-state {
+		pins = "gpio52";
+		function = "qup1_se5";
+		bias-disable;
+	};
+
+	qup_uart12_rts: qup-uart12-rts-state {
+		pins = "gpio53";
+		function = "qup1_se5";
+		bias-pull-down;
+	};
+
+	qup_uart12_tx: qup-uart12-tx-state {
+		pins = "gpio54";
+		function = "qup1_se5";
+		bias-pull-up;
+	};
+
+	qup_uart12_rx: qup-uart12-rx-state {
+		pins = "gpio55";
+		function = "qup1_se5";
+		bias-pull-down;
+	};
 };
 
 &uart10 {

@@ -75,6 +100,15 @@ &uart10 {
 	status = "okay";
 };
 
+&uart12 {
+	pinctrl-0 = <&qup_uart12_cts>,
+		    <&qup_uart12_rts>,
+		    <&qup_uart12_tx>,
+		    <&qup_uart12_rx>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
Signature · 1 line
2.37.2
#13 lore raw

Re: [PATCH v3 8/9] arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port

Quoted 23 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
 1 file changed, 34 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +1 -0
index d01ca3a9ee37..6f96907b335c 100644
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart10;
+		serial1 = &uart12;
 		i2c18 = &i2c18;
 		spi16 = &spi16;
 	};

arch/arm64/boot/dts/qcom/sa8775p-ride.dts qup_i2c18_default: qup-i2c18-state { · line 70

Quoted 4 lines
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +1 -0
@@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
 		drive-strength = <2>;
 		bias-pull-up;
 	};
+

qup_uart12_default: [...] {
    qup_uart12_cts: [...]
};

[...]

pinctrl-0 = <&qup_uart12_default>;

?

Konrad

Quoted 42 lines
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +32 -0
+	qup_uart12_cts: qup-uart12-cts-state {
+		pins = "gpio52";
+		function = "qup1_se5";
+		bias-disable;
+	};
+
+	qup_uart12_rts: qup-uart12-rts-state {
+		pins = "gpio53";
+		function = "qup1_se5";
+		bias-pull-down;
+	};
+
+	qup_uart12_tx: qup-uart12-tx-state {
+		pins = "gpio54";
+		function = "qup1_se5";
+		bias-pull-up;
+	};
+
+	qup_uart12_rx: qup-uart12-rx-state {
+		pins = "gpio55";
+		function = "qup1_se5";
+		bias-pull-down;
+	};
 };
 
 &uart10 {

@@ -75,6 +100,15 @@ &uart10 {
 	status = "okay";
 };
 
+&uart12 {
+	pinctrl-0 = <&qup_uart12_cts>,
+		    <&qup_uart12_rts>,
+		    <&qup_uart12_tx>,
+		    <&qup_uart12_rx>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
author
#14 lore raw

PATCH v3 9/9 arm64: dts: qcom: sa8775p-ride: enable the BT UART port

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the high-speed UART port connected to the Bluetooth controller on the sa8775p-adp development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +33 -0
index 6f96907b335c..1de3b9d4a05a 100644
@@ -14,6 +14,7 @@ / {
 	aliases {
 		serial0 = &uart10;
 		serial1 = &uart12;
+		serial2 = &uart17;
 		i2c18 = &i2c18;
 		spi16 = &spi16;
 	};

@@ -89,6 +90,29 @@ qup_uart12_tx: qup-uart12-tx-state {
 	qup_uart12_rx: qup-uart12-rx-state {
 		pins = "gpio55";
 		function = "qup1_se5";
+	};
+
+	qup_uart17_cts: qup-uart17-cts-state {
+		pins = "gpio91";
+		function = "qup2_se3";
+		bias-disable;
+	};
+
+	qup_uart17_rts: qup0-uart17-rts-state {
+		pins = "gpio92";
+		function = "qup2_se3";
+		bias-pull-down;
+	};
+
+	qup_uart17_tx: qup0-uart17-tx-state {
+		pins = "gpio93";
+		function = "qup2_se3";
+		bias-pull-up;
+	};
+
+	qup_uart17_rx: qup0-uart17-rx-state {
+		pins = "gpio94";
+		function = "qup2_se3";
 		bias-pull-down;
 	};
 };

@@ -109,6 +133,15 @@ &uart12 {
 	status = "okay";
 };
 
+&uart17 {
+	pinctrl-0 = <&qup_uart17_cts>,
+		    <&qup_uart17_rts>,
+		    <&qup_uart17_tx>,
+		    <&qup_uart17_rx>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
Signature · 1 line
2.37.2
#15 lore raw

Re: [PATCH v3 9/9] arm64: dts: qcom: sa8775p-ride: enable the BT UART port

Quoted 7 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the high-speed UART port connected to the Bluetooth controller on the sa8775p-adp development board.

Signed-off-by Bartosz Golaszewski <[email protected]>

---

Same comments as in the previous patch.

Konrad

Quoted 61 lines
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +33 -0
index 6f96907b335c..1de3b9d4a05a 100644
@@ -14,6 +14,7 @@ / {
 	aliases {
 		serial0 = &uart10;
 		serial1 = &uart12;
+		serial2 = &uart17;
 		i2c18 = &i2c18;
 		spi16 = &spi16;
 	};

@@ -89,6 +90,29 @@ qup_uart12_tx: qup-uart12-tx-state {
 	qup_uart12_rx: qup-uart12-rx-state {
 		pins = "gpio55";
 		function = "qup1_se5";
+	};
+
+	qup_uart17_cts: qup-uart17-cts-state {
+		pins = "gpio91";
+		function = "qup2_se3";
+		bias-disable;
+	};
+
+	qup_uart17_rts: qup0-uart17-rts-state {
+		pins = "gpio92";
+		function = "qup2_se3";
+		bias-pull-down;
+	};
+
+	qup_uart17_tx: qup0-uart17-tx-state {
+		pins = "gpio93";
+		function = "qup2_se3";
+		bias-pull-up;
+	};
+
+	qup_uart17_rx: qup0-uart17-rx-state {
+		pins = "gpio94";
+		function = "qup2_se3";
 		bias-pull-down;
 	};
 };

@@ -109,6 +133,15 @@ &uart12 {
 	status = "okay";
 };
 
+&uart17 {
+	pinctrl-0 = <&qup_uart17_cts>,
+		    <&qup_uart17_rts>,
+		    <&qup_uart17_tx>,
+		    <&qup_uart17_rx>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
author
#16 lore raw
In reply to Bartosz Golaszewski
Quoted 28 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
board: I2C, SPI and the Bluetooth and GNSS UART ports.

v2 -> v3:
- fix the interrupt number for uart12
- replace underscores with hyphens in DT node names (although make dtbs_check does not raise warnings about this)
- rearrange the commits so that they're more fine-grained with separate patches for adding nodes to dtsi and enabling them for the board

v1 -> v2:
- uart17 is the Bluetooth port, not GNSS
- add uart12 for GNSS too in that case

Bartosz Golaszewski (9):
arm64: dts: qcom: sa8775p: add the QUPv3 #2 node
arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
arm64: dts: qcom: sa8775p: add the i2c18 node
arm64: dts: qcom: sa8775p-ride: enable i2c18
arm64: dts: qcom: sa8775p: add the spi16 node
arm64: dts: qcom: sa8775p-ride: enable the SPI node
arm64: dts: qcom: sa8775p: add high-speed UART nodes
arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
arm64: dts: qcom: sa8775p-ride: enable the BT UART port

Quoted 7 lines
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 100 ++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8775p.dtsi     |  86 +++++++++++++++++++
 2 files changed, 186 insertions(+)

--
2.37.2

Konrad, Krzysztof et al,

It's been over two weeks, could you please take a look and let me know if this is good to go?

Thanks,
Bartosz