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arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs

PATCH Applied Bartosz Golaszewski 2 participants 12 messages Mar 9, 2023 – Mar 22, 2023

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Bartosz Golaszewski

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#0 lore raw

v5 cover arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs

From: Bartosz Golaszewski <[email protected]>

This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
board: I2C, SPI and the Bluetooth and GNSS UART ports.

v4 -> v5:
- remove board-specific interrupt from UART17 in SoC dtsi
- rearrange node properties to have various *-cells properties come right before status
- collect more tags

v3 -> v4:
- use interconnect constants instead of magic numbers where applicable
- pad addresses in reg to 8 digits
- group pins under state nodes for UART

v2 -> v3:
- fix the interrupt number for uart12
- replace underscores with hyphens in DT node names (although make dtbs_check does not raise warnings about this)
- rearrange the commits so that they're more fine-grained with separate patches for adding nodes to dtsi and enabling them for the board

v1 -> v2:
- uart17 is the Bluetooth port, not GNSS
- add uart12 for GNSS too in that case

Bartosz Golaszewski (9):
arm64: dts: qcom: sa8775p: add the QUPv3 #2 node
arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
arm64: dts: qcom: sa8775p: add the i2c18 node
arm64: dts: qcom: sa8775p-ride: enable i2c18
arm64: dts: qcom: sa8775p: add the spi16 node
arm64: dts: qcom: sa8775p-ride: enable the SPI node
arm64: dts: qcom: sa8775p: add high-speed UART nodes
arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
arm64: dts: qcom: sa8775p-ride: enable the BT UART port

 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 99 +++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 86 ++++++++++++++++++++
 2 files changed, 185 insertions(+)
Signature · 1 line
2.37.2
author
#1 lore raw

PATCH v5 1/9 arm64: dts: qcom: sa8775p: add the QUPv3 #2 node

From: Bartosz Golaszewski <[email protected]>

Add the second instance of the QUPv3 engine to the sa8775p.dtsi.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +13 -0
index 565c1376073e..9e30c1e3e66a 100644
@@ -491,6 +491,19 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
 			};
 		};
 
+		qupv3_id_2: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x008c0000 0x0 0x6000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+			clock-names = "m-ahb", "s-ahb";
+			iommus = <&apps_smmu 0x5a3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+		};
+
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
Signature · 1 line
2.37.2
author
#2 lore raw

PATCH v5 2/9 arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the second instance of the QUPv3 engine on the sa8775p-ride board.

Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +4 -0
index 3adf7349f4e5..a538bb79c04a 100644
@@ -24,6 +24,10 @@ &qupv3_id_1 {
 	status = "okay";
 };
 
+&qupv3_id_2 {
+	status = "okay";
+};
+
 &sleep_clk {
 	clock-frequency = <32764>;
 };
Signature · 1 line
2.37.2
author
#3 lore raw

PATCH v5 3/9 arm64: dts: qcom: sa8775p: add the i2c18 node

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add a disabled node for the I2C interface that's exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +22 -0
index 9e30c1e3e66a..e7ed309fc04f 100644
@@ -3,6 +3,7 @@
  * Copyright (c) 2023, Linaro Limited
  */
 
+#include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>

@@ -502,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
+
+			i2c18: i2c@890000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		intc: interrupt-controller@17a00000 {
Signature · 1 line
2.37.2
author
#4 lore raw

PATCH v5 4/9 arm64: dts: qcom: sa8775p-ride: enable i2c18

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

This enables the I2C interface on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +15 -0
index a538bb79c04a..5fdce8279537 100644
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart10;
+		i2c18 = &i2c18;
 	};
 
 	chosen {

@@ -20,6 +21,13 @@ chosen {
 	};
 };
 
+&i2c18 {
+	clock-frequency = <400000>;
+	pinctrl-0 = <&qup_i2c18_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };

@@ -37,6 +45,13 @@ qup_uart10_default: qup-uart10-state {
 		pins = "gpio46", "gpio47";
 		function = "qup1_se3";
 	};
+
+	qup_i2c18_default: qup-i2c18-state {
+		pins = "gpio95", "gpio96";
+		function = "qup2_se4";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
 };
 
 &uart10 {
Signature · 1 line
2.37.2
author
#5 lore raw

PATCH v5 5/9 arm64: dts: qcom: sa8775p: add the spi16 node

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add the SPI controller node for the interface exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +21 -0
index e7ed309fc04f..d1b2a6d30eae 100644
@@ -504,6 +504,27 @@ qupv3_id_2: geniqup@8c0000 {
 			#size-cells = <2>;
 			status = "disabled";
 
+			spi16: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			i2c18: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x00890000 0x0 0x4000>;
Signature · 1 line
2.37.2
author
#6 lore raw

PATCH v5 6/9 arm64: dts: qcom: sa8775p-ride: enable the SPI node

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the SPI interface exposed on the sa8775p-ride development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +14 -0
index 5fdce8279537..d01ca3a9ee37 100644
@@ -14,6 +14,7 @@ / {
 	aliases {
 		serial0 = &uart10;
 		i2c18 = &i2c18;
+		spi16 = &spi16;
 	};
 
 	chosen {

@@ -40,12 +41,25 @@ &sleep_clk {
 	clock-frequency = <32764>;
 };
 
+&spi16 {
+	pinctrl-0 = <&qup_spi16_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &tlmm {
 	qup_uart10_default: qup-uart10-state {
 		pins = "gpio46", "gpio47";
 		function = "qup1_se3";
 	};
 
+	qup_spi16_default: qup-spi16-state {
+		pins = "gpio86", "gpio87", "gpio88", "gpio89";
+		function = "qup2_se2";
+		drive-strength = <6>;
+		bias-disable;
+	};
+
 	qup_i2c18_default: qup-i2c18-state {
 		pins = "gpio95", "gpio96";
 		function = "qup2_se4";
Signature · 1 line
2.37.2
author
#7 lore raw

PATCH v5 7/9 arm64: dts: qcom: sa8775p: add high-speed UART nodes

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Add two UART nodes that are known to be used by existing development boards with this SoC.

Signed-off-by Bartosz Golaszewski <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 30 +++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +30 -0
index d1b2a6d30eae..468390edf049 100644
@@ -490,6 +490,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
 				operating-points-v2 = <&qup_opp_table_100mhz>;
 				status = "disabled";
 			};
+
+			uart12: serial@a94000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
 		};
 
 		qupv3_id_2: geniqup@8c0000 {

@@ -525,6 +540,21 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 				status = "disabled";
 			};
 
+			uart17: serial@88c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x0088c000 0x0 0x4000>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config";
+				power-domains = <&rpmhpd SA8775P_CX>;
+				status = "disabled";
+			};
+
 			i2c18: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0x0 0x00890000 0x0 0x4000>;
Signature · 1 line
2.37.2
author
#8 lore raw

PATCH v5 8/9 arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +33 -0
index d01ca3a9ee37..cba7c8116141 100644
@@ -13,6 +13,7 @@ / {
 
 	aliases {
 		serial0 = &uart10;
+		serial1 = &uart12;
 		i2c18 = &i2c18;
 		spi16 = &spi16;
 	};

@@ -66,6 +67,32 @@ qup_i2c18_default: qup-i2c18-state {
 		drive-strength = <2>;
 		bias-pull-up;
 	};
+
+	qup_uart12_default: qup-uart12-state {
+		qup_uart12_cts: qup-uart12-cts-pins {
+			pins = "gpio52";
+			function = "qup1_se5";
+			bias-disable;
+		};
+
+		qup_uart12_rts: qup-uart12-rts-pins {
+			pins = "gpio53";
+			function = "qup1_se5";
+			bias-pull-down;
+		};
+
+		qup_uart12_tx: qup-uart12-tx-pins {
+			pins = "gpio54";
+			function = "qup1_se5";
+			bias-pull-up;
+		};
+
+		qup_uart12_rx: qup-uart12-rx-pins {
+			pins = "gpio55";
+			function = "qup1_se5";
+			bias-pull-down;
+		};
+	};
 };
 
 &uart10 {

@@ -75,6 +102,12 @@ &uart10 {
 	status = "okay";
 };
 
+&uart12 {
+	pinctrl-0 = <&qup_uart12_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
Signature · 1 line
2.37.2
author
#9 lore raw

PATCH v5 9/9 arm64: dts: qcom: sa8775p-ride: enable the BT UART port

In reply to Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

Enable the high-speed UART port connected to the Bluetooth controller on the sa8775p-adp development board.

Signed-off-by Bartosz Golaszewski <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
---
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +33 -0
index cba7c8116141..1020dfd21da2 100644
@@ -14,6 +14,7 @@ / {
 	aliases {
 		serial0 = &uart10;
 		serial1 = &uart12;
+		serial2 = &uart17;
 		i2c18 = &i2c18;
 		spi16 = &spi16;
 	};

@@ -93,6 +94,32 @@ qup_uart12_rx: qup-uart12-rx-pins {
 			bias-pull-down;
 		};
 	};
+
+	qup_uart17_default: qup-uart17-state {
+		qup_uart17_cts: qup-uart17-cts-pins {
+			pins = "gpio91";
+			function = "qup2_se3";
+			bias-disable;
+		};
+
+		qup_uart17_rts: qup0-uart17-rts-pins {
+			pins = "gpio92";
+			function = "qup2_se3";
+			bias-pull-down;
+		};
+
+		qup_uart17_tx: qup0-uart17-tx-pins {
+			pins = "gpio93";
+			function = "qup2_se3";
+			bias-pull-up;
+		};
+
+		qup_uart17_rx: qup0-uart17-rx-pins {
+			pins = "gpio94";
+			function = "qup2_se3";
+			bias-pull-down;
+		};
+	};
 };
 
 &uart10 {

@@ -108,6 +135,12 @@ &uart12 {
 	status = "okay";
 };
 
+&uart17 {
+	pinctrl-0 = <&qup_uart17_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-frequency = <38400000>;
 };
Signature · 1 line
2.37.2
author
#10 lore raw
In reply to Bartosz Golaszewski
Quoted 39 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
board: I2C, SPI and the Bluetooth and GNSS UART ports.

v4 -> v5:
- remove board-specific interrupt from UART17 in SoC dtsi
- rearrange node properties to have various *-cells properties come right before status
- collect more tags

v3 -> v4:
- use interconnect constants instead of magic numbers where applicable
- pad addresses in reg to 8 digits
- group pins under state nodes for UART

v2 -> v3:
- fix the interrupt number for uart12
- replace underscores with hyphens in DT node names (although make dtbs_check does not raise warnings about this)
- rearrange the commits so that they're more fine-grained with separate patches for adding nodes to dtsi and enabling them for the board

v1 -> v2:
- uart17 is the Bluetooth port, not GNSS
- add uart12 for GNSS too in that case

Bartosz Golaszewski (9):
arm64: dts: qcom: sa8775p: add the QUPv3 #2 node
arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
arm64: dts: qcom: sa8775p: add the i2c18 node
arm64: dts: qcom: sa8775p-ride: enable i2c18
arm64: dts: qcom: sa8775p: add the spi16 node
arm64: dts: qcom: sa8775p-ride: enable the SPI node
arm64: dts: qcom: sa8775p: add high-speed UART nodes
arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
arm64: dts: qcom: sa8775p-ride: enable the BT UART port

Quoted 7 lines
 arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 99 +++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 86 ++++++++++++++++++++
 2 files changed, 185 insertions(+)

--
2.37.2

Bjorn,

I noticed you're picking up the reviewed patches. :) This series seems ready to go into your tree as well.

Thanks in advance,
Bartosz

maintainer Applied
#11 lore raw
In reply to Bartosz Golaszewski
Quoted 5 lines · Bartosz Golaszewski

From: Bartosz Golaszewski <[email protected]>

This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
board: I2C, SPI and the Bluetooth and GNSS UART ports.

Quoted 7 lines

v4 -> v5:
- remove board-specific interrupt from UART17 in SoC dtsi
- rearrange node properties to have various *-cells properties come right before status
- collect more tags

[...]

Applied, thanks!

[1/9] arm64: dts: qcom: sa8775p: add the QUPv3 #2 node

      commit: dc3ad22112de7fe76352ef2aa2943b62eb1836a3
[2/9] arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
      commit: 4926a8e93f321760fa265f91d78aa2a2163e222b
[3/9] arm64: dts: qcom: sa8775p: add the i2c18 node
      commit: a23d122572a4ad1292e60d4a87e6f0238aaa0505
[4/9] arm64: dts: qcom: sa8775p-ride: enable i2c18
      commit: 12f35f74ad6da53d94fcbc1bbb2adff60b31a71f
[5/9] arm64: dts: qcom: sa8775p: add the spi16 node
      commit: cfd975f588400e0942d55dc4bb84c12c6f217fb4
[6/9] arm64: dts: qcom: sa8775p-ride: enable the SPI node
      commit: a3b31b0e0f76326bfa4bc81577f52738ad8e072b
[7/9] arm64: dts: qcom: sa8775p: add high-speed UART nodes
      commit: 41ae5ca448c21a82a2f07e10954b043a0d45a811
[8/9] arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
      commit: 4b6c4249069694a593f3b4c3d81c75a5053b7693
[9/9] arm64: dts: qcom: sa8775p-ride: enable the BT UART port
      commit: e1988af7a646aafe8075b179c00fd8053ced2add

Best regards,

Signature · 1 line
Bjorn Andersson <[email protected]>