arm64: dts: qcom: sm8150: Add standalone ICE node for UFS
Subsystems (8)
v2 cover arm64: dts: qcom: sm8150: Add standalone ICE node for UFS
Hi everyone,
This small series brings the Qualcomm Inline Crypto Engine (ICE) to the SM8150 (Snapdragon 855) platform, following the same standalone-node style already used on SM8250 and newer SoCs.
The first patch documents the new qcom,sm8150-inline-crypto-engine compatible and moves qcom,sm8150-ufshc to the standalone-ICE UFS binding. The second patch converts the UFS node to reference a dedicated ICE node instead of embedding the registers directly.
I've tested this on a Google Pixel 4 (google-flame) and everything works:/sys/block/sda/queue/crypto now advertises AES-256-XTS and ext4 reports encryption as "supported". The ICE self-test completes cleanly during boot.
Happy to adjust anything or add more details if needed. Thanks for reviewing!
Changes in v2:
- Move qcom,sm8150-ufshc from the legacy embedded-ICE UFS binding to
the standalone-ICE UFS binding.
- Keep the SM8150 ICE compatible sorted in the existing list.
- Link to v1: https://patch.msgid.link/[email protected]
---
Andrew Gigena (2):
dt-bindings: crypto: ice: Document sm8150 inline crypto engine
arm64: dts: qcom: sm8150: Use standalone ICE node for UFS
.../bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + .../devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++ .../devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++------ arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 ++++++++++++++-------- 4 files changed, 23 insertions(+), 16 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261104-sm8150-ice-rfc-0b4b2c035e80
Best regards,
Signature · 1 line
Andrew Gigena <[email protected]>
PATCH v2 1/2 dt-bindings: crypto: ice: Document sm8150 inline crypto engine
Document the compatible used for the inline crypto engine found on SM8150.
SM8150 UFS uses a standalone ICE node referenced via qcom,ice, so move qcom,sm8150-ufshc from the legacy embedded-ICE UFS binding to the standalone-ICE UFS binding. Update the legacy binding example to use qcom,sdm845-ufshc, which still uses the embedded ICE representation.
--- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++ Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++------- 3 files changed, 7 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +1 -0
@@ -24,6 +24,7 @@ properties: - qcom,sc7180-inline-crypto-engine - qcom,sc7280-inline-crypto-engine - qcom,shikra-inline-crypto-engine + - qcom,sm8150-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml +2 -0
@@ -23,6 +23,7 @@ select: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc + - qcom,sm8150-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc
@@ -48,6 +49,7 @@ properties: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc + - qcom,sm8150-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +4 -7
@@ -23,7 +23,6 @@ select: - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - - qcom,sm8150-ufshc required: - compatible
@@ -38,7 +37,6 @@ properties: - qcom,sm6115-ufshc - qcom,sm6125-ufshc - qcom,sm6350-ufshc - - qcom,sm8150-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0
@@ -69,7 +67,6 @@ allOf: enum: - qcom,sdm845-ufshc - qcom,sm6350-ufshc - - qcom,sm8150-ufshc then: properties: clocks:
@@ -175,10 +172,10 @@ unevaluatedProperties: false examples: - | - #include <dt-bindings/clock/qcom,gcc-sm8150.h> + #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interconnect/qcom,sm8150.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> soc {
@@ -186,7 +183,7 @@ examples: #size-cells = <2>; ufs@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", + compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x2500>, <0x0 0x01d90000 0x0 0x8000>;
@@ -207,7 +204,7 @@ examples: vccq-max-microamp = <1200000>; power-domains = <&gcc UFS_PHY_GDSC>; - iommus = <&apps_smmu 0x300 0>; + iommus = <&apps_smmu 0x100 0xf>; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
Signature · 1 line
2.56.0
PATCH v2 2/2 arm64: dts: qcom: sm8150: Use standalone ICE node for UFS
In reply to Andrew GigenaConvert SM8150 UFS to use a standalone ICE node.
Move the ICE register region and clock from the UFS controller node into a dedicated ICE node. Reference the new node from the UFS controller using the qcom,ice property.
This brings the SM8150 device tree in line with the standalone ICE representation used on newer Qualcomm platforms.
--- arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-)
arch/arm64/boot/dts/qcom/sm8150.dtsi +16 -9
@@ -2071,9 +2071,7 @@ pcie1_phy: phy@1c0e000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x2500>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy>; phy-names = "ufsphy";
@@ -2092,8 +2090,7 @@ ufs_mem_hc: ufshc@1d84000 { "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -2102,8 +2099,7 @@ ufs_mem_hc: ufshc@1d84000 { <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <37500000 300000000>, <0 0>,
@@ -2112,8 +2108,8 @@ ufs_mem_hc: ufshc@1d84000 { <0 0>, <0 0>, <0 0>, - <0 0>, - <0 300000000>; + <0 0>; + qcom,ice = <&ice>; status = "disabled"; };
@@ -2139,6 +2135,17 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + ice: crypto@1d90000 { + compatible = "qcom,sm8150-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d90000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>;
Signature · 1 line
2.56.0
Re: [PATCH v2 2/2] arm64: dts: qcom: sm8150: Use standalone ICE node for UFS
Quoted 11 lines · Andrew Gigena
Convert SM8150 UFS to use a standalone ICE node.
Move the ICE register region and clock from the UFS controller node into a dedicated ICE node. Reference the new node from the UFS controller using the qcom,ice property.
This brings the SM8150 device tree in line with the standalone ICE representation used on newer Qualcomm platforms.
Signed-off-by Andrew Gigena <[email protected]>Tested-by Andrew Gigena <[email protected]>
Tested-by tag should come from someone else, other than the author.
Authors are expected to test their patches by default.
Re: [PATCH v2 2/2] arm64: dts: qcom: sm8150: Use standalone ICE node for UFS
I understand, I'll keep that in mind for future patches. Should I release patch v3 removing the "Tested-By" now, or wait for other reviews?
Quoted 18 lines · Abel Vesa
Quoted 11 lines · Andrew Gigena
Convert SM8150 UFS to use a standalone ICE node.
Move the ICE register region and clock from the UFS controller node into a dedicated ICE node. Reference the new node from the UFS controller using the qcom,ice property.
This brings the SM8150 device tree in line with the standalone ICE representation used on newer Qualcomm platforms.
Signed-off-by Andrew Gigena <[email protected]>Tested-by Andrew Gigena <[email protected]>Tested-by tag should come from someone else, other than the author.
Authors are expected to test their patches by default.
Re: [PATCH v2 1/2] dt-bindings: crypto: ice: Document sm8150 inline crypto engine
In reply to Andrew GigenaQuoted 8 lines · Andrew Gigena
Document the compatible used for the inline crypto engine found on SM8150.
SM8150 UFS uses a standalone ICE node referenced via qcom,ice, so move qcom,sm8150-ufshc from the legacy embedded-ICE UFS binding to the standalone-ICE UFS binding. Update the legacy binding example to use qcom,sdm845-ufshc, which still uses the embedded ICE representation.
This part should be a separate commit.
Quoted 32 lines
Signed-off-by Andrew Gigena <[email protected]>--- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml | 2 ++ Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 11 ++++------- 3 files changed, 7 insertions(+), 7 deletions(-)Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +1
-0@@ -24,6 +24,7 @@ properties: - qcom,sc7180-inline-crypto-engine - qcom,sc7280-inline-crypto-engine - qcom,shikra-inline-crypto-engine + - qcom,sm8150-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engineDocumentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml +1
-0@@ -23,6 +23,7 @@ select: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc + - qcom,sm8150-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc - qcom,sm8450-ufshc
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml properties: · line 51
Quoted 3 lines
Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml +0
-0@@ -48,6 +49,7 @@ properties: - qcom,sc7280-ufshc - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc
And what about eight clock? All existing DTS will report warning? I don't quite get the need of this move.
Best regards,
Krzysztof
Re: [PATCH v2 2/2] arm64: dts: qcom: sm8150: Use standalone ICE node for UFS
In reply to Andrew GigenaQuoted 3 lines · Andrew Gigena
I understand, I'll keep that in mind for future patches. Should I release patch v3 removing the "Tested-By" now, or wait for other reviews?
OK, now you are top-posting.
Please read through this:
You can send v3 now.
Re: [PATCH v2 1/2] dt-bindings: crypto: ice: Document sm8150 inline crypto engine
In reply to Krzysztof KozlowskiQuoted 1 line
This part should be a separate commit.
I splitted it into two commits in v3:
1. Add qcom,sm8150-inline-crypto-engine compatible.
2. Move qcom,sm8150-ufshc to the standalone-ICE UFS binding.
Quoted 2 lines
And what about eight clock? All existing DTS will report warning? I don't quite get the need of this move.
After the move, SM8150 UFS no longer provides the ICE register region or ice_core_clk; those live in the standalone ICE node. The only in-tree user of qcom,sm8150-ufshc is arch/arm64/boot/dts/qcom/sm8150.dtsi, which is converted in the DTS patch, so there are no leftover users of the embedded-ICE binding for this compatible and no schema warnings.
Re: [PATCH v2 1/2] dt-bindings: crypto: ice: Document sm8150 inline crypto engine
Quoted 6 lines · Andrew Gigena
Quoted 1 line
This part should be a separate commit.
I splitted it into two commits in v3:
1. Add qcom,sm8150-inline-crypto-engine compatible.
2. Move qcom,sm8150-ufshc to the standalone-ICE UFS binding.
No clue what's this about, you completely cut context.
Quoted 6 lines
Quoted 2 lines
And what about eight clock? All existing DTS will report warning? I don't quite get the need of this move.
After the move, SM8150 UFS no longer provides the ICE register region or
ice_core_clk; those live in the standalone ICE node. The only in-tree user of qcom,sm8150-ufshc isarch/arm64/boot/dts/qcom/sm8150.dtsi, which
So you introduce the warning at this point?
Quoted 2 lines
is converted in the DTS patch, so there are no leftover users of the embedded-ICE binding for this compatible and no schema warnings.
Best regards,
Krzysztof