add support for mcf5307

Add support for mcf5307 cpu.

---

Changes for v4:
- all previous patches was wrong, some files was missing, for an improper usage of git.

  arch/m68k/cpu/mcf530x/Makefile     |   48 +++++++
  arch/m68k/cpu/mcf530x/config.mk    |   25 ++++
  arch/m68k/cpu/mcf530x/cpu.c        |   48 +++++++
  arch/m68k/cpu/mcf530x/cpu.h        |   33 +++++
  arch/m68k/cpu/mcf530x/cpu_init.c   |  162 +++++++++++++++++++++++
  arch/m68k/cpu/mcf530x/interrupts.c |   42 ++++++
  arch/m68k/cpu/mcf530x/speed.c      |   36 +++++
  arch/m68k/cpu/mcf530x/start.S      |  253 
++++++++++++++++++++++++++++++++++++
  arch/m68k/include/asm/cache.h      |    2 +-
  arch/m68k/include/asm/immap.h      |   22 +++
  arch/m68k/include/asm/immap_5307.h |   78 +++++++++++
  arch/m68k/include/asm/m5307.h      |  124 ++++++++++++++++++
  arch/m68k/include/asm/timer.h      |    2 +-
  include/common.h                   |    6 +-
  14 files changed, 876 insertions(+), 5 deletions(-)

new file mode 100644
index 0000000..3c5a1c2
@@ -0,0 +1,48 @@
+#
+# Copyright (c) 2011 Angelo Dureghello <[email protected]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# CFLAGS += -DET_DEBUG
+
+LIB    = $(obj)lib$(CPU).o
+
+START    = start.o
+COBJS    = interrupts.o cpu.o speed.o cpu_init.o
+
+SRCS    := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START    := $(addprefix $(obj),$(START))
+
+all:    $(obj).depend $(START) $(LIB)
+
+$(LIB):    $(OBJS)
+    $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

b/arch/m68k/cpu/mcf530x/config.mk
new file mode 100644
index 0000000..2ba1644

@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2011 Angelo Dureghello <[email protected]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+PLATFORM_CPPFLAGS += -m5307 -fPIC

new file mode 100644
index 0000000..c1227eb
@@ -0,0 +1,33 @@
+/*
+ *  cpu.h
+ *
+ *  Copyright (c) 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+/* Use this to create board specific reset functions */
+void board_reset(void) __attribute__((__weak__));
+
+#endif /* _CPU_H_ */

b/arch/m68k/cpu/mcf530x/cpu_init.c
new file mode 100644
index 0000000..50030ba

b/arch/m68k/cpu/mcf530x/interrupts.c
new file mode 100644
index 0000000..f743d1e

new file mode 100644
index 0000000..426bd9e
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 Angelo Dureghello <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks (void)
+{
+    gd->cpu_clk = CONFIG_SYS_CLK;
+    gd->bus_clk = gd->cpu_clk / 2;
+
+    return (0);
+}

valid flag */
+ move.c %d0, %MBAR
+

+    move.l    #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+    move.c    %d0, %RAMBAR

+
+ /* if we come from a pre-loader we have no exception table and
+ * therefore no VBR to set
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
+ movec %d0, %VBR
+#endif
+

+    /* initialize general use internal ram */
+    move.l #0, %d0
+    move.l #(ICACHE_STATUS), %a1    /* icache */
+    move.l #(DCACHE_STATUS), %a2    /* icache */
+    move.l %d0, (%a1)
+    move.l %d0, (%a2)

+
+ /* set stackpointer to internal sram end - 80 (global data struct
size + some bytes)
+ * get some stackspace for the first c-code,
+ */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp at -
+
+ move.l #__got_start, %a5 /* put relocation table address to a5 */
+
+ bsr cpu_init_f /* run low-level CPU init code (from
flash) */
+ bsr board_init_f /* run low-level board init code (from
flash) */
+
+ /* board_init_f() does not return */
+ +/*------------------------------------------------------------------------------*/ +
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:

+    link.w %a6,#0
+    move.l 8(%a6), %sp        /* set new stack pointer */
+    move.l 12(%a6), %d0        /* Save copy of Global Data pointer */
+    move.l 16(%a6), %a0        /* Save copy of Destination Address */
+
+    move.l #CONFIG_SYS_MONITOR_BASE, %a1
+    move.l #__init_end, %a2
+    move.l %a0, %a3
+
+    /* copy the code to RAM */
+1:
+    move.l (%a1)+, (%a3)+
+    cmp.l  %a1,%a2
+    bgt.s     1b

+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */

+    move.l    %a0, %a1
+    add.l    #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
+    jmp    (%a1)

+
+in_ram:
+
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */

+    move.l    %a0, %a1
+    add.l    #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
+    move.l    %a0, %d1
+    add.l    #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
+6:
+    clr.l    (%a1)+
+    cmp.l    %a1,%d1
+    bgt.s    6b

+
+ /*
+ * fix got table in RAM
+ */

+    move.l    %a0, %a1
+    add.l    #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
+    move.l    %a1,%a5        /* * fix got pointer register a5 */

+
+ move.l %a0, %a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
+
+7:

+    move.l    (%a1),%d1
+    sub.l    #_start,%d1
+    add.l    %a0,%d1
+    move.l    %d1,(%a1)+
+    cmp.l    %a2, %a1
+    bne    7b
+
+    /* calculate relative jump to board_init_r in ram */
+    move.l %a0, %a1
+    add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
+
+    /* set parameters for board_init_r */
+    move.l %a0,-(%sp)        /* dest_addr */
+    move.l %d0,-(%sp)        /* gd */

+#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
+ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
+ halt
+#endif
+ jsr (%a1)
+ +/*------------------------------------------------------------------------------*/ +/* exception code */
+ .globl _fault
+_fault:
+ jmp _fault
+
+ .globl _exc_handler
+_exc_handler:

+    SAVE_ALL
+    movel    %sp,%sp at -
+    bsr     exc_handler
+    addql    #4,%sp
+    RESTORE_ALL
+
+    .globl    _int_handler
+_int_handler:
+    SAVE_ALL
+    movel    %sp,%sp at -
+    bsr     int_handler
+    addql    #4,%sp
+    RESTORE_ALL

+ +/*------------------------------------------------------------------------------*/ +
+ .globl version_string
+version_string:

+    .ascii U_BOOT_VERSION
+    .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
+    .ascii CONFIG_IDENT_STRING, "\0"
+    .align 4

index 7c84e48..e447f3c 100644
@@ -31,7 +31,7 @@
  #define CONFIG_CF_V2
  #endif
 
-#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || 

defined(CONFIG_MCF5301x)
#define CONFIG_CF_V3
#endif

index e83ce08..bc43f13 100644
@@ -256,6 +256,28 @@
  #endif
  #endif                /* CONFIG_M5282 */
 
+#ifdef CONFIG_M5307
+#include <asm/immap_5307.h>
+#include <asm/m5307.h>
+
+#define CONFIG_SYS_UART_BASE        (MMAP_UART0 + (CONFIG_SYS_UART_PORT 

* 0x40))
+
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
+#define CONFIG_SYS_TMRINTR_NO (31)
+#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC |
MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif /* CONFIG_M5307 */
+
#if defined(CONFIG_MCF5301x)
#include <asm/immap_5301x.h>
#include <asm/m5301x.h>

b/arch/m68k/include/asm/immap_5307.h
new file mode 100644
index 0000000..cb58297

new file mode 100644
index 0000000..aaa9f68
@@ -0,0 +1,124 @@
+/*
+ * mcf5307.h -- Definitions for Motorola Coldfire 5307
+ *
+ * Copyright (c) 2011 Angelo Dureghello <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef    mcf5307_h
+#define    mcf5307_h
+/****************************************************************************/
+
+/*
+ * useful definitions for reading/writing MBAR offset memory
+ */
+#define mbar_readLong(x)    *((volatile unsigned long *) 

(CONFIG_SYS_MBAR + x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *)
(CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *)
(CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *)
(CONFIG_SYS_MBAR + x)) = y
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 4096 /* RAMBAR - 4k */
+
+/*
+ * Define the 5249 SIM register set addresses.
+ */
+
+/*****************
+ ***** MBAR *****
+ *****************/
+#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */

+#define MCFSIM_SYPCR        0x01    /* System Protection reg (r/w) */
+#define MCFSIM_SWIVR        0x02    /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR        0x03    /* SW Watchdog service (r/w) */
+#define MCFSIM_PLLCR        0x08    /* PLL Control register */
+#define MCFSIM_MPARK        0x0c    /* Bus master park register (r/w) */
+
+#define MCFSIM_SIMR        0x00    /* SIM Config reg (r/w) */
+#define MCFSIM_ICR0        0x4c    /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1        0x4d    /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2        0x4e    /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3        0x4f    /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4        0x50    /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5        0x51    /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6        0x52    /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7        0x53    /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8        0x54    /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9        0x55    /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10        0x56    /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11        0x57    /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_IPR        0x40    /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR        0x44    /* Interrupt Mask reg (r/w) */

+
+#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
+#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
+
+#define MCFSIM_PAR 0x004 /* Parallel port Pin assignment reg */
+#define MCFSIM_PADDR 0x244 /* Parallel port Pin direction reg */
+#define MCFSIM_PADAT 0x248 /* Parallel port Pin data reg */
+
+
+/*
+ * Some symbol defines for the above...
+ */

+#define    MCFSIM_SWDICR        MCFSIM_ICR0    /* Watchdog timer ICR */
+#define    MCFSIM_TIMER1ICR    MCFSIM_ICR1    /* Timer 1 ICR */
+#define    MCFSIM_TIMER2ICR    MCFSIM_ICR2    /* Timer 2 ICR */
+#define    MCFSIM_I2CICR        MCFSIM_ICR3    /* I2C ICR */
+#define    MCFSIM_UART1ICR    MCFSIM_ICR4    /* UART 1 ICR */
+#define    MCFSIM_UART2ICR    MCFSIM_ICR5    /* UART 2 ICR */

+/* XXX - If needed, DMA ICRs go here */
+
+/*
+ * Bit definitions for the ICR family of registers.
+ */

+#define    MCFSIM_ICR_AUTOVEC    0x80    /* Auto-vectored intr */
+#define    MCFSIM_ICR_LEVEL0        0x00    /* Level 0 intr */
+#define    MCFSIM_ICR_LEVEL1        0x04    /* Level 1 intr */
+#define    MCFSIM_ICR_LEVEL2        0x08    /* Level 2 intr */
+#define    MCFSIM_ICR_LEVEL3        0x0c    /* Level 3 intr */
+#define    MCFSIM_ICR_LEVEL4        0x10    /* Level 4 intr */
+#define    MCFSIM_ICR_LEVEL5        0x14    /* Level 5 intr */
+#define    MCFSIM_ICR_LEVEL6        0x18    /* Level 6 intr */
+#define    MCFSIM_ICR_LEVEL7        0x1c    /* Level 7 intr */
+
+#define    MCFSIM_ICR_PRI0        0x00    /* Priority 0 intr */
+#define    MCFSIM_ICR_PRI1        0x01    /* Priority 1 intr */
+#define    MCFSIM_ICR_PRI2        0x02    /* Priority 2 intr */
+#define    MCFSIM_ICR_PRI3        0x03    /* Priority 3 intr */

+
+/*
+ * Macros to read/set IMR register. It is 32 bits on the 5307.
+ */
+
+#define mcf_getimr() \
+ *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
+
+#define mcf_setimr(imr) \
+ *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
+
+#endif /* mcf5307_h */

index 1a5de05..8516c8f 100644
@@ -33,7 +33,7 @@
  /****************************************************************************/
  /* DMA Timer module registers */
  typedef struct dtimer_ctrl {
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
+#if defined(CONFIG_M5307) || defined(CONFIG_M5249) || 

defined(CONFIG_M5253) || defined(CONFIG_M5272)

      u16 tmr;        /* 0x00 Mode register */
      u16 res1;        /* 0x02 */
      u16 trr;        /* 0x04 Reference register */

index d244bd4..a775bcf 100644
@@ -243,8 +243,8 @@ typedef void (interrupt_handler_t)(void *);
 
  void    hang        (void) __attribute__ ((noreturn));
 
-int    timer_init(void);
-int    cpu_init(void);
+//int    timer_init(void);
+//int    cpu_init(void);
 
  /* */
  phys_size_t initdram (int);

@@ -595,7 +595,7 @@ void    get_sys_info  ( sys_info_t * );
  #if defined(CONFIG_8xx) || defined(CONFIG_8260)
  void    cpu_init_f    (volatile immap_t *immr);
  #endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || 

defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || 
defined(CONFIG_MCF52x2) || defined (CONFIG_MCF5307) || 

defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif

Hi, Angelo,
I suggest to send all the patchset including the board file changes so that we can at least test the building. Thanks.

Jason

Hi Jason an all,

many thanks for the feedback,
sure, i post another updated patch-set, as a cpu patch followed from board patch, in some minutes.

Regards
angelo