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arm: dts: barreleye: Add missing clock sources

PATCH Superseded Eddie James 2 participants 2 messages May 24, 2017

Subsystems (2)
Device tree bindings Arm/Aspeed machine support

v1 of 4 Superseded Latest is v4 →

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Eddie James

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PATCH 1/1 arm: dts: barreleye: Add missing clock sources

From: "Edward A. James" <[email protected]>

Prevented BMC from booting on Barreleye in 4.10 kernel, with new aspeed-smc driver.

Signed-off-by Edward A. James <[email protected]>
---
 arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +7 -0
index be1f2d1..9b59587 100644
@@ -37,10 +37,14 @@
 				0x20000000 0x02000000 >;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			interrupts = <19>;
 			compatible = "aspeed,ast2400-fmc";
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
 			flash@0 {
 				reg = < 0 >;
 				compatible = "jedec,spi-nor" ;
+				m25p,fast-read;
 #include "aspeed-bmc-opp-flash-layout.dtsi"
 			};
 		};

@@ -51,10 +55,13 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "aspeed,ast2400-spi";
+			clocks = <&clk_ahb>;
+			clock-names = "ahb";
 			flash@0 {
 				reg = < 0 >;
 				compatible = "jedec,spi-nor" ;
 				label = "pnor";
+				m25p,fast-read;
 			};
 		};
 	};
Signature · 1 line
1.8.3.1
#1 lore raw
Quoted 18 lines · Eddie James

Prevented BMC from booting on Barreleye in 4.10 kernel, with new aspeed-smc driver.

Signed-off-by Edward A. James <[email protected]>

---
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 7 +++++++

1 file changed, 7 insertions(+)
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +0 -0
index be1f2d1..9b59587 100644
@@ -37,10 +37,14 @@
 0x20000000 0x02000000 >;
 #address-cells = <1>;
 #size-cells = <0>;

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts line 49

Quoted 10 lines
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +4 -0
+ interrupts = <19>;
 compatible = "aspeed,ast2400-fmc";
+ clocks = <&clk_ahb>;
+ clock-names = "ahb";
 flash@0 {
 reg = < 0 >;
 compatible = "jedec,spi-nor" ;
+ m25p,fast-read;
 #include "aspeed-bmc-opp-flash-layout.dtsi"
 };

Since the clocks and interrupts are all inside the SOC they should be part of the aspeed-g4 dtsi.

It looks like this was factored better on the g5 vs the g4 dtsi.

arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts line 64

Quoted 12 lines
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts +3 -0
 };

@@ -51,10 +55,13 @@
 #address-cells = <1>;
 #size-cells = <0>;
 compatible = "aspeed,ast2400-spi";
+ clocks = <&clk_ahb>;
+ clock-names = "ahb";
 flash@0 {
 reg = < 0 >;
 compatible = "jedec,spi-nor" ;
 label = "pnor";
+ m25p,fast-read;

milton