Add device tree support for sc7180
Subsystems (5)
v5 cover Add device tree support for sc7180
Bjorn/Andy, this patch series is now fairly reviewed and ack'ed, and given the dependent gcc patches (dt bindings header dependency for dts) have now landed in clk-next, can we pull these in as part of your second PR for 5.5?
Changes in v5:
* Dropped the arm-smmu binding update patch, pulled in by Rob H
* Updated 1/13 to also sort SoC and board names
* Dropped clock-output-names for sleep_clk
* Dropped the label for rsc node
Changes in v4:
* Rebased on top of Rob;s for-next
* reorderd patches to take care of pdc dependency
* Updated pdc binding to use a soc specific and soc independent compatible
* Other updates based on v3 feedback, changes listed in each patch
Changes in v3:
* PATCH 2/11: Updated the qup and uart lables to be consistent with the naming convention followed in sdm845 as suggested by Matthias
* Dropped 2 patches from v2 which added the new compatible and binding updates for sc7180 pdc and reused sdm845 compatible instead as suggested by Marc Z
This series adds DT support for basic peripherals on qualcomm's sc7180 SoC, drivers for which are already upstream.
Kiran Gunda (3):
arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
arm64: dts: qcom: sc7180-idp: Add RPMh regulators
Maulik Shah (3):
arm64: dts: qcom: sc7180: Add cmd_db reserved area
arm64: dts: qcom: sc7180: Add rpmh-rsc node
arm64: dts: qcom: sc7180: Add pdc interrupt controller
Rajendra Nayak (4):
dt-bindings: qcom: Add SC7180 bindings
arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
dt-bindings: qcom,pdc: Add compatible for sc7180
Roja Rani Yarubandi (1):
arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Taniya Das (1):
arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
Vivek Gautam (1):
arm64: dts: sc7180: Add device node for apps_smmu
.../devicetree/bindings/arm/qcom.yaml | 44 +- .../interrupt-controller/qcom,pdc.txt | 3 +- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/pm6150.dtsi | 72 ++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 31 + arch/arm64/boot/dts/qcom/sc7180-idp.dts | 402 ++++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 1131 +++++++++++++++++ drivers/irqchip/qcom-pdc.c | 2 +- 8 files changed, 1665 insertions(+), 21 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 1/13 dt-bindings: qcom: Add SC7180 bindings
Add a SoC string 'sc7180' for the qualcomm SC7180 SoC. Also add a new board type 'idp'
While at it, also sort the SoC and board names in
alphabetical order, and also fix the weird space
and tab combinations found in the file.
--- .../devicetree/bindings/arm/qcom.yaml | 44 +++++++++++-------- 1 file changed, 25 insertions(+), 19 deletions(-)
Documentation/devicetree/bindings/arm/qcom.yaml +25 -19
@@ -24,28 +24,30 @@ description: | The 'SoC' element must be one of the following strings: - apq8016 - apq8074 - apq8084 - apq8096 - msm8916 - msm8974 - msm8992 - msm8994 - msm8996 - mdm9615 - ipq8074 - sdm845 + apq8016 + apq8074 + apq8084 + apq8096 + ipq8074 + mdm9615 + msm8916 + msm8974 + msm8992 + msm8994 + msm8996 + sc7180 + sdm845 The 'board' element must be one of the following strings: - cdp - liquid - dragonboard - mtp - sbc - hk01 - qrd + cdp + dragonboard + hk01 + idp + liquid + mtp + qrd + sbc The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the same
@@ -144,4 +146,8 @@ properties: - qcom,ipq8074-hk01 - const: qcom,ipq8074 + - items: + - enum: + - qcom,sc7180-idp + - const: qcom,sc7180 ...
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 2/13 arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
In reply to Rajendra NayakAdd skeletal sc7180 SoC dtsi and idp board dts files.
--- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7180-idp.dts | 47 ++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 298 ++++++++++++++++++++++++ 3 files changed, 346 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180.dtsi
arch/arm64/boot/dts/qcom/Makefile +1 -0
@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
arch/arm64/boot/dts/qcom/sc7180-idp.dts new file +47 -0
47 lines not on this page · raw message
arch/arm64/boot/dts/qcom/sc7180.dtsi new file +298 -0
298 lines not on this page · raw message
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 02/13] arm64: dts: sc7180: Add minimal dts/dtsi files for SC7180 soc
Quoting Rajendra Nayak (2019-11-08 01:28:13)
Quoted 6 lines
Add skeletal sc7180 SoC dtsi and idp board dts files.
Co-developed-by Taniya Das <[email protected]>Signed-off-by Taniya Das <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v5 3/13 arm64: dts: sc7180: Add device node for apps_smmu
In reply to Rajendra NayakFrom: Vivek Gautam <[email protected]>
Adding device node for APPS SMMU that is connected to devices such as display, video, usb, mmc, etc. on SC7180 chipset.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 88 ++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +88 -0
@@ -209,6 +209,94 @@ }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #address-cells = <2>;
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 4/13 arm64: dts: qcom: sc7180: Add cmd_db reserved area
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Command_db provides mapping for resource key and address managed by remote processor. Add cmd_db reserved memory area.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +12 -0
@@ -30,6 +30,18 @@ }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aop_cmd_db_mem: memory@80820000 { + reg = <0x0 0x80820000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 5/13 arm64: dts: qcom: sc7180: Add rpmh-rsc node
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Add device bindings for the application processor's rsc. The rsc contains the TCS that are used for communicating with the hardened resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +18 -0
@@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7180.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> / { interrupt-parent = <&intc>;
@@ -386,6 +387,23 @@ status = "disabled"; }; }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0 0x18200000 0 0x10000>, + <0 0x18210000 0 0x10000>, + <0 0x18220000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 1>; + }; }; timer {
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PATCH v5 6/13 drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
In reply to Rajendra NayakRemove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
--- drivers/irqchip/qcom-pdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/irqchip/qcom-pdc.c +1 -1
@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)return ret; } -IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 06/13] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
Quoted 18 lines · Rajendra Nayak
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Lina Iyer <[email protected]>Reviewed-by Stephen Boyd <[email protected]>Cc Marc Zyngier <[email protected]>--- drivers/irqchip/qcom-pdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/irqchip/qcom-pdc.c +0
-0
drivers/irqchip/qcom-pdc.c static int qcom_pdc_init(struct device_node · line 312
Quoted 6 lines
drivers/irqchip/qcom-pdc.c +1
-1@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)return ret; } -IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);
How do you want me get this (and the DT change) merged? I can either take these two patches in the irqchip tree, or you arrange them to be taken by the platform maintainers. Your call.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Marc Zyngier
Acked-byRe: [PATCH v5 06/13] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
Quoted 23 lines · Marc Zyngier
Quoted 22 lines · Rajendra Nayak
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Lina Iyer <[email protected]>Reviewed-by Stephen Boyd <[email protected]>Cc Marc Zyngier <[email protected]>--- drivers/irqchip/qcom-pdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/irqchip/qcom-pdc.c +0
-0@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent)return ret; }
Quoted 4 lines
drivers/irqchip/qcom-pdc.c static int qcom_pdc_init(struct device_node *node, struct device_node *parent) · line 312
Quoted 2 lines
drivers/irqchip/qcom-pdc.c +1
-1-IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);Acked-by Marc Zyngier <[email protected]>
I need to have my hands fixed. The real tag is:
One day, I'll manage that...
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Re: [PATCH v5 06/13] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
In reply to Marc ZyngierQuoted 23 lines · Marc Zyngier
Quoted 22 lines · Rajendra Nayak
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Lina Iyer <[email protected]>Reviewed-by Stephen Boyd <[email protected]>Cc Marc Zyngier <[email protected]>---
drivers/irqchip/qcom-pdc.c | 2 +-1 file changed, 1 insertion(+), 1 deletion(-)drivers/irqchip/qcom-pdc.c +0
-0@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) return ret; }
Quoted 8 lines
drivers/irqchip/qcom-pdc.c static int qcom_pdc_init(struct device_node *node, struct device_node *parent) · line 312
Quoted 2 lines
drivers/irqchip/qcom-pdc.c +1
-1-IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);Acked-by Marc Zyngier <[email protected]>How do you want me get this (and the DT change) merged? I can either take these two patches in the irqchip tree, or you arrange them to be taken by the platform maintainers. Your call.
I think it makes sense for you to take these two via your tree (The driver and binding doc updates) and the DT node addition for pdc to go via Andy/Bjorn. Andy/Bjorn, does that sound fine?
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 06/13] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
Quoted 30 lines · Rajendra Nayak
Quoted 28 lines · Marc Zyngier
Quoted 18 lines · Rajendra Nayak
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Lina Iyer <[email protected]>Reviewed-by Stephen Boyd <[email protected]>Cc Marc Zyngier <[email protected]>---
drivers/irqchip/qcom-pdc.c | 2 +-1 file changed, 1 insertion(+), 1 deletion(-)drivers/irqchip/qcom-pdc.c +0
-0drivers/irqchip/qcom-pdc.c static int qcom_pdc_init(struct device_node · line 312
Quoted 6 lines
drivers/irqchip/qcom-pdc.c +1
-1@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) return ret; } -IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);Acked-by Marc Zyngier <[email protected]>
Quoted 8 lines
Quoted 3 lines
How do you want me get this (and the DT change) merged? I can either take these two patches in the irqchip tree, or you arrange them to be taken by the platform maintainers. Your call.
I think it makes sense for you to take these two via your tree (The driver and binding doc updates) and the DT node addition for pdc to go via Andy/Bjorn. Andy/Bjorn, does that sound fine?
Yes, that sounds good.
Regards,
Bjorn
Marc Zyngier
AppliedRe: [PATCH v5 06/13] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
Quoted 37 lines · Bjorn Andersson
Quoted 35 lines · Rajendra Nayak
Quoted 14 lines · Marc Zyngier
Quoted 13 lines · Rajendra Nayak
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Lina Iyer <[email protected]>Reviewed-by Stephen Boyd <[email protected]>Cc Marc Zyngier <[email protected]>---
drivers/irqchip/qcom-pdc.c | 2 +-1 file changed, 1 insertion(+), 1 deletion(-)Quoted 1 line
Review
Quoted 1 line
(quoted diff) +0
-0
b/drivers/irqchip/qcom-pdc.cQuoted 8 lines
Quoted 8 lines
index
faa7d61b9d6c..c175333bb646100644drivers/irqchip/qcom-pdc.c +0
-0@@ -309,4 +309,4 @@ static int qcom_pdc_init(struct device_node *node, struct device_node *parent) return ret; }Quoted 6 lines
drivers/irqchip/qcom-pdc.c static int qcom_pdc_init(struct device_node *node, struct device_node *parent) · line 312
Quoted 2 lines
drivers/irqchip/qcom-pdc.c +1
-1-IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);Acked-by Marc Zyngier <[email protected]>How do you want me get this (and the DT change) merged? I can
either take
Quoted 1 line
these two patches in the irqchip tree, or you arrange them to be
taken
Quoted 8 lines
Quoted 6 lines
Quoted 1 line
by the platform maintainers. Your call.
I think it makes sense for you to take these two via your tree (The driver and binding doc updates) and the DT node addition for pdc to go via Andy/Bjorn. Andy/Bjorn, does that sound fine?
Yes, that sounds good.
Applied to irqchip/next
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
[tip: irq/core] drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
In reply to Rajendra NayakThe following commit has been merged into the irq/core branch of tip:
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 8e4d5a5bde8896c7fa36b173c613dbbbf9d5dc32 Gitweb: https://git.kernel.org/tip/8e4d5a5bde8896c7fa36b173c613dbbbf9d5dc32 Author: Rajendra Nayak <[email protected]> AuthorDate: Fri, 08 Nov 2019 14:58:17 +05:30 Committer: Marc Zyngier <[email protected]> CommitterDate: Sun, 10 Nov 2019 18:47:49
drivers: irqchip: qcom-pdc: Move to an SoC independent compatible
Remove the sdm845 SoC specific compatible to make the driver easily reusable across other SoC's with the same IP block. This will reduce further churn adding any SoC specific compatibles unless really needed.
--- drivers/irqchip/qcom-pdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/irqchip/qcom-pdc.c +1 -1
@@ -309,4 +309,4 @@ fail:return ret; } -IRQCHIP_DECLARE (pdc_sdm845,"qcom,sdm845-pdc" , qcom_pdc_init); +IRQCHIP_DECLARE (qcom_pdc,"qcom,pdc" , qcom_pdc_init);
PATCH v5 7/13 dt-bindings: qcom,pdc: Add compatible for sc7180
In reply to Rajendra NayakAdd the compatible string for sc7180 SoC from Qualcomm.
--- .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +2 -1
@@ -17,7 +17,8 @@ Properties: - compatible: Usage: required Value type: <string> - Definition: Should contain "qcom,<soc>-pdc" + Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc" + - "qcom,sc7180-pdc": For SC7180 - "qcom,sdm845-pdc": For SDM845 - reg:
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[tip: irq/core] dt-bindings: qcom,pdc: Add compatible for sc7180
The following commit has been merged into the irq/core branch of tip:
The following commit has been merged into the irq/core branch of tip:
Commit-ID: bf93b04cd85d74c34335e76882cf8bf206caab6e Gitweb: https://git.kernel.org/tip/bf93b04cd85d74c34335e76882cf8bf206caab6e Author: Rajendra Nayak <[email protected]> AuthorDate: Fri, 08 Nov 2019 14:58:18 +05:30 Committer: Marc Zyngier <[email protected]> CommitterDate: Sun, 10 Nov 2019 18:47:50
dt-bindings: qcom,pdc: Add compatible for sc7180
Add the compatible string for sc7180 SoC from Qualcomm.
--- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +2 -1
@@ -17,7 +17,8 @@ Properties: - compatible: Usage: required Value type: <string> - Definition: Should contain "qcom,<soc>-pdc" + Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc" + - "qcom,sc7180-pdc": For SC7180 - "qcom,sdm845-pdc": For SDM845 - reg:
PATCH v5 8/13 arm64: dts: qcom: sc7180: Add pdc interrupt controller
In reply to Rajendra NayakFrom: Maulik Shah <[email protected]>
Add pdc interrupt controller for sc7180
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +10 -0
@@ -201,6 +201,16 @@ }; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sc7180-pdc", "qcom,pdc"; + reg = <0 0xb220000 0 0x30000>; + qcom,pdc-ranges = <0 480 15>, <17 497 98>, + <119 634 4>, <124 639 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@3500000 { compatible = "qcom,sc7180-pinctrl"; reg = <0 0x03500000 0 0x300000>,
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PATCH v5 9/13 arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +19 -0
@@ -232,6 +232,25 @@ }; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>;
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PATCH v5 10/13 arm64: dts: qcom: pm6150: Add PM6150/PM6150L PMIC peripherals
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add PM6150/PM6150L peripherals such as PON, GPIOs, ADC and other PMIC infra modules.
--- arch/arm64/boot/dts/qcom/pm6150.dtsi | 72 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 31 +++++++++++ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 2 + 3 files changed, 105 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm6150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm6150l.dtsi
arch/arm64/boot/dts/qcom/pm6150.dtsi new file +72 -0
@@ -0,0 +1,72 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/iio/qcom,spmi-vadc.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/thermal/thermal.h> + +&spmi_bus { + pm6150_lsid0: pmic@0 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150_pon: pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + }; + + pm6150_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm6150_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6150_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@ADC5_DIE_TEMP { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + }; + }; + + pm6150_gpio: gpios@c000 { + compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm6150_gpio 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm6150_lsid1: pmic@1 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
arch/arm64/boot/dts/qcom/pm6150l.dtsi new file +31 -0
@@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pm6150l_lsid4: pmic@4 { + compatible = "qcom,pm6150l", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm6150l_gpio: gpios@c000 { + compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm6150l_gpio 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm6150l_lsid5: pmic@5 { + compatible = "qcom,pm6150l", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};
arch/arm64/boot/dts/qcom/sc7180-idp.dts +2 -0
@@ -8,6 +8,8 @@ /dts-v1/; #include "sc7180.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" / { model = "Qualcomm Technologies, Inc. SC7180 IDP";
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PATCH v5 11/13 arm64: dts: qcom: sc7180-idp: Add RPMh regulators
In reply to Rajendra NayakFrom: Kiran Gunda <[email protected]>
Add the rpmh regulators for the sc7180 idp platform. This platform consists of PMIC PM6150 and PM6150l
--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 207 ++++++++++++++++++++++++ 1 file changed, 207 insertions(+)
arch/arm64/boot/dts/qcom/sc7180-idp.dts +207 -0
@@ -7,6 +7,7 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc7180.dtsi" #include "pm6150.dtsi" #include "pm6150l.dtsi"
@@ -24,6 +25,212 @@ }; }; +&apps_rsc { + pm6150-rpmh-regulators { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s1a_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s4a_1p0: smps4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1744000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_l1a_1p2: ldo1 { + regulator-min-microvolt = <1178000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_1p0: ldo2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l4a_0p8: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_2p7: ldo5 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p6: ldo6 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <648000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p6: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1832000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l19a_2p9: ldo19 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; + + pm6150l-rpmh-regulators { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + }; +}; + &qupv3_id_1 { status = "okay"; };
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Re: [PATCH v5 11/13] arm64: dts: qcom: sc7180-idp: Add RPMh regulators
Quoting Rajendra Nayak (2019-11-08 01:28:22)
Quoted 8 lines
From: Kiran Gunda <[email protected]>
Add the rpmh regulators for the sc7180 idp platform. This platform consists of PMIC PM6150 and PM6150l
Signed-off-by Kiran Gunda <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>---
PATCH v5 12/13 arm64: dts: qcom: SC7180: Add node for rpmhcc clock driver
In reply to Rajendra NayakFrom: Taniya Das <[email protected]>
Add node for rpmhcc clock driver.
--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +11 -0
@@ -6,6 +6,7 @@ */ #include <dt-bindings/clock/qcom,gcc-sc7180.h> +#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -173,6 +174,9 @@ gcc: clock-controller@100000 { compatible = "qcom,gcc-sc7180"; reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;
@@ -432,6 +436,13 @@ <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 1>; + + rpmhcc: clock-controller { + compatible = "qcom,sc7180-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; }; };
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PATCH v5 13/13 arm64: dts: sc7180: Add qupv3_0 and qupv3_1
In reply to Rajendra NayakFrom: Roja Rani Yarubandi <[email protected]>
Add QUP SE instances configuration for sc7180.
--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ 2 files changed, 821 insertions(+)
arch/arm64/boot/dts/qcom/sc7180-idp.dts +146 -0
@@ -17,6 +17,7 @@ compatible = "qcom,sc7180-idp"; aliases { + hsuart0 = &uart3; serial0 = &uart8; };
@@ -231,16 +232,100 @@ }; }; +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; +&uart3 { + status = "okay"; +}; + &uart8 { status = "okay"; }; /* PINCTRL - additions to nodes defined in sc7180.dtsi */ +&qup_i2c2_default { + pinconf { + pins = "gpio15", "gpio16"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c4_default { + pinconf { + pins = "gpio115", "gpio116"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c7_default { + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c9_default { + pinconf { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_uart3_default { + pinconf-cts { + /* + * Configure a pull-down on 38 (CTS) to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + bias-pull-down; + output-high; + }; + + pinconf-rts { + /* We'll drive 39 (RTS), so no pull */ + pins = "gpio39"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-tx { + /* We'll drive 40 (TX), so no pull */ + pins = "gpio40"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + pinconf-rx { + /* + * Configure a pull-up on 41 (RX). This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + pins = "gpio41"; + bias-pull-up; + }; +}; + &qup_uart8_default { pinconf-tx { pins = "gpio44";
@@ -254,3 +339,64 @@ bias-pull-up; }; }; + +&qup_spi0_default { + pinconf { + pins = "gpio34", "gpio35", "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi6_default { + pinconf { + pins = "gpio59", "gpio60", "gpio61", "gpio62"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi10_default { + pinconf { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&qspi_cs0 { + pinconf { + pins = "gpio68"; + bias-disable; + }; +}; + +&qspi_clk { + pinconf { + pins = "gpio63"; + bias-disable; + }; +}; + +&qspi_data01 { + pinconf { + pins = "gpio64", "gpio65"; + + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; + }; +};
arch/arm64/boot/dts/qcom/sc7180.dtsi +675 -0
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Re: [PATCH v5 13/13] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Hi,
Quoted 5 lines · Rajendra Nayak
From: Roja Rani Yarubandi <[email protected]>
Add QUP SE instances configuration for sc7180.
Quoted 7 lines
Signed-off-by Roja Rani Yarubandi <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Stephen Boyd <[email protected]>--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ 2 files changed, 821 insertions(+)
Comments below could be done in a follow-up patch if it makes more sense.
arch/arm64/boot/dts/qcom/sc7180.dtsi
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0
At the top of this file, please add aliases for all i2c and spi devices (like sdm845 did). Right now trying to use command line i2c tools is super confusing because busses are super jumbled.
arch/arm64/boot/dts/qcom/sc7180.dtsi line 281
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +12
-0+ i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };
Where is spi2?
arch/arm64/boot/dts/qcom/sc7180.dtsi line 342
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +12
-0+ i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };
Where is spi4?
arch/arm64/boot/dts/qcom/sc7180.dtsi line 452
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +12
-0+ i2c7: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };
Where is spi7?
arch/arm64/boot/dts/qcom/sc7180.dtsi line 513
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +12
-0+ i2c9: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };
Where is spi9?
arch/arm64/boot/dts/qcom/sc7180.dtsi line 755
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ qup_spi1_default: qup-spi1-default { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio12", "gpio94";
Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this.
arch/arm64/boot/dts/qcom/sc7180.dtsi line 780
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ qup_spi6_default: qup-spi6-default { + pinmux { + pins = "gpio59", "gpio60", + "gpio61", "gpio62", + "gpio68", "gpio72";
Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this.
arch/arm64/boot/dts/qcom/sc7180.dtsi line 797
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ qup_spi10_default: qup-spi10-default { + pinmux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89", + "gpio90", "gpio91";
Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this.
-Doug
Re: [PATCH v5 13/13] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Quoted 19 lines · Doug Anderson
Hi,
Quoted 5 lines · Rajendra Nayak
From: Roja Rani Yarubandi <[email protected]>
Add QUP SE instances configuration for sc7180.
Quoted 7 lines
Signed-off-by Roja Rani Yarubandi <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Stephen Boyd <[email protected]>--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ 2 files changed, 821 insertions(+)Comments below could be done in a follow-up patch if it makes more sense.
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0At the top of this file, please add aliases for all i2c and spi devices (like sdm845 did). Right now trying to use command line i2c tools is super confusing because busses are super jumbled.
sure, I'll add it.
Quoted 63 lines
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +2
-0+ i2c2: i2c@888000 { + compatible = "qcom,geni-i2c";arch/arm64/boot/dts/qcom/sc7180.dtsi line 281
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +10
-0+ reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };Where is spi2?
arch/arm64/boot/dts/qcom/sc7180.dtsi line 342
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +12
-0+ i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };Where is spi4?
arch/arm64/boot/dts/qcom/sc7180.dtsi line 452
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +12
-0+ i2c7: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };Where is spi7?
arch/arm64/boot/dts/qcom/sc7180.dtsi line 513
Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +12
-0+ i2c9: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_default>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + };
Quoted 1 line
Where is spi9?
so looks like these qup instances (qup2/4/7/9) can only be configured to be used as i2c or uart and not spi since we have only 2 pins for them and spi needs 4.
Quoted 29 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 755
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ qup_spi1_default: qup-spi1-default { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio12", "gpio94";Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this.
arch/arm64/boot/dts/qcom/sc7180.dtsi line 780
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ qup_spi6_default: qup-spi6-default { + pinmux { + pins = "gpio59", "gpio60", + "gpio61", "gpio62", + "gpio68", "gpio72";Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this.
arch/arm64/boot/dts/qcom/sc7180.dtsi line 797
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +5
-0+ qup_spi10_default: qup-spi10-default { + pinmux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89", + "gpio90", "gpio91";
Quoted 3 lines
Please just mux one of the chip selects by default. It seems like it would be _much_ more common to have a single SPI device on the bus and then every board doesn't have to override this.
yes, i will fix all of them to remove the additional chip select muxes.
Signature · 2 lines
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Re: [PATCH v5 13/13] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Hi,
Quoted 18 lines · Rajendra Nayak
Quoted 16 lines · Doug Anderson
Hi,
Quoted 12 lines · Rajendra Nayak
From: Roja Rani Yarubandi <[email protected]>
Add QUP SE instances configuration for sc7180.
Signed-off-by Roja Rani Yarubandi <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Stephen Boyd <[email protected]>--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 146 +++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 675 ++++++++++++++++++++++++ 2 files changed, 821 insertions(+)
Quoted 1 line
Quoted 1 line
Comments below could be done in a follow-up patch if it makes more sense.
Just to note: looks like your patch is now landed in the Qualcomm maintainer tree, so I'll look for the fixes in a follow-up patch. :-)
-Doug