Re-introduce TX FIFO resize for larger EP bursting

Some devices have USB compositions which may require multiple endpoints that support EP bursting. HW defined TX FIFO sizes may not always be sufficient for these compositions. By utilizing flexible TX FIFO allocation, this allows for endpoints to request the required FIFO depth to achieve higher bandwidth. With some higher bMaxBurst configurations, using a larger TX FIFO size results in better TX throughput.

drivers/usb/dwc3/ep0.c +22 -0

@@ -611,6 +612,40 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 		return -EINVAL;
 
 	case USB_STATE_ADDRESS:
+		/*
+		 * If tx-fifo-resize flag is not set for the controller, then
+		 * do not clear existing allocated TXFIFO since we do not
+		 * allocate it again in dwc3_gadget_resize_tx_fifos
+		 */
+		if (dwc->needs_fifo_resize) {
+			/* Read ep0IN related TXFIFO size */
+			dep = dwc->eps[1];
+			size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+			if (dwc3_is_usb31(dwc))
+				dep->fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+			else
+				dep->fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
+
+			dwc->last_fifo_depth = dep->fifo_depth;
+			/* Clear existing TXFIFO for all IN eps except ep0 */
+			for (num = 3; num < min_t(int, dwc->num_eps,
+				DWC3_ENDPOINTS_NUM); num += 2) {
+				dep = dwc->eps[num];
+				/* Don't change TXFRAMNUM on usb31 version */
+				size = dwc3_is_usb31(dwc) ?
+					dwc3_readl(dwc->regs,

drivers/usb/dwc3/gadget.c +15 -0

index 00746c2848c0..777badf3e85d 100644
@@ -540,6 +540,117 @@ static int dwc3_gadget_start_config(struct dwc3_ep *dep)
 	return 0;
 }
 
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *

drivers/usb/dwc3/gadget.c +9 -0

+		return 0;
+
+	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+	mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+	/* MDWIDTH is represented in bits, we need it in bytes */
+	mdwidth >>= 3;
+
+	if (((dep->endpoint.maxburst > 1) &&
+			usb_endpoint_xfer_bulk(dep->endpoint.desc))

drivers/usb/dwc3/gadget.c +18 -0

+	dep->fifo_depth = fifo_size;
+
+	/* Check if TXFIFOs start at non-zero addr */
+	tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+	fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+	fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+	if (dwc3_is_usb31(dwc))
+		dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+	else
+		dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+
+	/* Check fifo size allocation doesn't exceed available RAM size. */
+	if (dwc->last_fifo_depth >= ram1_depth) {
+		dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
+				(dwc->last_fifo_depth * mdwidth), ram1_depth,
+				dep->endpoint.name, fifo_size);
+		if (dwc3_is_usb31(dwc))

Wesley Cheng <[email protected]> writes:

Hi,

Quoted 6 lines

Some devices have USB compositions which may require multiple endpoints that support EP bursting. HW defined TX FIFO sizes may not always be sufficient for these compositions. By utilizing flexible TX FIFO allocation, this allows for endpoints to request the required FIFO depth to achieve higher bandwidth. With some higher bMaxBurst configurations, using a larger TX FIFO size results in better TX throughput.

how much better? What's the impact? Got some real numbers of this running with upstream kernel? I guess mass storage gadget is the simplest one to test.

Quoted 4 lines

drivers/usb/dwc3/ep0.c +0 -0

index 6dee4dabc0a4..76db9b530861 100644

drivers/usb/dwc3/ep0.c static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) · line 604

Quoted 6 lines

drivers/usb/dwc3/ep0.c +1 -1

@@ -601,8 +601,9 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 {
 	enum usb_device_state state = dwc->gadget.state;
 	u32 cfg;
-	int ret;
+	int ret, num, size;

no, no. Please one declaration per line.

drivers/usb/dwc3/ep0.c static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) · line 606

Quoted 2 lines

drivers/usb/dwc3/ep0.c +1 -0

 	u32 reg;
+	struct dwc3_ep *dep;

Keep reverse xmas tree order.

Quoted 31 lines

drivers/usb/dwc3/ep0.c +27 -0

@@ -611,6 +612,40 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 		return -EINVAL;
 
 	case USB_STATE_ADDRESS:
+		/*
+		 * If tx-fifo-resize flag is not set for the controller, then
+		 * do not clear existing allocated TXFIFO since we do not
+		 * allocate it again in dwc3_gadget_resize_tx_fifos
+		 */
+		if (dwc->needs_fifo_resize) {
+			/* Read ep0IN related TXFIFO size */
+			dep = dwc->eps[1];
+			size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+			if (dwc3_is_usb31(dwc))
+				dep->fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+			else
+				dep->fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
+
+			dwc->last_fifo_depth = dep->fifo_depth;
+			/* Clear existing TXFIFO for all IN eps except ep0 */
+			for (num = 3; num < min_t(int, dwc->num_eps,
+				DWC3_ENDPOINTS_NUM); num += 2) {
+				dep = dwc->eps[num];
+				/* Don't change TXFRAMNUM on usb31 version */
+				size = dwc3_is_usb31(dwc) ?
+					dwc3_readl(dwc->regs,
+						   DWC3_GTXFIFOSIZ(num >> 1)) &
+						   DWC31_GTXFIFOSIZ_TXFRAMNUM :
+						   0;
+
+				dwc3_writel(dwc->regs,

drivers/usb/dwc3/ep0.c static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) · line 646

Quoted 5 lines

drivers/usb/dwc3/ep0.c +5 -0

+					    DWC3_GTXFIFOSIZ(num >> 1),
+					    size);
+				dep->fifo_depth = 0;
+			}
+			dwc->num_ep_resized = 0;

care to move this into a helper that you call unconditionally and the helper returns early is !needs_fifo_resize?

Quoted 28 lines

drivers/usb/dwc3/gadget.c +20 -0

index 00746c2848c0..777badf3e85d 100644
@@ -540,6 +540,117 @@ static int dwc3_gadget_start_config(struct dwc3_ep *dep)
 	return 0;
 }
 
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 567

Quoted 5 lines

drivers/usb/dwc3/gadget.c +5 -0

+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+	struct dwc3 *dwc = dep->dwc;
+	int ram1_depth, mdwidth, fifo_0_start, tmp, num_in_ep;
+	int min_depth, remaining, fifo_size, mult = 1, fifo, max_packet = 1024;

one declaration per line, also make sure you order it in reverse xmas tree order.

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 577

Quoted 9 lines

drivers/usb/dwc3/gadget.c +9 -0

+	if (!dwc->needs_fifo_resize)
+		return 0;
+
+	/* resize IN endpoints except ep0 */
+	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+		return 0;
+
+	/* Don't resize already resized IN endpoint */
+	if (dep->fifo_depth)

using fifo_depth as a flag seems flakey to me. What happens when someone in the future changes the behavior below and this doesn't apply anymore?

Also, why is this procedure called more than once for the same endpoint? Does that really happen?

Quoted 9 lines

drivers/usb/dwc3/gadget.c +9 -0

+		return 0;
+
+	ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+	mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+	/* MDWIDTH is represented in bits, we need it in bytes */
+	mdwidth >>= 3;
+
+	if (((dep->endpoint.maxburst > 1) &&
+			usb_endpoint_xfer_bulk(dep->endpoint.desc))

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 596

Quoted 10 lines

drivers/usb/dwc3/gadget.c +10 -0

+			|| usb_endpoint_xfer_isoc(dep->endpoint.desc))
+		mult = 3;
+
+	if ((dep->endpoint.maxburst > 6) &&
+			usb_endpoint_xfer_bulk(dep->endpoint.desc)
+			&& dwc3_is_usb31(dwc))
+		mult = 6;
+
+	/* FIFO size for a single buffer */
+	fifo = (max_packet + mdwidth)/mdwidth;

add spaces around integer division operator

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 609

Quoted 13 lines

drivers/usb/dwc3/gadget.c +13 -0

+	fifo++;
+
+	/* Calculate the number of remaining EPs w/o any FIFO */
+	num_in_ep = dwc->num_eps/2;
+	num_in_ep -= dwc->num_ep_resized;
+	/* Ignore EP0 IN */
+	num_in_ep--;
+
+	/* Reserve at least one FIFO for the number of IN EPs */
+	min_depth = num_in_ep * (fifo+1);
+	remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
+
+	/* We've already reserved 1 FIFO per EP, so check what we can fit in

comment style is wrong

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 613

Quoted 4 lines

drivers/usb/dwc3/gadget.c +4 -0

+	 * addition to it.  If there is not enough remaining space, allocate
+	 * all the remaining space to the EP.
+	 */
+	fifo_size = (mult-1) * fifo;

spaces around subtraction

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 622

Quoted 9 lines

drivers/usb/dwc3/gadget.c +9 -0

+	if (remaining < fifo_size) {
+		if (remaining > 0)
+			fifo_size = remaining;
+		else
+			fifo_size = 0;
+	}
+
+	fifo_size += fifo;
+	fifo_size++;

why the increment?

Quoted 18 lines

drivers/usb/dwc3/gadget.c +18 -0

+	dep->fifo_depth = fifo_size;
+
+	/* Check if TXFIFOs start at non-zero addr */
+	tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+	fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+	fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+	if (dwc3_is_usb31(dwc))
+		dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+	else
+		dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+
+	/* Check fifo size allocation doesn't exceed available RAM size. */
+	if (dwc->last_fifo_depth >= ram1_depth) {
+		dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
+				(dwc->last_fifo_depth * mdwidth), ram1_depth,
+				dep->endpoint.name, fifo_size);
+		if (dwc3_is_usb31(dwc))

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 650

Quoted 10 lines

drivers/usb/dwc3/gadget.c +10 -0

+			fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+		else
+			fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+		dwc->last_fifo_depth -= fifo_size;
+		dep->fifo_depth = 0;
+		return -ENOMEM;
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
+	dwc->num_ep_resized++;

add a blank line here

Quoted 9 lines

drivers/usb/dwc3/gadget.c +3 -0

+	return 0;
+}
+
 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 {
 	const struct usb_ss_ep_comp_descriptor *comp_desc;

@@ -620,6 +731,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 	int			ret;
 

drivers/usb/dwc3/gadget.c static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) · line 736

Quoted 4 lines

drivers/usb/dwc3/gadget.c +3 -0

 	if (!(dep->flags & DWC3_EP_ENABLED)) {
+		ret = dwc3_gadget_resize_tx_fifos(dep);
+		if (ret)
+			return ret;

doesn't it look odd that you're resizing every fifo every time a new endpoint is enabled? Is there a better way to achieve this?

Quoted 11 lines · Felipe Balbi

Wesley Cheng <[email protected]> writes:

Hi,

Quoted 6 lines

Some devices have USB compositions which may require multiple endpoints that support EP bursting. HW defined TX FIFO sizes may not always be sufficient for these compositions. By utilizing flexible TX FIFO allocation, this allows for endpoints to request the required FIFO depth to achieve higher bandwidth. With some higher bMaxBurst configurations, using a larger TX FIFO size results in better TX throughput.

Quoted 4 lines

how much better? What's the impact? Got some real numbers of this running with upstream kernel? I guess mass storage gadget is the simplest one to test.

Hi Felipe,

Thanks for the input.

Sorry for not including the numbers in the patch itself, but I did mention the set of mass storage tests I ran w/ the upstream kernel on SM8150 in the cover letter. Let me just share that here:

Test Parameters:
- Platform: Qualcomm SM8150
- bMaxBurst = 6
- USB req size = 256kB
- Num of USB reqs = 16
- USB Speed = Super-Speed
- Function Driver: Mass Storage (w/ ramdisk)
- Test Application: CrystalDiskMark

Results:

TXFIFO Depth = 3 max packets

Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------

Sequential|1 GB x     |
Read      |9 loops    | 193.60
	  |           | 195.86
          |           | 184.77
          |           | 193.60

-------------------------------------------

TXFIFO Depth = 6 max packets

Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------

Sequential|1 GB x     |
Read      |9 loops    | 287.35
	  |           | 304.94
          |           | 289.64
          |           | 293.61

-------------------------------------------

Quoted 13 lines

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 577

Quoted 9 lines

drivers/usb/dwc3/gadget.c +9 -0

+	if (!dwc->needs_fifo_resize)
+		return 0;
+
+	/* resize IN endpoints except ep0 */
+	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+		return 0;
+
+	/* Don't resize already resized IN endpoint */
+	if (dep->fifo_depth)

using fifo_depth as a flag seems flakey to me. What happens when someone in the future changes the behavior below and this doesn't apply anymore?

Quoted 3 lines

Also, why is this procedure called more than once for the same endpoint? Does that really happen?

I guess it can be considered a bug elsewhere (ie usb gadget or function driver) if this happens twice. Plus, if we decide to keep this in the dwc3 enable endpoint path, the DWC3_EP_ENABLED flag will ensure it's called only once as well. Its probably overkill to check fifo_depth here.

Quoted 12 lines

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 622

Quoted 9 lines

drivers/usb/dwc3/gadget.c +9 -0

+	if (remaining < fifo_size) {
+		if (remaining > 0)
+			fifo_size = remaining;
+		else
+			fifo_size = 0;
+	}
+
+	fifo_size += fifo;
+	fifo_size++;

why the increment?

This is to account for the last +1 in the equation from the DWC3 databook:
fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1 <- this one

Quoted 9 lines

Quoted 9 lines

drivers/usb/dwc3/gadget.c +3 -0

+	return 0;
+}
+
 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 {
 	const struct usb_ss_ep_comp_descriptor *comp_desc;

@@ -620,6 +731,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 	int			ret;
 

Quoted 8 lines

drivers/usb/dwc3/gadget.c static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) · line 736

Quoted 4 lines

drivers/usb/dwc3/gadget.c +3 -0

 	if (!(dep->flags & DWC3_EP_ENABLED)) {
+		ret = dwc3_gadget_resize_tx_fifos(dep);
+		if (ret)
+			return ret;

doesn't it look odd that you're resizing every fifo every time a new endpoint is enabled? Is there a better way to achieve this?

We're only resizing a single fifo per call, and clearing the previous fifo configuration upon receiving the set address. In the past, I know the change was to resize all fifos after receiving the set configuration packet. With that approach, I believe we saw issues with some function drivers that immediately queued a USB request during their set_alt() routine, followed by the dwc3 ep0 driver calling the TX fifo resize API.(as the tx fifo resize was executed after we delegated the set config packet to the USB composite)

One possibility around this was suggested above, something along the lines of:

usb_gadget_ep_enable_bulk(struct usb_gadget *, struct
usb_ep_alloc_desc *alloc_desc)

(please think of better names, I'm hopeless haha)

Hi,

Quoted 48 lines · Wesley Cheng

Quoted 11 lines · Felipe Balbi

Wesley Cheng <[email protected]> writes:

Hi,

Quoted 6 lines

Some devices have USB compositions which may require multiple endpoints that support EP bursting. HW defined TX FIFO sizes may not always be sufficient for these compositions. By utilizing flexible TX FIFO allocation, this allows for endpoints to request the required FIFO depth to achieve higher bandwidth. With some higher bMaxBurst configurations, using a larger TX FIFO size results in better TX throughput.

Quoted 4 lines

how much better? What's the impact? Got some real numbers of this running with upstream kernel? I guess mass storage gadget is the simplest one to test.

Hi Felipe,

Thanks for the input.

Sorry for not including the numbers in the patch itself, but I did mention the set of mass storage tests I ran w/ the upstream kernel on SM8150 in the cover letter. Let me just share that here:

Test Parameters:
- Platform: Qualcomm SM8150
- bMaxBurst = 6
- USB req size = 256kB
- Num of USB reqs = 16
- USB Speed = Super-Speed
- Function Driver: Mass Storage (w/ ramdisk)
- Test Application: CrystalDiskMark

Results:

TXFIFO Depth = 3 max packets

Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------

Sequential|1 GB x     |
Read      |9 loops    | 193.60
	  |           | 195.86
          |           | 184.77
          |           | 193.60

-------------------------------------------

TXFIFO Depth = 6 max packets

Quoted 8 lines

Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------

Sequential|1 GB x     |
Read      |9 loops    | 287.35
	  |           | 304.94
          |           | 289.64
          |           | 293.61

-------------------------------------------

awesome, thanks a lot for this :-) It's a considerable increase in your setup. My only fear here is that we may end up creating a situation where we can't allocate enough FIFO for all endpoints. This is, of course, a consequence of the fact that we enable one endpoint at a time.

Perhaps we could envision a way where function driver requests endpoints in bulk, i.e. combines all endpoint requirements into a single method call for gadget framework and, consequently, for UDC.

Quoted 16 lines

Quoted 16 lines

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 577

Quoted 9 lines

drivers/usb/dwc3/gadget.c +9 -0

+	if (!dwc->needs_fifo_resize)
+		return 0;
+
+	/* resize IN endpoints except ep0 */
+	if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+		return 0;
+
+	/* Don't resize already resized IN endpoint */
+	if (dep->fifo_depth)

using fifo_depth as a flag seems flakey to me. What happens when someone in the future changes the behavior below and this doesn't apply anymore?

Also, why is this procedure called more than once for the same endpoint? Does that really happen?

Quoted 4 lines

I guess it can be considered a bug elsewhere (ie usb gadget or function driver) if this happens twice. Plus, if we decide to keep this in the dwc3 enable endpoint path, the DWC3_EP_ENABLED flag will ensure it's called only once as well. Its probably overkill to check fifo_depth here.

We could add a dev_WARN_ONCE() just to catch any possible bugs elsewhere.

Quoted 12 lines

Quoted 12 lines

drivers/usb/dwc3/gadget.c static int dwc3_gadget_start_config(struct dwc3_ep *dep) · line 622

Quoted 9 lines

drivers/usb/dwc3/gadget.c +9 -0

+	if (remaining < fifo_size) {
+		if (remaining > 0)
+			fifo_size = remaining;
+		else
+			fifo_size = 0;
+	}
+
+	fifo_size += fifo;
+	fifo_size++;

why the increment?

Quoted 2 lines

This is to account for the last +1 in the equation from the DWC3 databook:
fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1 <- this one

great, could you add this detail as a comment so it doesn't look as cryptic? :-)

Quoted 17 lines

Quoted 9 lines

Quoted 9 lines

drivers/usb/dwc3/gadget.c +3 -0

+	return 0;
+}
+
 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 {
 	const struct usb_ss_ep_comp_descriptor *comp_desc;

@@ -620,6 +731,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 	int			ret;
 

Quoted 8 lines

drivers/usb/dwc3/gadget.c static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) · line 736

Quoted 4 lines

drivers/usb/dwc3/gadget.c +3 -0

 	if (!(dep->flags & DWC3_EP_ENABLED)) {
+		ret = dwc3_gadget_resize_tx_fifos(dep);
+		if (ret)
+			return ret;

doesn't it look odd that you're resizing every fifo every time a new endpoint is enabled? Is there a better way to achieve this?

Quoted 8 lines

We're only resizing a single fifo per call, and clearing the previous fifo configuration upon receiving the set address. In the past, I know the change was to resize all fifos after receiving the set configuration packet. With that approach, I believe we saw issues with some function drivers that immediately queued a USB request during their set_alt() routine, followed by the dwc3 ep0 driver calling the TX fifo resize API.(as the tx fifo resize was executed after we delegated the set config packet to the USB composite)

I don't remember seeing such an issue. Allocating FIFOs after we know the entire requirements would avoid another possible situation, that of dwc3 exausting FIFO space before it knows there are more enpdoints to enable.

One possibility around this was suggested above, something along the lines of:

usb_gadget_ep_enable_bulk(struct usb_gadget *, struct
usb_ep_alloc_desc *alloc_desc)

(please think of better names, I'm hopeless haha)

Quoted 11 lines

awesome, thanks a lot for this :-) It's a considerable increase in your setup. My only fear here is that we may end up creating a situation where we can't allocate enough FIFO for all endpoints. This is, of course, a consequence of the fact that we enable one endpoint at a time.

Perhaps we could envision a way where function driver requests endpoints in bulk, i.e. combines all endpoint requirements into a single method call for gadget framework and, consequently, for UDC.

Hi Felipe,

I agree...Resizing the txfifo is not as straightforward as it sounds :).
Would be interesting to see how this affects tput on other platforms as
well. We had a few discussions within our team, and came up with the logic implemented in this patch to reserve at least 1 txfifo per endpoint. Then we allocate any additional fifo space requests based on the remaining space left. That way we could avoid over allocating, but the trade off is that we may have unused EPs taking up fifo space.

I didn't consider branching out to changing the gadget framework, so let me take a look at your suggestion to see how it turns out.

Some devices have USB compositions which may require multiple endpoints that support EP bursting. HW defined TX FIFO sizes may not always be sufficient for these compositions. By utilizing flexible TX FIFO allocation, this allows for endpoints to request the required FIFO depth to achieve higher bandwidth. With some higher bMaxBurst configurations, using a larger TX FIFO size results in better TX throughput.

Ensure that one TX FIFO is reserved for every IN endpoint. This allows for the FIFO logic to prevent running out of FIFO space.

Signed-off-by Wesley Cheng <[email protected]>

---
 drivers/usb/dwc3/core.c   |   2 +
 drivers/usb/dwc3/core.h   |   8 +++
 drivers/usb/dwc3/ep0.c    |  37 +++++++++++-
 drivers/usb/dwc3/gadget.c | 115 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 161 insertions(+), 1 deletion(-)

drivers/usb/dwc3/core.c +2 -0

index edc17155cb2b..cca555493929 100644
@@ -1304,6 +1304,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
                                &tx_thr_num_pkt_prd);
        device_property_read_u8(dev, "snps,tx-max-burst-prd",
                                &tx_max_burst_prd);
+       dwc->needs_fifo_resize = device_property_read_bool(dev,
+                               "tx-fifo-resize");
 
        dwc->disable_scramble_quirk = device_property_read_bool(dev,
                                "snps,disable_scramble_quirk");

drivers/usb/dwc3/core.h +8 -0

index 4c171a8e215f..ce0bf288b6ac 100644
@@ -675,6 +675,7 @@ struct dwc3_event_buffer {
  *             isochronous START TRANSFER command failure workaround
  * @start_cmd_status: the status of testing START TRANSFER command with
  *             combo_num = 'b00
+ * @fifo_depth: allocated TXFIFO depth
  */
 struct dwc3_ep {
        struct usb_ep           endpoint;

@@ -727,6 +728,7 @@ struct dwc3_ep {
        /* For isochronous START TRANSFER workaround only */
        u8                      combo_num;
        int                     start_cmd_status;
+       int                     fifo_depth;
 };
 
 enum dwc3_phy {

@@ -1004,6 +1006,7 @@ struct dwc3_scratchpad_array {
  *     1       - utmi_l1_suspend_n
  * @is_fpga: true when we are using the FPGA board
  * @pending_events: true when we have pending IRQs to be handled
+ * @needs_fifo_resize: not all users might want fifo resizing, flag it
  * @pullups_connected: true when Run/Stop bit is set
  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
  * @three_stage_setup: set if we perform a three phase setup

@@ -1044,6 +1047,8 @@ struct dwc3_scratchpad_array {
  * @dis_metastability_quirk: set to disable metastability quirk.
  * @imod_interval: set the interrupt moderation interval in 250ns
  *                 increments or 0 to disable.
+ * @last_fifo_depth: total TXFIFO depth of all enabled USB IN/INT endpoints
+ * @num_ep_resized: the number of TX FIFOs that have already been resized
  */
 struct dwc3 {
        struct work_struct      drd_work;

@@ -1204,6 +1209,7 @@ struct dwc3 {
        unsigned                is_utmi_l1_suspend:1;
        unsigned                is_fpga:1;
        unsigned                pending_events:1;
+       unsigned                needs_fifo_resize:1;
        unsigned                pullups_connected:1;
        unsigned                setup_packet_pending:1;
        unsigned                three_stage_setup:1;

@@ -1236,6 +1242,8 @@ struct dwc3 {
        unsigned                dis_metastability_quirk:1;
 
        u16                     imod_interval;
+       int                     last_fifo_depth;
+       int                     num_ep_resized;
 };
 
 #define INCRX_BURST_MODE 0

drivers/usb/dwc3/ep0.c +36 -1

index 6dee4dabc0a4..76db9b530861 100644
@@ -601,8 +601,9 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 {
        enum usb_device_state state = dwc->gadget.state;
        u32 cfg;
-       int ret;
+       int ret, num, size;
        u32 reg;
+       struct dwc3_ep *dep;
 
        cfg = le16_to_cpu(ctrl->wValue);
 

@@ -611,6 +612,40 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
                return -EINVAL;
 
        case USB_STATE_ADDRESS:
+               /*
+                * If tx-fifo-resize flag is not set for the controller, then
+                * do not clear existing allocated TXFIFO since we do not
+                * allocate it again in dwc3_gadget_resize_tx_fifos
+                */
+               if (dwc->needs_fifo_resize) {
+                       /* Read ep0IN related TXFIFO size */
+                       dep = dwc->eps[1];
+                       size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+                       if (dwc3_is_usb31(dwc))
+                               dep->fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+                       else
+                               dep->fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
+
+                       dwc->last_fifo_depth = dep->fifo_depth;
+                       /* Clear existing TXFIFO for all IN eps except ep0 */
+                       for (num = 3; num < min_t(int, dwc->num_eps,
+                               DWC3_ENDPOINTS_NUM); num += 2) {
+                               dep = dwc->eps[num];
+                               /* Don't change TXFRAMNUM on usb31 version */
+                               size = dwc3_is_usb31(dwc) ?
+                                       dwc3_readl(dwc->regs,
+                                                  DWC3_GTXFIFOSIZ(num >> 1)) &
+                                                  DWC31_GTXFIFOSIZ_TXFRAMNUM :
+                                                  0;
+
+                               dwc3_writel(dwc->regs,
+                                           DWC3_GTXFIFOSIZ(num >> 1),
+                                           size);
+                               dep->fifo_depth = 0;
+                       }
+                       dwc->num_ep_resized = 0;
+               }
+
                ret = dwc3_ep0_delegate_req(dwc, ctrl);
                /* if the cfg matches and the cfg is non zero */
                if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {

drivers/usb/dwc3/gadget.c +115 -1

index 00746c2848c0..777badf3e85d 100644
@@ -540,6 +540,117 @@ static int dwc3_gadget_start_config(struct dwc3_ep *dep)
        return 0;
 }
 
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
+{
+       struct dwc3 *dwc = dep->dwc;
+       int ram1_depth, mdwidth, fifo_0_start, tmp, num_in_ep;
+       int min_depth, remaining, fifo_size, mult = 1, fifo, max_packet = 1024;
+
+       if (!dwc->needs_fifo_resize)
+               return 0;
+
+       /* resize IN endpoints except ep0 */
+       if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+               return 0;
+
+       /* Don't resize already resized IN endpoint */
+       if (dep->fifo_depth)
+               return 0;
+
+       ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+       mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+       /* MDWIDTH is represented in bits, we need it in bytes */
+       mdwidth >>= 3;
+
+       if (((dep->endpoint.maxburst > 1) &&
+                       usb_endpoint_xfer_bulk(dep->endpoint.desc))
+                       || usb_endpoint_xfer_isoc(dep->endpoint.desc))
+               mult = 3;
+
+       if ((dep->endpoint.maxburst > 6) &&
+                       usb_endpoint_xfer_bulk(dep->endpoint.desc)
+                       && dwc3_is_usb31(dwc))
+               mult = 6;
+
+       /* FIFO size for a single buffer */
+       fifo = (max_packet + mdwidth)/mdwidth;
+       fifo++;
+
+       /* Calculate the number of remaining EPs w/o any FIFO */
+       num_in_ep = dwc->num_eps/2;
+       num_in_ep -= dwc->num_ep_resized;
+       /* Ignore EP0 IN */
+       num_in_ep--;
+
+       /* Reserve at least one FIFO for the number of IN EPs */
+       min_depth = num_in_ep * (fifo+1);
+       remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
+
+       /* We've already reserved 1 FIFO per EP, so check what we can fit in
+        * addition to it.  If there is not enough remaining space, allocate
+        * all the remaining space to the EP.
+        */
+       fifo_size = (mult-1) * fifo;
+       if (remaining < fifo_size) {
+               if (remaining > 0)
+                       fifo_size = remaining;
+               else
+                       fifo_size = 0;
+       }
+
+       fifo_size += fifo;
+       fifo_size++;
+       dep->fifo_depth = fifo_size;
+
+       /* Check if TXFIFOs start at non-zero addr */
+       tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+       fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+       fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+       if (dwc3_is_usb31(dwc))
+               dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+       else
+               dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+
+       /* Check fifo size allocation doesn't exceed available RAM size. */
+       if (dwc->last_fifo_depth >= ram1_depth) {
+               dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
+                               (dwc->last_fifo_depth * mdwidth), ram1_depth,
+                               dep->endpoint.name, fifo_size);
+               if (dwc3_is_usb31(dwc))
+                       fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+               else
+                       fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+               dwc->last_fifo_depth -= fifo_size;
+               dep->fifo_depth = 0;
+               return -ENOMEM;
+       }
+
+       dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
+       dwc->num_ep_resized++;
+       return 0;
+}
+
 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 {
        const struct usb_ss_ep_comp_descriptor *comp_desc;

@@ -620,6 +731,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
        int                     ret;
 
        if (!(dep->flags & DWC3_EP_ENABLED)) {
+               ret = dwc3_gadget_resize_tx_fifos(dep);
+               if (ret)
+                       return ret;
+
                ret = dwc3_gadget_start_config(dep);
                if (ret)
                        return ret;
--

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

Quoted 11 lines · Wesley Cheng

Some devices have USB compositions which may require multiple endpoints that support EP bursting. HW defined TX FIFO sizes may not always be sufficient for these compositions. By utilizing flexible TX FIFO allocation, this allows for endpoints to request the required FIFO depth to achieve higher bandwidth. With some higher bMaxBurst configurations, using a larger TX FIFO size results in better TX throughput.

Ensure that one TX FIFO is reserved for every IN endpoint. This allows for the FIFO logic to prevent running out of FIFO space.

You may do this for only allocated endpoints, but you need override default .match_ep
API. See cdns3/gadget.c and cdns3/ep0.c as an example.

Peter

Thank you for your input. I've actually considered doing some matching/resizing in the .match_ep route as well, but it doesn't work well for situations where multiple configurations are in play. The reason being that if you look at the epautoconf APIs, the configfs driver will use the usb_ep_autoconfig_reset() to reset the endpoints claimed between initialization of each configuration. This means that the epautoconf driver expects to re-use the usb_endpoints:

static int configfs_composite_bind(struct usb_gadget *gadget,
struct usb_gadget_driver *gdriver)
{
...

/* Go through all configs, attach all functions */ list_for_each_entry(c, &gi-

Quoted 1 line

cdev.configs, list) { ...

list_for_each_entry_safe(f, tmp, &cfg->func_list, list) {
	list_del(&f->list);
	ret = usb_add_function(c, f);
	if (ret) {
		list_add(&f->list, &cfg->func_list);
		goto err_purge_funcs;
	}
}

usb_ep_autoconfig_reset(cdev->gadget);
}

So in this situation, I wouldn't want the dwc3 gadget driver to assign a different dwc3 ep for endpoints in each configuration, when we know that only one set of EPs will be active when the host chooses. I hope I understood your feedback correctly, and definitely appreciate the input!