RZN1 USB Host support

Convert Renesas PCI bridge bindings documentation to json-schema.

Signed-off-by Herve Codina <[email protected]>

---
 .../devicetree/bindings/pci/pci-rcar-gen2.txt |  84 ----------
 .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 156 ++++++++++++++++++
 2 files changed, 156 insertions(+), 84 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
 create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file +14 -0

new file mode 100644
index 000000000000..494eb975c146
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas AHB to PCI bridge
+
+maintainers:
+  - Marek Vasut <[email protected]>
+  - Yoshihiro Shimoda <[email protected]>
+
+description: |
+  This is the bridge used internally to connect the USB controllers to the

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file +11 -0

+          - enum:
+              - renesas,pci-r8a7742      # RZ/G1H
+              - renesas,pci-r8a7743      # RZ/G1M
+              - renesas,pci-r8a7744      # RZ/G1N
+              - renesas,pci-r8a7745      # RZ/G1E
+              - renesas,pci-r8a7790      # R-Car H2
+              - renesas,pci-r8a7791      # R-Car M2-W
+              - renesas,pci-r8a7793      # R-Car M2-N
+              - renesas,pci-r8a7794      # R-Car E2
+          - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+

Quoted 34 lines · Herve Codina

Convert Renesas PCI bridge bindings documentation to json-schema.

Signed-off-by Herve Codina <[email protected]>

---
 .../devicetree/bindings/pci/pci-rcar-gen2.txt |  84 ----------
 .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 156 ++++++++++++++++++
 2 files changed, 156 insertions(+), 84 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
 create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file +18 -0

new file mode 100644
index 000000000000..494eb975c146
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas AHB to PCI bridge
+
+maintainers:
+  - Marek Vasut <[email protected]>
+  - Yoshihiro Shimoda <[email protected]>
+
+description: |
+  This is the bridge used internally to connect the USB controllers to the
+  AHB. There is one bridge instance per USB port connected to the internal
+  OHCI and EHCI controllers.
+
+allOf:

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml line 24

Quoted 6 lines

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file +6 -0

+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:

Don't need oneOf with only 1 entry. Otherwise,

Reviewed-by Rob Herring <[email protected]>

Quoted 11 lines

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml new file +11 -0

+          - enum:
+              - renesas,pci-r8a7742      # RZ/G1H
+              - renesas,pci-r8a7743      # RZ/G1M
+              - renesas,pci-r8a7744      # RZ/G1N
+              - renesas,pci-r8a7745      # RZ/G1E
+              - renesas,pci-r8a7790      # R-Car H2
+              - renesas,pci-r8a7791      # R-Car M2-W
+              - renesas,pci-r8a7793      # R-Car M2-N
+              - renesas,pci-r8a7794      # R-Car E2
+          - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+

Convert Renesas PCI bridge bindings documentation to json-schema.

Signed-off-by Herve Codina <[email protected]>

Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of one.

Signed-off-by Herve Codina <[email protected]>

---
 .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 43 ++++++++++++++++---
 1 file changed, 37 insertions(+), 6 deletions(-)

Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of one.

Signed-off-by Herve Codina <[email protected]>

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +9 -0

@@ -113,6 +113,37 @@ required:
   - "#size-cells"
   - "#interrupt-cells"
 
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - renesas,pci-rzn1
+
+then:
+  properties:

Hi Hervé,

Quoted 7 lines · Herve Codina

Add internal PCI bridge support for the r9a06g032 SOC. The Renesas RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of one.

Signed-off-by Herve Codina <[email protected]>

Thanks for your patch!

Quoted 21 lines

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +15 -0

@@ -113,6 +113,37 @@ required:
   - "#size-cells"
   - "#interrupt-cells"
 
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - renesas,pci-rzn1
+
+then:
+  properties:
+    clocks:
+      items:
+        - description: Internal bus clock (AHB) for HOST
+        - description: Internal bus clock (AHB) Power Management
+        - description: PCI clock for USB subsystem
+    clock-names:

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml required: · line 134

Quoted 4 lines

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +4 -0

+      items:
+        - const: hclk_usbh
+        - const: hclk_usbpm
+        - const: clk_pci_usb  

These are the provider names.
I think they should use the consumer names: usb_hclkh, usb_hclkpm, and usb_pciclk.

The rest looks good to me.

Add Renesas RZ/N1 SOCs family support to the Renesas R-Car gen2 PCI bridge driver.
The Renesas RZ/N1 SOCs internal PCI bridge is comptible with the one available in the R-Car Gen2 family.
Tested with the RZ/N1D (R9A06G032) SOC.

Signed-off-by Herve Codina <[email protected]>

---
 drivers/pci/controller/pci-rcar-gen2.c | 1 +
 1 file changed, 1 insertion(+)

drivers/pci/controller/pci-rcar-gen2.c +1 -0

index 35804ea394fd..839695791757 100644
@@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = {
 	{ .compatible = "renesas,pci-r8a7791", },
 	{ .compatible = "renesas,pci-r8a7794", },
 	{ .compatible = "renesas,pci-rcar-gen2", },
+	{ .compatible = "renesas,pci-rzn1", },
 	{ },
 };
 

Signature · 1 line

2.35.1

Quoted 5 lines · Herve Codina

Add Renesas RZ/N1 SOCs family support to the Renesas R-Car gen2 PCI bridge driver.
The Renesas RZ/N1 SOCs internal PCI bridge is comptible with the one available in the R-Car Gen2 family.
Tested with the RZ/N1D (R9A06G032) SOC.

Nits (only address if you have some other reason to repost this series):

- Subject claims this adds "support," which suggests that this adds some piece of new functionality. But it adds no new functionality, it merely adds a new compatible string. I would say "Add RZ/N1 SOC compatible string"

- Add blank lines between paragraphs

- Rewrap paragraphs to fill 75 characters

- s/comptible/compatible/

- s/R-Car gen2/R-Car Gen2/ to write this consistently instead of capitalizing "Gen2" sometimes but not others

PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs. Without these configs, the clocks used by the PCI bridge are not enabled and so accessing the devices leads to a kernel crash:

  [    0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848

Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1

Signed-off-by Herve Codina <[email protected]>

Quoted 5 lines · Herve Codina

PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs. Without these configs, the clocks used by the PCI bridge are not enabled and so accessing the devices leads to a kernel crash:

  [    0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848

Quoted 3 lines

Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1

Signed-off-by Herve Codina <[email protected]>

Reviewed-by Geert Uytterhoeven <[email protected]>

i.e. will queue in renesas-devel for v5.19.

Quoted 6 lines · On Wed, 27 Apr 2022 16:58:07 +0200 Geert Uytterhoeven <[email protected]>…

Quoted 5 lines · Herve Codina

PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs. Without these configs, the clocks used by the PCI bridge are not enabled and so accessing the devices leads to a kernel crash:

  [    0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848

Quoted 6 lines

Quoted 3 lines

Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1

Signed-off-by Herve Codina <[email protected]>

Reviewed-by Geert Uytterhoeven <[email protected]>

i.e. will queue in renesas-devel for v5.19.

I plan to send a v4 of this series.

As this patch (4/8) and the following one (5/8) will be queued for v5.19, I plan to remove them from the v4 version of the series.

Is that ok for you or do you prefer to still have them in v4 ?

Hi Hervé,

Quoted 21 lines · Herve Codina

Quoted 6 lines · On Wed, 27 Apr 2022 16:58:07 +0200 Geert Uytterhoeven <[email protected]>…

Quoted 5 lines · Herve Codina

PM and PM_GENERIC_DOMAINS configs are required for RZ/N1 SOCs. Without these configs, the clocks used by the PCI bridge are not enabled and so accessing the devices leads to a kernel crash:

  [    0.832958] Unhandled fault: external abort on non-linefetch (0x1008) at 0x90b5f848

Quoted 6 lines

Quoted 3 lines

Select PM and PM_GENERIC_DOMAINS for ARCH_RZN1

Signed-off-by Herve Codina <[email protected]>

Reviewed-by Geert Uytterhoeven <[email protected]>

i.e. will queue in renesas-devel for v5.19.

I plan to send a v4 of this series.

As this patch (4/8) and the following one (5/8) will be queued for v5.19, I plan to remove them from the v4 version of the series.

Quoted 2 lines

Is that ok for you or do you prefer to still have them in v4 ?

As these two patches are not strictly related to adding PCI support, but they are dependencies, I will queue them separately. Hence you do not need to include them in v5.

Without '#power-domain-cells' property, power-domains cannot be used. This property is noted required in the device-tree binding.

Add '#power-domain-cells' as needed.

Signed-off-by Herve Codina <[email protected]>

Add the device node for the r9a06g032 internal PCI bridge device.

Signed-off-by Herve Codina <[email protected]>

arch/arm/boot/dts/r9a06g032.dtsi +0 -0

@@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
                        interrupts =

arch/arm/boot/dts/r9a06g032.dtsi gic: interrupt-controller@44101000 { · line 216

Quoted 8 lines

arch/arm/boot/dts/r9a06g032.dtsi +2 -0

@@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
                        interrupts =
                                <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
                };
+
+               pci_usb: pci@40030000 {

Hi Hervé,

On Thu, Apr 28, 2022 at 11:49 AM Geert Uytterhoeven <[email protected]> wrote:

Quoted 8 lines

arch/arm/boot/dts/r9a06g032.dtsi gic: interrupt-controller@44101000 { · line 216

Quoted 8 lines

arch/arm/boot/dts/r9a06g032.dtsi +2 -0

@@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
                        interrupts =
                                <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
                };
+
+               pci_usb: pci@40030000 {  

Please preserve sort order (by unit address).

Hi Hervé

Quoted 3 lines · Herve Codina

Add the device node for the r9a06g032 internal PCI bridge device.

Signed-off-by Herve Codina <[email protected]>

Thanks for your patch!

Quoted 4 lines

arch/arm/boot/dts/r9a06g032.dtsi +0 -0

@@ -212,6 +212,35 @@ gic: interrupt-controller@44101000 {
                        interrupts =

arch/arm/boot/dts/r9a06g032.dtsi gic: interrupt-controller@44101000 { · line 222

Quoted 10 lines

arch/arm/boot/dts/r9a06g032.dtsi +8 -0

                                <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
                };
+
+               pci_usb: pci@40030000 {
+                       compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
+                       device_type = "pci";
+                       clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+                                <&sysctrl R9A06G032_HCLK_USBPM>,
+                                <&sysctrl R9A06G032_CLK_PCI_USB>;
+                       clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";  

The clock names need an update, cfr. my comment on the bindings.

The rest LGTM, so with the above fixed:

Reviewed-by Geert Uytterhoeven <[email protected]>

Define the r9a06g032 generic part of the USB PHY device node.

Signed-off-by Herve Codina <[email protected]>

---
 arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/boot/dts/r9a06g032.dtsi +0 -0

index 33581f0c55c4..58af07eb75c9 100644

Quoted 15 lines

Define the r9a06g032 generic part of the USB PHY device node.

Signed-off-by Herve Codina <[email protected]>

---
 arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/boot/dts/r9a06g032.dtsi +0 -0

index 33581f0c55c4..58af07eb75c9 100644
@@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
 		clock-frequency = <0>;
 	};
 

arch/arm/boot/dts/r9a06g032.dtsi ext_rtc_clk: extrtcclk { · line 62

Quoted 1 line

arch/arm/boot/dts/r9a06g032.dtsi +1 -0

+	usbphy: usbphy {

I think the node name should be "usb-phy"...

[...]

On 4/23/22 12:09 PM, Sergey Shtylyov wrote:

[...]

Quoted 15 lines

Quoted 15 lines

Define the r9a06g032 generic part of the USB PHY device node.

Signed-off-by Herve Codina <[email protected]>

---
 arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/boot/dts/r9a06g032.dtsi +0 -0

index 33581f0c55c4..58af07eb75c9 100644
@@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
 		clock-frequency = <0>;
 	};
 

Quoted 3 lines

arch/arm/boot/dts/r9a06g032.dtsi ext_rtc_clk: extrtcclk { · line 62

Quoted 1 line

arch/arm/boot/dts/r9a06g032.dtsi +1 -0

+	usbphy: usbphy {  

I think the node name should be "usb-phy"...

It's not my thinking alone, the DT spec documents "usb-phy" in section 2.2.2. :-)

Define the r9a06g032 generic part of the USB PHY device node.

Signed-off-by Herve Codina <[email protected]>

Hi Hervé,

Quoted 3 lines · Herve Codina

Define the r9a06g032 generic part of the USB PHY device node.

Signed-off-by Herve Codina <[email protected]>

Thanks for your patch!

Quoted 6 lines

arch/arm/boot/dts/r9a06g032.dtsi +0 -0

@@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
                clock-frequency = <0>;
        };
 

arch/arm/boot/dts/r9a06g032.dtsi ext_rtc_clk: extrtcclk { · line 62

Quoted 1 line

arch/arm/boot/dts/r9a06g032.dtsi +1 -0

+       usbphy: usbphy {  

Please preserve sort order (by node name).

arch/arm/boot/dts/r9a06g032.dtsi ext_rtc_clk: extrtcclk { · line 70

Quoted 9 lines

arch/arm/boot/dts/r9a06g032.dtsi +5 -0

+               #phy-cells = <0>;
+               compatible = "usb-nop-xceiv";
+               status = "disabled";
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <1>;  

The rest LGTM, so with the above fixed:

Reviewed-by Geert Uytterhoeven <[email protected]>

Describe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device.

Signed-off-by Herve Codina <[email protected]>