arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs
v2 cover arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs
From: Bartosz Golaszewski <[email protected]>
This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
board: I2C, SPI and the Bluetooth and GNSS UART ports.
v1 -> v2:
- uart17 is the Bluetooth port, not GNSS
- add uart12 for GNSS too in that case
Bartosz Golaszewski (4):
arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride
arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride
arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for
sa8775p-ride
arm64: dts: qcom: sa8775p: add the BT high-speed UART for sa8775p-ride
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 100 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 87 +++++++++++++++++++ 2 files changed, 187 insertions(+)
Signature · 1 line
2.37.2
PATCH v2 1/4 arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride
From: Bartosz Golaszewski <[email protected]>
Add the i2c node for the interface exposed on the sa8775p-ride board.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 +++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++++++++++++++++++ 2 files changed, 53 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +19 -0
@@ -13,6 +13,7 @@ / { aliases { serial0 = &uart10; + i2c18 = &i2c18; }; chosen {
@@ -20,10 +21,21 @@ chosen { }; }; +&i2c18 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; };
@@ -33,6 +45,13 @@ qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3"; }; + + qup_i2c18_default: qup-i2c18-state { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart10 {
arch/arm64/boot/dts/qcom/sa8775p.dtsi +34 -0
@@ -491,6 +491,40 @@ &clk_virt SLAVE_QUP_CORE_1 0>, }; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x8c0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0x0>; + status = "disabled"; + + i2c18: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x890000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 + &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 + &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
Signature · 1 line
2.37.2
PATCH v2 2/4 arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the SPI node for the interface exposed on the sa8775p-ride board.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++ 2 files changed, 35 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +14 -0
@@ -14,6 +14,7 @@ / { aliases { serial0 = &uart10; i2c18 = &i2c18; + spi16 = &spi16; }; chosen {
@@ -40,12 +41,25 @@ &sleep_clk { clock-frequency = <32764>; }; +&spi16 { + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &tlmm { qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3"; }; + qup_spi16_default: qup-spi16-state { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c18_default: qup-i2c18-state { pins = "gpio95", "gpio96"; function = "qup2_se4";
arch/arm64/boot/dts/qcom/sa8775p.dtsi +21 -0
@@ -503,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 { iommus = <&apps_smmu 0x5a3 0x0>; status = "disabled"; + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x888000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 + &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 + &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x890000 0x0 0x4000>;
Signature · 1 line
2.37.2
PATCH v2 3/4 arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the serial port connected to the GNSS on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 15 ++++++++++ 2 files changed, 49 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +34 -0
@@ -13,6 +13,7 @@ / { aliases { serial0 = &uart10; + serial1 = &uart12; i2c18 = &i2c18; spi16 = &spi16; };
@@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state { drive-strength = <2>; bias-pull-up; }; + + qup_uart12_cts: qup-uart12-cts-state { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup_uart12_rts-state { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup_uart12_tx-state { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup_uart12_rx-state { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; }; &uart10 {
@@ -75,6 +100,15 @@ &uart10 { status = "okay"; }; +&uart12 { + pinctrl-0 = <&qup_uart12_cts>, + <&qup_uart12_rts>, + <&qup_uart12_tx>, + <&qup_uart12_rx>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };
arch/arm64/boot/dts/qcom/sa8775p.dtsi +15 -0
@@ -489,6 +489,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>, operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; + + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_2: geniqup@8c0000 {
Signature · 1 line
2.37.2
Re: [PATCH v2 3/4] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride
Quoted 75 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the serial port connected to the GNSS on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 15 ++++++++++ 2 files changed, 49 insertions(+)arch/arm64/boot/dts/qcom/sa8775p-ride.dts +34
-0@@ -13,6 +13,7 @@ / { aliases { serial0 = &uart10; + serial1 = &uart12; i2c18 = &i2c18; spi16 = &spi16; };@@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state { drive-strength = <2>; bias-pull-up; }; + + qup_uart12_cts: qup-uart12-cts-state { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup_uart12_rts-state { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup_uart12_tx-state { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup_uart12_rx-state { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; }; &uart10 {@@ -75,6 +100,15 @@ &uart10 { status = "okay"; }; +&uart12 { + pinctrl-0 = <&qup_uart12_cts>, + <&qup_uart12_rts>, + <&qup_uart12_tx>, + <&qup_uart12_rx>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };arch/arm64/boot/dts/qcom/sa8775p.dtsi +0
-0
arch/arm64/boot/dts/qcom/sa8775p.dtsi &clk_virt SLAVE_QUP_CORE_1 0>, · line 496
Quoted 8 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +5
-0@@ -489,6 +489,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>, operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; + + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
Please disregard this series, I've just noticed I didn't stage the change to the interrupt number here which is wrong. And I need to fix the underscores in node names too.
Bart
Quoted 16 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +10
-1+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_2: geniqup@8c0000 { --2.37.2
Re: [PATCH v2 3/4] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride
Quoted 80 lines · Bartosz Golaszewski
Quoted 79 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the serial port connected to the GNSS on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 15 ++++++++++ 2 files changed, 49 insertions(+)arch/arm64/boot/dts/qcom/sa8775p-ride.dts +34
-0@@ -13,6 +13,7 @@ / { aliases { serial0 = &uart10; + serial1 = &uart12; i2c18 = &i2c18; spi16 = &spi16; };@@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state { drive-strength = <2>; bias-pull-up; }; + + qup_uart12_cts: qup-uart12-cts-state { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup_uart12_rts-state { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup_uart12_tx-state { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup_uart12_rx-state { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; }; &uart10 {@@ -75,6 +100,15 @@ &uart10 { status = "okay"; }; +&uart12 { + pinctrl-0 = <&qup_uart12_cts>, + <&qup_uart12_rts>, + <&qup_uart12_tx>, + <&qup_uart12_rx>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };arch/arm64/boot/dts/qcom/sa8775p.dtsi +1
-0@@ -489,6 +489,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>, operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; +
Quoted 8 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi &clk_virt SLAVE_QUP_CORE_1 0>, · line 496
Quoted 4 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +4
-0+ uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;Please disregard this series, I've just noticed I didn't stage the change to the interrupt number here which is wrong. And I need to fix the underscores in node names too.
Generally it would be "nicer" if you split adding the nodes in the SoC and device DTs as well, since you're already resending..
Konrad
Quoted 19 lines
Bart
Quoted 16 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +10
-1+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_2: geniqup@8c0000 { --2.37.2
PATCH v2 4/4 arm64: dts: qcom: sa8775p: add the BT high-speed UART for sa8775p-ride
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add the serial port connected to the Bluetooth controller on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>
--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 17 ++++++++++++ 2 files changed, 50 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +33 -0
@@ -14,6 +14,7 @@ / { aliases { serial0 = &uart10; serial1 = &uart12; + serial2 = &uart17; i2c18 = &i2c18; spi16 = &spi16; };
@@ -89,6 +90,29 @@ qup_uart12_tx: qup_uart12_tx-state { qup_uart12_rx: qup_uart12_rx-state { pins = "gpio55"; function = "qup1_se5"; + }; + + qup_uart17_cts: qup-uart17-cts-state { + pins = "gpio91"; + function = "qup2_se3"; + bias-disable; + }; + + qup_uart17_rts: qup0_uart17_rts-state { + pins = "gpio92"; + function = "qup2_se3"; + bias-pull-down; + }; + + qup_uart17_tx: qup0_uart17_tx-state { + pins = "gpio93"; + function = "qup2_se3"; + bias-pull-up; + }; + + qup_uart17_rx: qup0_uart17_rx-state { + pins = "gpio94"; + function = "qup2_se3"; bias-pull-down; }; };
@@ -109,6 +133,15 @@ &uart12 { status = "okay"; }; +&uart17 { + pinctrl-0 = <&qup_uart17_cts>, + <&qup_uart17_rts>, + <&qup_uart17_tx>, + <&qup_uart17_rx>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };
arch/arm64/boot/dts/qcom/sa8775p.dtsi +17 -0
@@ -539,6 +539,23 @@ &config_noc SLAVE_QUP_2 0>, status = "disabled"; }; + uart17: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x88c000 0x0 0x4000>; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 + &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x890000 0x0 0x4000>;
Signature · 1 line
2.37.2