Enable Power Modes Support for SAMA7D65 SoC

Add SAMA7D65 DDR3phy compatible to DT bindings documentation

From: Ryan Wanner <[email protected]>

Add SAMA7D65 SFRBU compatible string to DT bindings documentation

Signed-off-by Ryan Wanner <[email protected]>

---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
 1 file changed, 2 insertions(+)

Add SAMA7D65 SFRBU compatible string to DT bindings documentation

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTC compatible to DT bindings documentation.

Signed-off-by Ryan Wanner <[email protected]>

---
 .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml         | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

From: Ryan Wanner <[email protected]>

Add SAMA7D65 RTT compatible to DT bindings documentation.

Signed-off-by Ryan Wanner <[email protected]>

---
 Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 1 +
 1 file changed, 1 insertion(+)

From: Ryan Wanner <[email protected]>

Add PM support to SAMA7D65 SoC.

Signed-off-by Ryan Wanner <[email protected]>

---
 arch/arm/mach-at91/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-at91/Kconfig +0 -0

index 04bd91c72521..f3ff1220c0fb 100644

arch/arm/mach-at91/Kconfig +0 -0

 	select SOC_SAMA7
 	help
 	  Select this if you are using one of Microchip's SAMA7D65 family SoC.

From: Ryan Wanner <[email protected]>

Add support for SAMA7D65 new compatible strings in pm.c file for wakeup source IDs and PMC.
This is the first bits of PM for this new SoC. PM depends on other patches.

Signed-off-by Ryan Wanner <[email protected]>

[[email protected]: split patch and address only the pm.c changes]

Signed-off-by Nicolas Ferre <[email protected]>

---
  arch/arm/mach-at91/pm.c | 8 ++++++--
  1 file changed, 6 insertions(+), 2 deletions(-)

arch/arm/mach-at91/pm.c +4 -1

index 6c3e6aa22606..39644703244d 100644
@@ -222,13 +222,16 @@ static const struct of_device_id sam9x60_ws_ids[] = {
  	{ /* sentinel */ }
  };
 
-static const struct of_device_id sama7g5_ws_ids[] = {
+static const struct of_device_id sama7_ws_ids[] = {
+	{ .compatible = "microchip,sama7d65-rtc",	.data = &ws_info[1] },
  	{ .compatible = "microchip,sama7g5-rtc",	.data = &ws_info[1] },
  	{ .compatible = "microchip,sama7g5-ohci",	.data = &ws_info[2] },
  	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
  	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
  	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
+	{ .compatible = "microchip,sama7d65-sdhci",	.data = &ws_info[3] },
  	{ .compatible = "microchip,sama7g5-sdhci",	.data = &ws_info[3] },
+	{ .compatible = "microchip,sama7d65-rtt",	.data = &ws_info[4] },
  	{ .compatible = "microchip,sama7g5-rtt",	.data = &ws_info[4] },
  	{ /* sentinel */ }
  };

arch/arm/mach-at91/pm.c +1 -1

  	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
  	{ /* sentinel */ },
  };

@@ -1672,7 +1676,7 @@ void __init sama7_pm_init(void)
  	at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
  	at91_pm_init(NULL);
 
-	soc_pm.ws_ids = sama7g5_ws_ids;
+	soc_pm.ws_ids = sama7_ws_ids;
  	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
 
  	soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);

From: Ryan Wanner <[email protected]>

Add config check that enables Backup mode for SAMA7D65 SoC.

Add SHDWC_SR read to clear the status bits once finished exiting backup mode. This is only for SAMA7D65 SoCs. The SHDWC status register needs to be cleared after exiting backup mode to clear the wake up pin status.

Signed-off-by Ryan Wanner <[email protected]>

---
  arch/arm/mach-at91/pm.c | 9 ++++++++-
  1 file changed, 8 insertions(+), 1 deletion(-)

arch/arm/mach-at91/pm.c +5 -0

index 39644703244d..d82a507bc8da 100644
@@ -647,6 +647,11 @@ static void at91_pm_suspend(suspend_state_t state)
  		at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
  					     &at91_pm_suspend_in_sram,
  					     at91_pm_suspend_in_sram_sz);
+
+		if (IS_ENABLED(CONFIG_SOC_SAMA7D65))
+			/* SHDWC.SR */
+			readl(soc_pm.data.shdwc + 0x08);
+
  	} else {
  		at91_suspend_finish(0);
  	}

arch/arm/mach-at91/pm.c +2 -1

  }
 
 

@@ -1065,7 +1071,8 @@ static int __init at91_pm_backup_init(void)
  	int ret = -ENODEV, located = 0;
 
  	if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
-	    !IS_ENABLED(CONFIG_SOC_SAMA7G5))
+	    !IS_ENABLED(CONFIG_SOC_SAMA7G5) &&
+	    !IS_ENABLED(CONFIG_SOC_SAMA7D65))
  		return -EPERM;
 
  	if (!at91_is_pm_mode_active(AT91_PM_BACKUP))

From: Ryan Wanner <[email protected]>

Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes.

Signed-off-by Ryan Wanner <[email protected]>

---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 35 +++++++++++++++++++++++
 1 file changed, 35 insertions(+)

arch/arm/boot/dts/microchip/sama7d65.dtsi +10 -0

index 92a5347e35b5..c10cc3558efd 100644
@@ -47,12 +47,37 @@ slow_xtal: clock-slowxtal {
 		};
 	};
 
+	ns_sram: sram@100000 {
+		compatible = "mmio-sram";
+		reg = <0x100000 0x20000>;
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		securam: sram@e0000800 {
+			compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram";

arch/arm/boot/dts/microchip/sama7d65.dtsi +15 -0

+			reg = <0xe0004000 0x4000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
 		pioa: pinctrl@e0014000 {
 			compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
 			reg = <0xe0014000 0x800>;

@@ -190,6 +215,16 @@ i2c10: i2c@600 {
 			};
 		};
 
+		uddrc: uddrc@e3800000 {
+			compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
+			reg = <0xe3800000 0x4000>;
+		};
+
+		ddr3phy: ddr3phy@e3804000 {
+			compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
+			reg = <0xe3804000 0x1000>;
+		};
+
 		gic: interrupt-controller@e8c11000 {
 			compatible = "arm,cortex-a7-gic";
 			reg = <0xe8c11000 0x1000>,

From: Ryan Wanner <[email protected]>

Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data.

Signed-off-by Ryan Wanner <[email protected]>

---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/boot/dts/microchip/sama7d65.dtsi +7 -0

index b0a676623100..aadeea132289 100644
@@ -120,6 +120,13 @@ shdwc: poweroff@e001d200 {
 			status = "disabled";
 		};
 
+		rtt: rtc@e001d300 {
+			compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+			reg = <0xe001d300 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 0>;
+		};
+
 		clk32k: clock-controller@e001d500 {
 			compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
 			reg = <0xe001d500 0x4>;

arch/arm/boot/dts/microchip/sama7d65.dtsi +3 -0

+			reg = <0xe001d700 0x48>;
+		};
+
 		dma2: dma-controller@e1200000 {
 			compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
 			reg = <0xe1200000 0x1000>;

From: Ryan Wanner <[email protected]>

Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able to store the RTT time data.

Signed-off-by Ryan Wanner <[email protected]>

---
  arch/arm/boot/dts/microchip/sama7d65.dtsi | 12 ++++++++++++
  1 file changed, 12 insertions(+)

arch/arm/boot/dts/microchip/sama7d65.dtsi +7 -0

index b0a676623100..aadeea132289 100644
@@ -120,6 +120,13 @@ shdwc: poweroff@e001d200 {
  			status = "disabled";
  		};
 
+		rtt: rtc@e001d300 {
+			compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+			reg = <0xe001d300 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 0>;
+		};
+
  		clk32k: clock-controller@e001d500 {
  			compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
  			reg = <0xe001d500 0x4>;

arch/arm/boot/dts/microchip/sama7d65.dtsi +1 -0

+
  		dma2: dma-controller@e1200000 {
  			compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
  			reg = <0xe1200000 0x1000>;

From: Ryan Wanner <[email protected]>

This patch set adds support for low power modes for the SAMA7D65 SoC and the required components and changes for low power modes.

The series includes changes in the asm code to account for the addtional clocks that are in this SoC.

The Device tree additions are to enable all the components needed to keep the SoC in low power mode.

There are some DTB check warnings but that is due to the dt-binding not in the correct .yaml file format.

Changes v1 -> v2:
- Add missing compatible for ddr3phy, it is now in both syscon sets.
- Fix alphabetical ordering for sama7d65.
- Remove the incorrect reorganizing patch.
- Remove sama7g5-rtt as a compatible for sama7d65-rtt and add sama7d65-rtt as a compatible wake up source in the pm driver.

Changes from v2 -> v3:
- Correct mistake in v2 sfrbu dt-binding patch.
- Correct incorrect dt-binding addition and formatting for rtc and rtt bindings.
- Add missing SoB tag.
- Cleaned up commit message for Backup mode to describe SHDWC is status register is cleared for this SoC.
- Cleaned up variable naming and usage for mcks. Changed the mcks number to the correct number of clocks needed to be saved and corrected the ASM code accordingly.
- Removed the SHDWC from ULP0 wake-up source as it is not configured as a valid wake-up source for ULP0.
- Separated all the DTSI and DTS changes into individual patches.

Li Bin (1):
ARM: at91: pm: fix at91_suspend_finish for ZQ calibration

Ryan Wanner (20):
dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy
dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu
dt-bindings: sram: Add microchip,sama7d65-sram
dt-bindings: power: reset: atmel,sama5d2-shdwc: Add
microchip,sama7d65-shdwc
dt-bindings: reset: atmel,at91sam9260-reset: add
microchip,sama7d65-rstc
dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
ARM: at91: Add PM support to sama7d65
ARM: at91: pm: add DT compatible support for sama7d65
ARM: at91: PM: Add Backup mode for SAMA7D65
ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65
power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC
ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support
ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC
ARM: dts: microchip: sama7d65: Add Shutdown controller support
ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65
SoC
ARM: dts: microchip: sama7d65: Add RTC support for sama7d65
ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65
ARM: dts: microchip: sama7d65: Enable shutdown controller
ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board

 .../devicetree/bindings/mfd/syscon.yaml       |   4 +
 .../power/reset/atmel,sama5d2-shdwc.yaml      |   5 +
 .../reset/atmel,at91sam9260-reset.yaml        |   3 +
 .../bindings/rtc/atmel,at91rm9200-rtc.yaml    |   4 +-
 .../bindings/rtc/atmel,at91sam9260-rtt.yaml   |   1 +
 .../devicetree/bindings/sram/sram.yaml        |   1 +
 .../dts/microchip/at91-sama7d65_curiosity.dts |  13 +++
 arch/arm/boot/dts/microchip/sama7d65.dtsi     |  77 +++++++++++++
 arch/arm/mach-at91/Kconfig                    |   1 +
 arch/arm/mach-at91/pm.c                       |  47 +++++---
 arch/arm/mach-at91/pm.h                       |   1 +
 arch/arm/mach-at91/pm_data-offsets.c          |   2 +
 arch/arm/mach-at91/pm_suspend.S               | 101 ++++++++++++++++--
 drivers/power/reset/at91-sama5d2_shdwc.c      |   1 +
 14 files changed, 238 insertions(+), 23 deletions(-)

--
2.43.0

Ryan Wanner (20):
ARM: at91: Add PM support to sama7d65
ARM: at91: pm: add DT compatible support for sama7d65
ARM: at91: PM: Add Backup mode for SAMA7D65
ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65

ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC
ARM: dts: microchip: sama7d65: Add Shutdown controller support
ARM: dts: microchip: sama7d65: Add RTC support for sama7d65
ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65
ARM: dts: microchip: sama7d65: Enable shutdown controller

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Quoted 5 lines · On 27.02.2025 17:51, [email protected] wrote:

Ryan Wanner (20):
ARM: at91: Add PM support to sama7d65
ARM: at91: pm: add DT compatible support for sama7d65
ARM: at91: PM: Add Backup mode for SAMA7D65
ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65

Applied to at91-soc with some adjustments, please check!

Quoted 6 lines

ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC
ARM: dts: microchip: sama7d65: Add Shutdown controller support
ARM: dts: microchip: sama7d65: Add RTC support for sama7d65
ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65
ARM: dts: microchip: sama7d65: Enable shutdown controller

Applied to at91-dt with some adjustments, please check!

Thank you!

From: Ryan Wanner <[email protected]>

This patch set adds support for low power modes for the SAMA7D65 SoC and the required components and changes for low power modes.

The series includes changes in the asm code to account for the addtional clocks that are in this SoC.

[...]

From: Ryan Wanner <[email protected]>

This patch set adds support for low power modes for the SAMA7D65 SoC and the required components and changes for low power modes.

The series includes changes in the asm code to account for the addtional clocks that are in this SoC.

The Device tree additions are to enable all the components needed to keep the SoC in low power mode.

There are some DTB check warnings but that is due to the dt-binding not in the correct .yaml file format.

Changes v1 -> v2:
- Add missing compatible for ddr3phy, it is now in both syscon sets.
- Fix alphabetical ordering for sama7d65.
- Remove the incorrect reorganizing patch.
- Remove sama7g5-rtt as a compatible for sama7d65-rtt and add sama7d65-rtt as a compatible wake up source in the pm driver.

Changes from v2 -> v3:
- Correct mistake in v2 sfrbu dt-binding patch.
- Correct incorrect dt-binding addition and formatting for rtc and rtt bindings.
- Add missing SoB tag.
- Cleaned up commit message for Backup mode to describe SHDWC is status register is cleared for this SoC.
- Cleaned up variable naming and usage for mcks. Changed the mcks number to the correct number of clocks needed to be saved and corrected the ASM code accordingly.
- Removed the SHDWC from ULP0 wake-up source as it is not configured as a valid wake-up source for ULP0.
- Separated all the DTSI and DTS changes into individual patches.

Li Bin (1):
ARM: at91: pm: fix at91_suspend_finish for ZQ calibration

Ryan Wanner (20):
dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy
dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu

dt-bindings: sram: Add microchip,sama7d65-sram
dt-bindings: power: reset: atmel,sama5d2-shdwc: Add
microchip,sama7d65-shdwc
dt-bindings: reset: atmel,at91sam9260-reset: add
microchip,sama7d65-rstc
dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
ARM: at91: Add PM support to sama7d65
ARM: at91: pm: add DT compatible support for sama7d65
ARM: at91: PM: Add Backup mode for SAMA7D65
ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65
power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC
ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support
ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC
ARM: dts: microchip: sama7d65: Add Shutdown controller support
ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65
SoC
ARM: dts: microchip: sama7d65: Add RTC support for sama7d65
ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65
ARM: dts: microchip: sama7d65: Enable shutdown controller
ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board

 .../devicetree/bindings/mfd/syscon.yaml       |   4 +
 .../power/reset/atmel,sama5d2-shdwc.yaml      |   5 +
 .../reset/atmel,at91sam9260-reset.yaml        |   3 +
 .../bindings/rtc/atmel,at91rm9200-rtc.yaml    |   4 +-
 .../bindings/rtc/atmel,at91sam9260-rtt.yaml   |   1 +
 .../devicetree/bindings/sram/sram.yaml        |   1 +
 .../dts/microchip/at91-sama7d65_curiosity.dts |  13 +++
 arch/arm/boot/dts/microchip/sama7d65.dtsi     |  77 +++++++++++++
 arch/arm/mach-at91/Kconfig                    |   1 +
 arch/arm/mach-at91/pm.c                       |  47 +++++---
 arch/arm/mach-at91/pm.h                       |   1 +
 arch/arm/mach-at91/pm_data-offsets.c          |   2 +
 arch/arm/mach-at91/pm_suspend.S               | 101 ++++++++++++++++--
 drivers/power/reset/at91-sama5d2_shdwc.c      |   1 +
 14 files changed, 238 insertions(+), 23 deletions(-)

Signature · 1 line

2.43.0

EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe

Quoted 35 lines · On Thu, 27 Feb 2025, [email protected] wrote:

From: Ryan Wanner <[email protected]>

This patch set adds support for low power modes for the SAMA7D65 SoC and the required components and changes for low power modes.

The series includes changes in the asm code to account for the addtional clocks that are in this SoC.

The Device tree additions are to enable all the components needed to keep the SoC in low power mode.

There are some DTB check warnings but that is due to the dt-binding not in the correct .yaml file format.

Changes v1 -> v2:
- Add missing compatible for ddr3phy, it is now in both syscon sets.
- Fix alphabetical ordering for sama7d65.
- Remove the incorrect reorganizing patch.
- Remove sama7g5-rtt as a compatible for sama7d65-rtt and add sama7d65-rtt as a compatible wake up source in the pm driver.

Changes from v2 -> v3:
- Correct mistake in v2 sfrbu dt-binding patch.
- Correct incorrect dt-binding addition and formatting for rtc and rtt bindings.
- Add missing SoB tag.
- Cleaned up commit message for Backup mode to describe SHDWC is status register is cleared for this SoC.
- Cleaned up variable naming and usage for mcks. Changed the mcks number to the correct number of clocks needed to be saved and corrected the ASM code accordingly.
- Removed the SHDWC from ULP0 wake-up source as it is not configured as a valid wake-up source for ULP0.
- Separated all the DTSI and DTS changes into individual patches.

Quoted 6 lines

Li Bin (1):
ARM: at91: pm: fix at91_suspend_finish for ZQ calibration

Ryan Wanner (20):
dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy
dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu

Ping me when these are ready to take.

Quoted 39 lines

dt-bindings: sram: Add microchip,sama7d65-sram
dt-bindings: power: reset: atmel,sama5d2-shdwc: Add
microchip,sama7d65-shdwc
dt-bindings: reset: atmel,at91sam9260-reset: add
microchip,sama7d65-rstc
dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc
dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt
ARM: at91: Add PM support to sama7d65
ARM: at91: pm: add DT compatible support for sama7d65
ARM: at91: PM: Add Backup mode for SAMA7D65
ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65
power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC
ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support
ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC
ARM: dts: microchip: sama7d65: Add Shutdown controller support
ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65
SoC
ARM: dts: microchip: sama7d65: Add RTC support for sama7d65
ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65
ARM: dts: microchip: sama7d65: Enable shutdown controller
ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board

 .../devicetree/bindings/mfd/syscon.yaml       |   4 +
 .../power/reset/atmel,sama5d2-shdwc.yaml      |   5 +
 .../reset/atmel,at91sam9260-reset.yaml        |   3 +
 .../bindings/rtc/atmel,at91rm9200-rtc.yaml    |   4 +-
 .../bindings/rtc/atmel,at91sam9260-rtt.yaml   |   1 +
 .../devicetree/bindings/sram/sram.yaml        |   1 +
 .../dts/microchip/at91-sama7d65_curiosity.dts |  13 +++
 arch/arm/boot/dts/microchip/sama7d65.dtsi     |  77 +++++++++++++
 arch/arm/mach-at91/Kconfig                    |   1 +
 arch/arm/mach-at91/pm.c                       |  47 +++++---
 arch/arm/mach-at91/pm.h                       |   1 +
 arch/arm/mach-at91/pm_data-offsets.c          |   2 +
 arch/arm/mach-at91/pm_suspend.S               | 101 ++++++++++++++++--
 drivers/power/reset/at91-sama5d2_shdwc.c      |   1 +
 14 files changed, 238 insertions(+), 23 deletions(-)

Quoted 3 lines

--
2.43.0

--
Lee Jones [李琼斯]