x86/Hyper-V: Add AMD Secure AVIC for Hyper-V platform

RFC PATCH Superseded Tianyu Lan 4 participants 14 messages Aug 4, 2025 – Aug 6, 2025

Subsystems (4)

x86 Generic include/asm header files Hyper-V/Azure core and drivers Microsoft MANA RDMA driver

lore

Share & tools

lore

Tianyu Lan

author

2025-08-04 18:05 UTC #0 lore raw

v5 cover x86/Hyper-V: Add AMD Secure AVIC for Hyper-V platform

From: Tianyu Lan <[email protected]>

Secure AVIC is a new hardware feature in the AMD64 architecture to allow SEV-SNP guests to prevent the hypervisor from generating unexpected interrupts to a vCPU or otherwise violate architectural assumptions around APIC behavior.

Each vCPU has a guest-allocated APIC backing page of size 4K, which maintains APIC state for that vCPU. APIC backing page's ALLOWED_IRR field indicates the interrupt vectors which the guest allows the hypervisor to send.

This patchset is to enable the feature for Hyper-V platform. Patch "Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V" is to expose new fucntion hv_enable_coco_interrupt() and device driver and arch code may update AVIC backing page ALLOWED_IRR field to allow Hyper-V inject associated vector.

This patchset is based on the AMD patchset "AMD: Add Secure AVIC Guest Support"
https://lkml.org/lkml/2025/6/10/1579

Change since v4:
- Change the order to call hv_enable_coco_interrupt() in the hv_synic_enable/disable_regs().
- Update commit title "Drivers/hv:" to "Drivers: hv:"

Change since v3:
- Disable VMBus Message interrupt via hv_enable_ coco_interrupt() in the hv_synic_disable_regs().
- Fix coding style issue and update change log.

Change since v2:
- Add hv_enable_coco_interrupt() as wrapper of apic_update_vector()
- Re-work change logs

Change since v1:
- Remove the check of Secure AVIC when set APIC backing page
- Use apic_update_vector() instead of exposing new interface from Secure AVIC driver to update APIC backing page and allow associated interrupt to be injected by hypervisor.

Tianyu Lan (4):
x86/hyperv: Don't use hv apic driver when Secure AVIC is available
Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V x86/hyperv: Don't use auto-eoi when Secure AVIC is available x86/hyperv: Allow Hyper-V to inject STIMER0 interrupts

 arch/x86/hyperv/hv_apic.c      | 8 ++++++++
 arch/x86/hyperv/hv_init.c      | 7 +++++++
 arch/x86/kernel/cpu/mshyperv.c | 2 ++
 drivers/hv/hv.c                | 7 ++++++-
 drivers/hv/hv_common.c         | 5 +++++
 include/asm-generic/mshyperv.h | 1 +
 6 files changed, 29 insertions(+), 1 deletion(-)

Signature · 1 line

2.25.1

Tianyu Lan

author

2025-08-04 18:05 UTC #1 lore raw

RFC PATCH v5 1/4 x86/hyperv: Don't use hv apic driver when Secure AVIC is available

From: Tianyu Lan <[email protected]>

When Secure AVIC is available, the AMD x2apic Secure AVIC driver will be selected. In that case, have hv_apic_init() return immediately without doing anything.

Reviewed-by Michael Kelley <[email protected]>

Signed-off-by Tianyu Lan <[email protected]>

---
Change since RFC V3:
- Update Change log and fix coding style issue.

---
 arch/x86/hyperv/hv_apic.c | 3 +++
 1 file changed, 3 insertions(+)

arch/x86/hyperv/hv_apic.c +3 -0

index bfde0a3498b9..e669053b637d 100644
@@ -293,6 +293,9 @@ static void hv_send_ipi_self(int vector)
 
 void __init hv_apic_init(void)
 {
+	if (cc_platform_has(CC_ATTR_SNP_SECURE_AVIC))
+		return;
+
 	if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
 		pr_info("Hyper-V: Using IPI hypercalls\n");
 		/*

Signature · 1 line

2.25.1

Neeraj Upadhyay

Reviewed-by on v5 1/4

2025-08-05 13:42 UTC #2 lore raw

Re: [RFC PATCH V5 1/4] x86/hyperv: Don't use hv apic driver when Secure AVIC is available

Quoted 9 lines · Tianyu Lan

From: Tianyu Lan <[email protected]>
When Secure AVIC is available, the AMD x2apic Secure AVIC driver will be selected. In that case, have hv_apic_init() return immediately without doing anything.
Reviewed-by Michael Kelley <[email protected]>
Signed-off-by Tianyu Lan <[email protected]>
---

Do you need to include linux/cc_platform.h ?

Reviewed-by Neeraj Upadhyay <[email protected]>

- Neeraj

Tianyu Lan

author

2025-08-04 18:05 UTC #3 lore raw

RFC PATCH v5 2/4 Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V

In reply to Tianyu Lan

From: Tianyu Lan <[email protected]>

When Secure AVIC is enabled, VMBus driver should call x2apic Secure AVIC interface to allow Hyper-V to inject VMBus message interrupt.

Reviewed-by Michael Kelley <[email protected]>

Signed-off-by Tianyu Lan <[email protected]>

---
Change since RFC V4:
- Change the order to call hv_enable_coco_interrupt() in the hv_synic_enable/disable_regs().
- Update commit title "Drivers/hv:" to "Drivers: hv:"

Change since RFC V3:
- Disable VMBus Message interrupt via hv_enable_ coco_interrupt() in the hv_synic_disable_regs().

---
 arch/x86/hyperv/hv_apic.c      | 5 +++++
 drivers/hv/hv.c                | 7 ++++++-
 drivers/hv/hv_common.c         | 5 +++++
 include/asm-generic/mshyperv.h | 1 +
 4 files changed, 17 insertions(+), 1 deletion(-)

arch/x86/hyperv/hv_apic.c +5 -0

index e669053b637d..a8de503def37 100644
@@ -53,6 +53,11 @@ static void hv_apic_icr_write(u32 low, u32 id)
 	wrmsrq(HV_X64_MSR_ICR, reg_val);
 }
 
+void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set)
+{
+	apic_update_vector(cpu, vector, set);
+}
+
 static u32 hv_apic_read(u32 reg)
 {
 	u32 reg_val, hi;

drivers/hv/hv.c +6 -1

index 308c8f279df8..2ff433cb5cc2 100644
@@ -314,8 +314,11 @@ void hv_synic_enable_regs(unsigned int cpu)
 	shared_sint.vector = vmbus_interrupt;
 	shared_sint.masked = false;
 	shared_sint.auto_eoi = hv_recommend_using_aeoi();
+
 	hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
+	hv_enable_coco_interrupt(cpu, vmbus_interrupt, true);
+
 	/* Enable the global synic bit */
 	sctrl.as_uint64 = hv_get_msr(HV_MSR_SCONTROL);
 	sctrl.enable = 1;

@@ -342,7 +345,6 @@ void hv_synic_disable_regs(unsigned int cpu)
 	union hv_synic_scontrol sctrl;
 
 	shared_sint.as_uint64 = hv_get_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT);
-
 	shared_sint.masked = 1;
 
 	/* Need to correctly cleanup in the case of SMP!!! */

@@ -350,6 +352,9 @@ void hv_synic_disable_regs(unsigned int cpu)
 	hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
 	simp.as_uint64 = hv_get_msr(HV_MSR_SIMP);
+
+	hv_enable_coco_interrupt(cpu, vmbus_interrupt, false);
+
 	/*
 	 * In Isolation VM, sim and sief pages are allocated by
 	 * paravisor. These pages also will be used by kdump

drivers/hv/hv_common.c +5 -0

index 49898d10faff..0f024ab3d360 100644
@@ -716,6 +716,11 @@ u64 __weak hv_tdx_hypercall(u64 control, u64 param1, u64 param2)
 }
 EXPORT_SYMBOL_GPL(hv_tdx_hypercall);
 
+void __weak hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set)
+{
+}
+EXPORT_SYMBOL_GPL(hv_enable_coco_interrupt);
+
 void hv_identify_partition_type(void)
 {
 	/* Assume guest role */

include/asm-generic/mshyperv.h +1 -0

index a729b77983fa..7907c9878369 100644
@@ -333,6 +333,7 @@ bool hv_is_isolation_supported(void);
 bool hv_isolation_type_snp(void);
 u64 hv_ghcb_hypercall(u64 control, void *input, void *output, u32 input_size);
 u64 hv_tdx_hypercall(u64 control, u64 param1, u64 param2);
+void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set);
 void hyperv_cleanup(void);
 bool hv_query_ext_cap(u64 cap_query);
 void hv_setup_dma_ops(struct device *dev, bool coherent);

Signature · 1 line

2.25.1

Neeraj Upadhyay

Reviewed-by on v5 2/4

2025-08-05 13:59 UTC #4 lore raw

Re: [RFC PATCH V5 2/4] Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V

Quoted 2 lines · Tianyu Lan

From: Tianyu Lan <[email protected]>

...

drivers/hv/hv.c void hv_synic_enable_regs(unsigned int cpu) · line 317

Quoted 9 lines

drivers/hv/hv.c +1 -0

index 308c8f279df8..2ff433cb5cc2 100644
@@ -314,8 +314,11 @@ void hv_synic_enable_regs(unsigned int cpu)
 	shared_sint.vector = vmbus_interrupt;
 	shared_sint.masked = false;
 	shared_sint.auto_eoi = hv_recommend_using_aeoi();
+

Nit: extra newline.

drivers/hv/hv.c void hv_synic_disable_regs(unsigned int cpu) · line 345

Quoted 12 lines

drivers/hv/hv.c +2 -1

 	hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
+	hv_enable_coco_interrupt(cpu, vmbus_interrupt, true);
+
 	/* Enable the global synic bit */
 	sctrl.as_uint64 = hv_get_msr(HV_MSR_SCONTROL);
 	sctrl.enable = 1;

@@ -342,7 +345,6 @@ void hv_synic_disable_regs(unsigned int cpu)
 	union hv_synic_scontrol sctrl;
 
 	shared_sint.as_uint64 = hv_get_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT);
-

Nit: extra newline.

drivers/hv/hv.c void hv_synic_disable_regs(unsigned int cpu) · line 357

Quoted 10 lines

drivers/hv/hv.c +3 -0

 	shared_sint.masked = 1;
 
 	/* Need to correctly cleanup in the case of SMP!!! */

@@ -350,6 +352,9 @@ void hv_synic_disable_regs(unsigned int cpu)
 	hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
 	simp.as_uint64 = hv_get_msr(HV_MSR_SIMP);
+
+	hv_enable_coco_interrupt(cpu, vmbus_interrupt, false);
+

Nit: Maybe this should be above "simp.as_uint64 = hv_get_msr(HV_MSR_SIMP)" ?

Reviewed-by Neeraj Upadhyay <[email protected]>

- Neeraj

Tianyu Lan

author

2025-08-05 15:19 UTC #5 lore raw

Re: [RFC PATCH V5 2/4] Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V

Quoted 6 lines · Neeraj Upadhyay

Quoted 2 lines · Tianyu Lan
From: Tianyu Lan <[email protected]>

Quoted 11 lines

drivers/hv/hv.c void hv_synic_enable_regs(unsigned int cpu) · line 317

Quoted 9 lines

drivers/hv/hv.c +1 -0

index 308c8f279df8..2ff433cb5cc2 100644
@@ -314,8 +314,11 @@ void hv_synic_enable_regs(unsigned int cpu)
      shared_sint.vector = vmbus_interrupt;
      shared_sint.masked = false;
      shared_sint.auto_eoi = hv_recommend_using_aeoi();
+

Nit: extra newline.

Thanks for your review. Will remove it..

Quoted 11 lines

drivers/hv/hv.c +2 -0

      hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
+     hv_enable_coco_interrupt(cpu, vmbus_interrupt, true);
+
      /* Enable the global synic bit */
      sctrl.as_uint64 = hv_get_msr(HV_MSR_SCONTROL);
      sctrl.enable = 1;

@@ -342,7 +345,6 @@ void hv_synic_disable_regs(unsigned int cpu)
      union hv_synic_scontrol sctrl;

Quoted 5 lines

drivers/hv/hv.c void hv_synic_disable_regs(unsigned int cpu) · line 345
Quoted 2 lines
drivers/hv/hv.c +0 -1
      shared_sint.as_uint64 = hv_get_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT);
-
Nit: extra newline.

Will remove it..

Quoted 7 lines

drivers/hv/hv.c +0 -0

      shared_sint.masked = 1;
 
      /* Need to correctly cleanup in the case of SMP!!! */

@@ -350,6 +352,9 @@ void hv_synic_disable_regs(unsigned int cpu)
      hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);

Quoted 7 lines

drivers/hv/hv.c void hv_synic_disable_regs(unsigned int cpu) · line 357
Quoted 4 lines
drivers/hv/hv.c +3 -0
      simp.as_uint64 = hv_get_msr(HV_MSR_SIMP);
+
+     hv_enable_coco_interrupt(cpu, vmbus_interrupt, false);
+
Nit: Maybe this should be above "simp.as_uint64 = hv_get_msr(HV_MSR_SIMP)" ?

--
Thanks
Tianyu Lan

Michael Kelley

2025-08-05 18:09 UTC #6 lore raw

RE: [RFC PATCH V5 2/4] Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V

In reply to Tianyu Lan

From: Tianyu Lan <[email protected]> Sent: Monday, August 4, 2025 11:05 AM

Quoted 64 lines

When Secure AVIC is enabled, VMBus driver should call x2apic Secure AVIC interface to allow Hyper-V to inject VMBus message interrupt.

Reviewed-by Michael Kelley <[email protected]>

Signed-off-by Tianyu Lan <[email protected]>

---
Change since RFC V4:
- Change the order to call hv_enable_coco_interrupt() in the hv_synic_enable/disable_regs().
- Update commit title "Drivers/hv:" to "Drivers: hv:"

Change since RFC V3:
- Disable VMBus Message interrupt via hv_enable_ coco_interrupt() in the hv_synic_disable_regs().

---
 arch/x86/hyperv/hv_apic.c      | 5 +++++
 drivers/hv/hv.c                | 7 ++++++-
 drivers/hv/hv_common.c         | 5 +++++
 include/asm-generic/mshyperv.h | 1 +
 4 files changed, 17 insertions(+), 1 deletion(-)

arch/x86/hyperv/hv_apic.c +5 -0

index e669053b637d..a8de503def37 100644
@@ -53,6 +53,11 @@ static void hv_apic_icr_write(u32 low, u32 id)
 	wrmsrq(HV_X64_MSR_ICR, reg_val);
 }
 
+void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set)
+{
+	apic_update_vector(cpu, vector, set);
+}
+
 static u32 hv_apic_read(u32 reg)
 {
 	u32 reg_val, hi;

drivers/hv/hv.c +3 -1

index 308c8f279df8..2ff433cb5cc2 100644
@@ -314,8 +314,11 @@ void hv_synic_enable_regs(unsigned int cpu)
 	shared_sint.vector = vmbus_interrupt;
 	shared_sint.masked = false;
 	shared_sint.auto_eoi = hv_recommend_using_aeoi();
+
 	hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
+	hv_enable_coco_interrupt(cpu, vmbus_interrupt, true);
+
 	/* Enable the global synic bit */
 	sctrl.as_uint64 = hv_get_msr(HV_MSR_SCONTROL);
 	sctrl.enable = 1;

@@ -342,7 +345,6 @@ void hv_synic_disable_regs(unsigned int cpu)
 	union hv_synic_scontrol sctrl;
 
 	shared_sint.as_uint64 = hv_get_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT);
-
 	shared_sint.masked = 1;
 
 	/* Need to correctly cleanup in the case of SMP!!! */

drivers/hv/hv.c void hv_synic_disable_regs(unsigned int cpu) · line 357

Quoted 6 lines

drivers/hv/hv.c +3 -0

@@ -350,6 +352,9 @@ void hv_synic_disable_regs(unsigned int cpu)
 	hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
 	simp.as_uint64 = hv_get_msr(HV_MSR_SIMP);
+
+	hv_enable_coco_interrupt(cpu, vmbus_interrupt, false);
+

I agree with Neeraj's comment on the placement of this line of code. As I commented on v4 of the series, the hv_synic_enable/disable_regs() functions have units of code that do read, modify, then write of a synthetic MSR, such as the SIMP, SIEFP, and SINT. It's weird to have hv_enable_coco_interrupt() in the middle of such a unit. In this v5, you fixed the issue for hv_synic_enable_regs(), but not here for hv_synic_disable_regs(). The call to hv_enable_coco_interrupt() should go after call to hv_set_msr(HV_MSR_SINT0 ....), but before the call to hv_get_msr(HV_MSR_SIMP) so that the read/modify/write units aren't mixed with other things.

Michael

Quoted 33 lines

drivers/hv/hv.c +0 -0

 	/*
 	 * In Isolation VM, sim and sief pages are allocated by
 	 * paravisor. These pages also will be used by kdump

drivers/hv/hv_common.c +5 -0

index 49898d10faff..0f024ab3d360 100644
@@ -716,6 +716,11 @@ u64 __weak hv_tdx_hypercall(u64 control, u64 param1, u64 param2)
 }
 EXPORT_SYMBOL_GPL(hv_tdx_hypercall);
 
+void __weak hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set)
+{
+}
+EXPORT_SYMBOL_GPL(hv_enable_coco_interrupt);
+
 void hv_identify_partition_type(void)
 {
 	/* Assume guest role */

include/asm-generic/mshyperv.h +1 -1

index a729b77983fa..7907c9878369 100644
@@ -333,6 +333,7 @@ bool hv_is_isolation_supported(void);
 bool hv_isolation_type_snp(void);
 u64 hv_ghcb_hypercall(u64 control, void *input, void *output, u32 input_size);
 u64 hv_tdx_hypercall(u64 control, u64 param1, u64 param2);
+void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set);
 void hyperv_cleanup(void);
 bool hv_query_ext_cap(u64 cap_query);
 void hv_setup_dma_ops(struct device *dev, bool coherent);
--

2.25.1

Tianyu Lan

author

2025-08-05 19:25 UTC #7 lore raw

Re: [RFC PATCH V5 2/4] Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V

Quoted 68 lines · Michael Kelley

From: Tianyu Lan <[email protected]> Sent: Monday, August 4, 2025 11:05 AM

Quoted 66 lines

When Secure AVIC is enabled, VMBus driver should call x2apic Secure AVIC interface to allow Hyper-V to inject VMBus message interrupt.

Reviewed-by Michael Kelley <[email protected]>

Signed-off-by Tianyu Lan <[email protected]>

---
Change since RFC V4:
- Change the order to call hv_enable_coco_interrupt() in the hv_synic_enable/disable_regs().
- Update commit title "Drivers/hv:" to "Drivers: hv:"

Change since RFC V3:
- Disable VMBus Message interrupt via hv_enable_ coco_interrupt() in the hv_synic_disable_regs().

---
 arch/x86/hyperv/hv_apic.c      | 5 +++++
 drivers/hv/hv.c                | 7 ++++++-
 drivers/hv/hv_common.c         | 5 +++++
 include/asm-generic/mshyperv.h | 1 +
 4 files changed, 17 insertions(+), 1 deletion(-)

arch/x86/hyperv/hv_apic.c +5 -0

index e669053b637d..a8de503def37 100644
@@ -53,6 +53,11 @@ static void hv_apic_icr_write(u32 low, u32 id)
      wrmsrq(HV_X64_MSR_ICR, reg_val);
 }
 
+void hv_enable_coco_interrupt(unsigned int cpu, unsigned int vector, bool set)
+{
+     apic_update_vector(cpu, vector, set);
+}
+
 static u32 hv_apic_read(u32 reg)
 {
      u32 reg_val, hi;

drivers/hv/hv.c +3 -1

index 308c8f279df8..2ff433cb5cc2 100644
@@ -314,8 +314,11 @@ void hv_synic_enable_regs(unsigned int cpu)
      shared_sint.vector = vmbus_interrupt;
      shared_sint.masked = false;
      shared_sint.auto_eoi = hv_recommend_using_aeoi();
+
      hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
 
+     hv_enable_coco_interrupt(cpu, vmbus_interrupt, true);
+
      /* Enable the global synic bit */
      sctrl.as_uint64 = hv_get_msr(HV_MSR_SCONTROL);
      sctrl.enable = 1;

@@ -342,7 +345,6 @@ void hv_synic_disable_regs(unsigned int cpu)
      union hv_synic_scontrol sctrl;
 
      shared_sint.as_uint64 = hv_get_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT);
-
      shared_sint.masked = 1;
 
      /* Need to correctly cleanup in the case of SMP!!! */

@@ -350,6 +352,9 @@ void hv_synic_disable_regs(unsigned int cpu)
      hv_set_msr(HV_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);

Quoted 16 lines

drivers/hv/hv.c void hv_synic_disable_regs(unsigned int cpu) · line 357
Quoted 4 lines
drivers/hv/hv.c +3 -0
      simp.as_uint64 = hv_get_msr(HV_MSR_SIMP);
+
+     hv_enable_coco_interrupt(cpu, vmbus_interrupt, false);
+
I agree with Neeraj's comment on the placement of this line of code. As I commented on v4 of the series, the hv_synic_enable/disable_regs() functions have units of code that do read, modify, then write of a synthetic MSR, such as the SIMP, SIEFP, and SINT. It's weird to have hv_enable_coco_interrupt() in the middle of such a unit. In this v5, you fixed the issue for hv_synic_enable_regs(), but not here for hv_synic_disable_regs(). The call to hv_enable_coco_interrupt() should go after call to hv_set_msr(HV_MSR_SINT0 ....), but before the call to hv_get_msr(HV_MSR_SIMP) so that the read/modify/write units aren't mixed with other things.

Hi Michael:
Thanks for your review. Agree. Will update in the next version.

--
Thanks
Tianyu Lan

Tianyu Lan

author

2025-08-04 18:05 UTC #8 lore raw

RFC PATCH v5 3/4 x86/hyperv: Don't use auto-eoi when Secure AVIC is available

In reply to Tianyu Lan

From: Tianyu Lan <[email protected]>

Hyper-V doesn't support auto-eoi with Secure AVIC. So set the HV_DEPRECATING_AEOI_RECOMMENDED flag
to force writing the EOI register after handling an interrupt.

Reviewed-by Michael Kelley <[email protected]>

Signed-off-by Tianyu Lan <[email protected]>

---
Change since RFC V3:
- Update title prefix from "x86/Hyper-V" to "x86/hyperv"

---
 arch/x86/kernel/cpu/mshyperv.c | 2 ++
 1 file changed, 2 insertions(+)

arch/x86/kernel/cpu/mshyperv.c +2 -0

index c78f860419d6..8f029650f16c 100644
@@ -463,6 +463,8 @@ static void __init ms_hyperv_init_platform(void)
 		 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index);
 
 	hv_identify_partition_type();
+	if (cc_platform_has(CC_ATTR_SNP_SECURE_AVIC))
+		ms_hyperv.hints |= HV_DEPRECATING_AEOI_RECOMMENDED;
 
 	if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) {
 		hv_nested = true;

Signature · 1 line

2.25.1

Neeraj Upadhyay

Reviewed-by on v5 3/4

2025-08-05 14:06 UTC #9 lore raw

Re: [RFC PATCH V5 3/4] x86/hyperv: Don't use auto-eoi when Secure AVIC is available

Quoted 6 lines · Tianyu Lan

From: Tianyu Lan <[email protected]>
Hyper-V doesn't support auto-eoi with Secure AVIC. So set the HV_DEPRECATING_AEOI_RECOMMENDED flag
to force writing the EOI register after handling an interrupt.

Quoted 6 lines

Reviewed-by Michael Kelley <[email protected]>
Signed-off-by Tianyu Lan <[email protected]>
---
Change since RFC V3:
- Update title prefix from "x86/Hyper-V" to "x86/hyperv"
---

Reviewed-by Neeraj Upadhyay <[email protected]>

Tianyu Lan

author

2025-08-04 18:05 UTC #10 lore raw

RFC PATCH v5 4/4 x86/hyperv: Allow Hyper-V to inject STIMER0 interrupts

In reply to Tianyu Lan

From: Tianyu Lan <[email protected]>

When Secure AVIC is enabled, call Secure AVIC function to allow Hyper-V to inject STIMER0 interrupt.

Reviewed-by Michael Kelley <[email protected]>

Signed-off-by Tianyu Lan <[email protected]>

---
 arch/x86/hyperv/hv_init.c | 7 +++++++
 1 file changed, 7 insertions(+)

arch/x86/hyperv/hv_init.c +7 -0

index 3d1d3547095a..591338162420 100644
@@ -132,6 +132,10 @@ static int hv_cpu_init(unsigned int cpu)
 		wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64);
 	}
 
+	/* Allow Hyper-V stimer vector to be injected from Hypervisor. */
+	if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE)
+		apic_update_vector(cpu, HYPERV_STIMER0_VECTOR, true);
+
 	return hyperv_init_ghcb();
 }

@@ -239,6 +243,9 @@ static int hv_cpu_die(unsigned int cpu)
 		*ghcb_va = NULL;
 	}
 
+	if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE)
+		apic_update_vector(cpu, HYPERV_STIMER0_VECTOR, false);
+
 	hv_common_cpu_die(cpu);
 
 	if (hv_vp_assist_page && hv_vp_assist_page[cpu]) {

Signature · 1 line

2.25.1

Neeraj Upadhyay

Reviewed-by on v5 4/4

2025-08-05 14:09 UTC #11 lore raw

Re: [RFC PATCH V5 4/4] x86/hyperv: Allow Hyper-V to inject STIMER0 interrupts

Quoted 8 lines · Tianyu Lan

From: Tianyu Lan <[email protected]>
When Secure AVIC is enabled, call Secure AVIC function to allow Hyper-V to inject STIMER0 interrupt.
Reviewed-by Michael Kelley <[email protected]>
Signed-off-by Tianyu Lan <[email protected]>
---

Reviewed-by Neeraj Upadhyay <[email protected]>

Naman Jain

2025-08-06 05:42 UTC #12 lore raw

In reply to Tianyu Lan

Quoted 22 lines · Tianyu Lan

From: Tianyu Lan <[email protected]>
Secure AVIC is a new hardware feature in the AMD64 architecture to allow SEV-SNP guests to prevent the hypervisor from generating unexpected interrupts to a vCPU or otherwise violate architectural assumptions around APIC behavior.
Each vCPU has a guest-allocated APIC backing page of size 4K, which maintains APIC state for that vCPU. APIC backing page's ALLOWED_IRR field indicates the interrupt vectors which the guest allows the hypervisor to send.
This patchset is to enable the feature for Hyper-V platform. Patch "Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V" is to expose new fucntion hv_enable_coco_interrupt() and device driver and arch code may update AVIC backing page ALLOWED_IRR field to allow Hyper-V inject associated vector.

Quoted 3 lines

This patchset is based on the AMD patchset "AMD: Add Secure AVIC Guest Support"

NIT:
Generally RFC tag is meant to be used for the patches which are probably not ready for merging, and is mostly intended for having a discussion around your changes. Since this is now reviewed by multiple people and have gone through multiple versions already, if you feel this can be merged, you can remove RFC tags in next version, if you are planning to send it.

Regards,
Naman

Tianyu Lan

author

2025-08-06 09:21 UTC #13 lore raw

Quoted 31 lines · Naman Jain

Quoted 22 lines · Tianyu Lan
From: Tianyu Lan <[email protected]>
Secure AVIC is a new hardware feature in the AMD64 architecture to allow SEV-SNP guests to prevent the hypervisor from generating unexpected interrupts to a vCPU or otherwise violate architectural assumptions around APIC behavior.
Each vCPU has a guest-allocated APIC backing page of size 4K, which maintains APIC state for that vCPU. APIC backing page's ALLOWED_IRR field indicates the interrupt vectors which the guest allows the hypervisor to send.
This patchset is to enable the feature for Hyper-V platform. Patch "Drivers: hv: Allow vmbus message synic interrupt injected from Hyper-V" is to expose new fucntion hv_enable_coco_interrupt() and device driver and arch code may update AVIC backing page ALLOWED_IRR field to allow Hyper-V inject associated vector.
Quoted 3 lines
This patchset is based on the AMD patchset "AMD: Add Secure AVIC Guest Support"

Quoted 8 lines

NIT:
Generally RFC tag is meant to be used for the patches which are probably not ready for merging, and is mostly intended for having a discussion around your changes. Since this is now reviewed by multiple people and have gone through multiple versions already, if you feel this can be merged, you can remove RFC tags in next version, if you are planning to send it.

Hi Naman:
Thanks for your review and suggestion. This patchset is based on
the AMD Secure AVIC
driver patchset.which is still with RFC tag. I will remove the RFC tag of this patchset after AMD
patchset merged.
.
...
Thanks
Tianyu Lan