Update the Netduino 2 Machine

Add the STM32F2xx ADC device. This device randomly generates values on each read.

This also includes creating a hw/adc directory.

Signed-off-by Alistair Francis <[email protected]>

Add the STM32F2xx SPI device.

Signed-off-by Alistair Francis <[email protected]>

---

hw/ssi/stm32f2xx_spi.c new file +8 -0

+static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
+                                     unsigned int size)
+{
+    STM32F2XXSPIState *s = opaque;
+    uint32_t retval;
+
+    DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
+

hw/ssi/stm32f2xx_spi.c new file +21 -0

+    case STM_SPI_DR:
+        stm32f2xx_spi_transfer(s);
+        s->spi_sr &= ~STM_SPI_SR_RXNE;
+        return s->spi_dr;
+    case STM_SPI_CRCPR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_crcpr;
+    case STM_SPI_RXCRCR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_rxcrcr;
+    case STM_SPI_TXCRCR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_txcrcr;
+    case STM_SPI_I2SCFGR:
+        qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_i2scfgr;
+    case STM_SPI_I2SPR:

Quoted 17 lines · Alistair Francis

Add the STM32F2xx SPI device.

Signed-off-by Alistair Francis <[email protected]>

---

hw/ssi/stm32f2xx_spi.c new file +12 -0

+static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
+                                     unsigned int size)
+{
+    STM32F2XXSPIState *s = opaque;
+    uint32_t retval;
+
+    DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
+
+    switch (addr) {
+    case STM_SPI_CR1:
+        return s->spi_cr1;
+    case STM_SPI_CR2:

hw/ssi/stm32f2xx_spi.c line 84

Quoted 6 lines

hw/ssi/stm32f2xx_spi.c new file +6 -0

+        qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n",
+                      __func__);
+        return s->spi_cr2;
+    case STM_SPI_SR:
+        retval = s->spi_sr;
+        return retval;

Why not just 'return s->spi_sr;' like the other cases?

Quoted 22 lines

hw/ssi/stm32f2xx_spi.c new file +21 -0

+    case STM_SPI_DR:
+        stm32f2xx_spi_transfer(s);
+        s->spi_sr &= ~STM_SPI_SR_RXNE;
+        return s->spi_dr;
+    case STM_SPI_CRCPR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_crcpr;
+    case STM_SPI_RXCRCR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_rxcrcr;
+    case STM_SPI_TXCRCR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_txcrcr;
+    case STM_SPI_I2SCFGR:
+        qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_i2scfgr;
+    case STM_SPI_I2SPR:

hw/ssi/stm32f2xx_spi.c line 115

Quoted 10 lines

hw/ssi/stm32f2xx_spi.c new file +10 -0

+        qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+                      "are included for compatibility\n", __func__);
+        return s->spi_i2spr;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+    }
+
+    return 0;
+}

Otherwise

Reviewed-by Peter Maydell <[email protected]>

thanks
-- PMM

Connect the ADC devices to the STM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

---
V4:
- Connect all the interrupt lines correctly
V2:
- Fix up the device/devices commit message

(quoted diff) +13 -0

@@ -132,6 +142,29 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
     }
+
+    /* ADC 1 to 3 */
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, adc_addr[i]);
+    }
+

Quoted 26 lines · Alistair Francis

Connect the ADC devices to the STM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

---
V4:
- Connect all the interrupt lines correctly
V2:
- Fix up the device/devices commit message

(quoted diff) +13 -0

@@ -132,6 +142,29 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
     }
+
+    /* ADC 1 to 3 */
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, adc_addr[i]);
+    }
+

Review static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) · line 167

Quoted 10 lines

(quoted diff) +10 -0

+    /* Connect each ADC device to the one GIC IRQ line */
+    gic_adc_irq = qdev_get_gpio_in(nvic, ADC_IRQ);
+    gic_adc_irq_arr = qemu_extend_irqs(NULL, 0,
+                                       qemu_irq_get_handler(gic_adc_irq),
+                                       qemu_irq_get_opaque(gic_adc_irq),
+                                       STM_NUM_ADCS);
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, gic_adc_irq_arr[i]);
+    }

This will lower the IRQ input to the GIC as soon as any one of the ADCs lowers its IRQ (even if another of them has it held high), and conversely raise it again as soon as any one ADC raises its IRQ (even if another of them has it held low). We talked about this on the last version: http://patchwork.ozlabs.org/patch/569823/
and I still think you should implement an OR gate here.

Checking the real hardware behaviour by writing a test would be ideal; but whatever the hardware does it isn't going to be what this code does; and an OR gate is the obvious guess.

I was going to suggest something like:

/**
* qemu_irq_or:
* @irqs: array of IRQs to OR together
* @numirqs: number of IRQs in @irqs
*
* Returns a new IRQ which behaves as the logical OR of all the
* input IRQS in @irqs.
*/
qemu_irq qemu_irq_or(qemu_irq *irqs, int numirqs);

along the same lines as qemu_irq_invert(), which creates a NOT gate, but then I realized you need some actual state in there (because you need to remember the current state of all the input lines). So this probably needs to be a real device object so it can be migrated.

thanks
-- PMM

I think this function should work:

/*
* qemu_allocate_or_irqs
* @in_irq: An input IRQ. It will be the result of the @out_irqs ORed together
* @n: The number of interrupt lines that should be ORed together *
* returns: An array of interrupts that should be ORed together
*
* OR all of the interrupts returned in the array into a single @in_irq. */
qemu_irq *qemu_allocate_or_irqs(qemu_irq in_irq, int n);