Update the Netduino 2 Machine

PATCH In review Alistair Francis 2 participants 13 messages Sep 24, 2016 – Sep 30, 2016 Arm STM32

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Alistair Francis

author

2016-09-24 19:21 UTC #0 lore raw

v8 cover Update the Netduino 2 Machine

This patchset continues with the Netduino 2 and STM32F205 SoC work.

This patch series makes a small change to the STM32F2xx SoC to tidy up the code.

Next a feature is added to the STM32F2xx timer to display the PWM duty cycle, when debugging is enabled.

Then the STM32F2xx SPI and ADC devices are added and connected to the STM32F205 SoC.

Finally the maintainers file is updated to add myself as the maintainer for the Netdunio 2 and STM32F2xx.

V8:
- Use the qdev_init_gpio_in() function to create in irqs for the OR device.
V6:
- Add vmstate to the new OR IRQ device
V5:
- Add a irq ORing function
V4:
- Add VMState to the new devices
- Remove rand() function
V3:
- Rebase
V2:
- Update based on Peter C's coments
- Rebase
- Create an ADC folder for the ADC device

Alistair Francis (8):
STM32F205: Remove the individual device variables
STM32F2xx: Display PWM duty cycle from timer
STM32F2xx: Add the ADC device
STM32F2xx: Add the SPI device
irq: Add a new irq device that allows the ORing of lines
STM32F205: Connect the ADC devices
STM32F205: Connect the SPI devices
MAINTAINERS: Add Alistair to the maintainers list

 MAINTAINERS                     |  15 ++
 default-configs/arm-softmmu.mak |   2 +
 hw/Makefile.objs                |   1 +
 hw/adc/Makefile.objs            |   1 +
 hw/adc/stm32f2xx_adc.c          | 306 ++++++++++++++++++++++++++++++++++++++++
 hw/arm/stm32f205_soc.c          |  92 +++++++++---
 hw/core/Makefile.objs           |   1 +
 hw/core/or-irq.c                | 107 ++++++++++++++
 hw/ssi/Makefile.objs            |   1 +
 hw/ssi/stm32f2xx_spi.c          | 225 +++++++++++++++++++++++++++++
 hw/timer/stm32f2xx_timer.c      |   9 ++
 include/hw/adc/stm32f2xx_adc.h  |  87 ++++++++++++
 include/hw/arm/stm32f205_soc.h  |   9 ++
 include/hw/or-irq.h             |  44 ++++++
 include/hw/ssi/stm32f2xx_spi.h  |  72 ++++++++++
 15 files changed, 954 insertions(+), 18 deletions(-)
 create mode 100644 hw/adc/Makefile.objs
 create mode 100644 hw/adc/stm32f2xx_adc.c
 create mode 100644 hw/core/or-irq.c
 create mode 100644 hw/ssi/stm32f2xx_spi.c
 create mode 100644 include/hw/adc/stm32f2xx_adc.h
 create mode 100644 include/hw/or-irq.h
 create mode 100644 include/hw/ssi/stm32f2xx_spi.h

Signature · 1 line

2.7.4

Alistair Francis

author

2016-09-24 19:21 UTC #1 lore raw

PATCH v8 1/8 STM32F205: Remove the individual device variables

Cleanup the individual DeviceState and SysBusDevice variables to re-use the same variable for each device.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Crosthwaite <[email protected]>

---

 hw/arm/stm32f205_soc.c | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

hw/arm/stm32f205_soc.c +17 ~~-18~~

index de26b8c..5b6fa3b 100644
@@ -62,8 +62,8 @@ static void stm32f205_soc_initfn(Object *obj)
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
 {
     STM32F205State *s = STM32F205_SOC(dev_soc);
-    DeviceState *syscfgdev, *usartdev, *timerdev, *nvic;
-    SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
+    DeviceState *dev, *nvic;
+    SysBusDevice *busdev;
     Error *err = NULL;
     int i;

@@ -94,44 +94,43 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
                        s->kernel_filename, s->cpu_model);
 
     /* System configuration controller */
-    syscfgdev = DEVICE(&s->syscfg);
+    dev = DEVICE(&s->syscfg);
     object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
     if (err != NULL) {
         error_propagate(errp, err);
         return;
     }
-    syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
-    sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
-    sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71));
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, 0x40013800);
+    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
 
     /* Attach UART (uses USART registers) and USART controllers */
     for (i = 0; i < STM_NUM_USARTS; i++) {
-        usartdev = DEVICE(&(s->usart[i]));
-        qdev_prop_set_chr(usartdev, "chardev", i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
+        dev = DEVICE(&(s->usart[i]));
+        qdev_prop_set_chr(dev, "chardev",
+                          i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
         object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
         if (err != NULL) {
             error_propagate(errp, err);
             return;
         }
-        usartbusdev = SYS_BUS_DEVICE(usartdev);
-        sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
-        sysbus_connect_irq(usartbusdev, 0,
-                           qdev_get_gpio_in(nvic, usart_irq[i]));
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
     }
 
     /* Timer 2 to 5 */
     for (i = 0; i < STM_NUM_TIMERS; i++) {
-        timerdev = DEVICE(&(s->timer[i]));
-        qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
+        dev = DEVICE(&(s->timer[i]));
+        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
         if (err != NULL) {
             error_propagate(errp, err);
             return;
         }
-        timerbusdev = SYS_BUS_DEVICE(timerdev);
-        sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
-        sysbus_connect_irq(timerbusdev, 0,
-                           qdev_get_gpio_in(nvic, timer_irq[i]));
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, timer_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
     }
 }

Signature · 1 line

2.7.4

Alistair Francis

author

2016-09-24 19:21 UTC #2 lore raw

PATCH v8 2/8 STM32F2xx: Display PWM duty cycle from timer

In reply to Alistair Francis

If correctly configured allow the STM32F2xx timer to print out the PWM duty cycle information.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Crosthwaite <[email protected]>

---
V3:
- Use OR instead of + for masking
- Improve clarity of print statement
V2:
- Fix up if statement braces
- Remove stm32f2xx_timer_set_alarm() call

 hw/timer/stm32f2xx_timer.c | 9 +++++++++
 1 file changed, 9 insertions(+)

hw/timer/stm32f2xx_timer.c +9 -0

index bf0fb28..8c4c1f9 100644
@@ -51,6 +51,15 @@ static void stm32f2xx_timer_interrupt(void *opaque)
         qemu_irq_pulse(s->irq);
         stm32f2xx_timer_set_alarm(s, s->hit_time);
     }
+
+    if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) &&
+        !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
+        s->tim_ccmr1 & TIM_CCMR1_OC2PE &&
+        s->tim_ccer & TIM_CCER_CC2E) {
+        /* PWM 2 - Mode 1 */
+        DB_PRINT("PWM2 Duty Cycle: %d%%\n",
+                s->tim_ccr2 / (100 * (s->tim_psc + 1)));
+    }
 }
 
 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)

Signature · 1 line

2.7.4

Alistair Francis

author

2016-09-24 19:21 UTC #3 lore raw

PATCH v8 3/8 STM32F2xx: Add the ADC device

In reply to Alistair Francis

Add the STM32F2xx ADC device. This device randomly generates values on each read.

This also includes creating a hw/adc directory.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Maydell <[email protected]>

---
V4:
- Remove the rand() function
- Add VMState
- Small cleanups
V2:
- Address Peter C's comments
- Create a ADC folder and move the file in there
- Move some of the registers into arrays

 default-configs/arm-softmmu.mak |   1 +
 hw/Makefile.objs                |   1 +
 hw/adc/Makefile.objs            |   1 +
 hw/adc/stm32f2xx_adc.c          | 306 ++++++++++++++++++++++++++++++++++++++++
 include/hw/adc/stm32f2xx_adc.h  |  87 ++++++++++++
 5 files changed, 396 insertions(+)
 create mode 100644 hw/adc/Makefile.objs
 create mode 100644 hw/adc/stm32f2xx_adc.c
 create mode 100644 include/hw/adc/stm32f2xx_adc.h

default-configs/arm-softmmu.mak +1 -0

index e124360..3379b55 100644
@@ -86,6 +86,7 @@ CONFIG_ZYNQ=y
 CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
 CONFIG_STM32F2XX_SYSCFG=y
+CONFIG_STM32F2XX_ADC=y
 CONFIG_STM32F205_SOC=y
 
 CONFIG_VERSATILE_PCI=y

hw/Makefile.objs +1 -0

index 4a07ed4..0ffd281 100644
@@ -1,5 +1,6 @@
 devices-dirs-$(call land, $(CONFIG_VIRTIO),$(call land,$(CONFIG_VIRTFS),$(CONFIG_PCI))) += 9pfs/
 devices-dirs-$(CONFIG_ACPI) += acpi/
+devices-dirs-$(CONFIG_SOFTMMU) += adc/
 devices-dirs-$(CONFIG_SOFTMMU) += audio/
 devices-dirs-$(CONFIG_SOFTMMU) += block/
 devices-dirs-$(CONFIG_SOFTMMU) += bt/

hw/adc/Makefile.objs new file +1 -0

new file mode 100644
index 0000000..3f6dfde
@@ -0,0 +1 @@
+obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o

hw/adc/stm32f2xx_adc.c new file +306 -0

306 lines not on this page · raw message

include/hw/adc/stm32f2xx_adc.h new file +87 -0

87 lines not on this page · raw message

Signature · 1 line

2.7.4

Alistair Francis

author

2016-09-24 19:21 UTC #4 lore raw

PATCH v8 4/8 STM32F2xx: Add the SPI device

In reply to Alistair Francis

Add the STM32F2xx SPI device.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Maydell <[email protected]>

---
V4:
- Add VMState
- Small fixes
V2:
- Address Peter C's comments

 default-configs/arm-softmmu.mak |   1 +
 hw/ssi/Makefile.objs            |   1 +
 hw/ssi/stm32f2xx_spi.c          | 225 ++++++++++++++++++++++++++++++++++++++++
 include/hw/ssi/stm32f2xx_spi.h  |  72 +++++++++++++
 4 files changed, 299 insertions(+)
 create mode 100644 hw/ssi/stm32f2xx_spi.c
 create mode 100644 include/hw/ssi/stm32f2xx_spi.h

default-configs/arm-softmmu.mak +1 -0

index 3379b55..6de3e16 100644
@@ -87,6 +87,7 @@ CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
 CONFIG_STM32F2XX_SYSCFG=y
 CONFIG_STM32F2XX_ADC=y
+CONFIG_STM32F2XX_SPI=y
 CONFIG_STM32F205_SOC=y
 
 CONFIG_VERSATILE_PCI=y

hw/ssi/Makefile.objs +1 -0

index c79a8dc..487add2 100644
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_SSI) += ssi.o
 common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
 common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
+common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
 
 obj-$(CONFIG_OMAP) += omap_spi.o
 obj-$(CONFIG_IMX) += imx_spi.o

hw/ssi/stm32f2xx_spi.c new file +225 -0

225 lines not on this page · raw message

include/hw/ssi/stm32f2xx_spi.h new file +72 -0

72 lines not on this page · raw message

Signature · 1 line

2.7.4

Alistair Francis

author

2016-09-24 19:21 UTC #5 lore raw

PATCH v8 5/8 irq: Add a new irq device that allows the ORing of lines

In reply to Alistair Francis

Signed-off-by Alistair Francis <[email protected]>

---
As the migration framework is not included in user mode this needs to be a new file.

V8:
- Use the standard qdev_init_gpio_in() function
V7:
- Use the standard QEMU init/realise functions
V6:
- Make the OR IRQ device a TYPE_DEVICE
- Add vmstate

 hw/core/Makefile.objs |   1 +
 hw/core/or-irq.c      | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/or-irq.h   |  44 +++++++++++++++++++++
 3 files changed, 152 insertions(+)
 create mode 100644 hw/core/or-irq.c
 create mode 100644 include/hw/or-irq.h

hw/core/Makefile.objs +1 -0

index cfd4840..b47241b 100644
@@ -16,4 +16,5 @@ common-obj-$(CONFIG_SOFTMMU) += null-machine.o
 common-obj-$(CONFIG_SOFTMMU) += loader.o
 common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
 common-obj-$(CONFIG_SOFTMMU) += register.o
+common-obj-$(CONFIG_SOFTMMU) += or-irq.o
 common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o

hw/core/or-irq.c new file +107 -0

107 lines not on this page · raw message

include/hw/or-irq.h new file +44 -0

44 lines not on this page · raw message

Signature · 1 line

2.7.4

Peter Maydell

Reviewed-by on v8 5/8

2016-09-29 23:54 UTC #6 lore raw

Re: [Qemu-devel] [PATCH v8 5/8] irq: Add a new irq device that allows the ORing of lines

Quoted 5 lines · Alistair Francis

Signed-off-by Alistair Francis <[email protected]>
---
As the migration framework is not included in user mode this needs to be a new file.

Quoted 7 lines

V8:
- Use the standard qdev_init_gpio_in() function
V7:
- Use the standard QEMU init/realise functions
V6:
- Make the OR IRQ device a TYPE_DEVICE
- Add vmstate

Reviewed-by Peter Maydell <[email protected]>

thanks
-- PMM

Alistair Francis

author

2016-09-30 00:43 UTC #7 lore raw

Re: [Qemu-devel] [PATCH v8 5/8] irq: Add a new irq device that allows the ORing of lines

Quoted 14 lines · Peter Maydell

Quoted 5 lines · Alistair Francis
Signed-off-by Alistair Francis <[email protected]>
---
As the migration framework is not included in user mode this needs to be a new file.
Quoted 7 lines
V8:
- Use the standard qdev_init_gpio_in() function
V7:
- Use the standard QEMU init/realise functions
V6:
- Make the OR IRQ device a TYPE_DEVICE
- Add vmstate

Quoted 1 line

Reviewed-by Peter Maydell <[email protected]>

Thanks!

Quoted 3 lines

thanks
-- PMM

Alistair Francis

author

2016-09-24 19:21 UTC #8 lore raw

PATCH v8 6/8 STM32F205: Connect the ADC devices

In reply to Alistair Francis

Connect the ADC devices to the STM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

---
V7:
- Create the new ADC device
V5:
- Use the new irq ORing function
V4:
- Connect all the interrupt lines correctly
V2:
- Fix up the device/devices commit message

 hw/arm/stm32f205_soc.c         | 35 +++++++++++++++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  6 ++++++
 2 files changed, 41 insertions(+)

hw/arm/stm32f205_soc.c +35 -0

index 5b6fa3b..2feddc3 100644
@@ -34,9 +34,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
     0x40000800, 0x40000C00 };
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
+    0x40012200 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+#define ADC_IRQ 18
 
 static void stm32f205_soc_initfn(Object *obj)
 {

@@ -57,6 +60,14 @@ static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_TIMER);
         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
     }
+
+    s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        object_initialize(&s->adc[i], sizeof(s->adc[i]),
+                          TYPE_STM32F2XX_ADC);
+        qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -132,6 +143,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
     }
+
+    /* ADC 1 to 3 */
+    object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
+                            "num-lines", &err);
+    object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
+                          qdev_get_gpio_in(nvic, ADC_IRQ));
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, adc_addr[i]);
+        sysbus_connect_irq(busdev, 0,
+                           qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
+    }
 }
 
 static Property stm32f205_soc_properties[] = {

include/hw/arm/stm32f205_soc.h +6 -0

index 779b5da..1adf824 100644
@@ -28,6 +28,8 @@
 #include "hw/misc/stm32f2xx_syscfg.h"
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
+#include "hw/adc/stm32f2xx_adc.h"
+#include "hw/or-irq.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \

@@ -35,6 +37,7 @@
 
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)

@@ -52,6 +55,9 @@ typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXADCState adc[STM_NUM_ADCS];
+
+    qemu_or_irq *adc_irqs;
 } STM32F205State;
 
 #endif

Signature · 1 line

2.7.4

Peter Maydell

2016-09-29 23:59 UTC #9 lore raw

Re: [Qemu-devel] [PATCH v8 6/8] STM32F205: Connect the ADC devices

Quoted 8 lines · Alistair Francis

Connect the ADC devices to the STM32F205 SoC.
Signed-off-by Alistair Francis <[email protected]>
---
#define FLASH_BASE_ADDRESS 0x08000000
#define FLASH_SIZE (1024 * 1024)

include/hw/arm/stm32f205_soc.h typedef struct STM32F205State { · line 60

Quoted 6 lines

include/hw/arm/stm32f205_soc.h +3 -0

@@ -52,6 +55,9 @@ typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXADCState adc[STM_NUM_ADCS];
+
+    qemu_or_irq *adc_irqs;

Seems mildly inconsistent that all the other devices "owned" by this SoC are embedded in the struct but this one is a pointer (and so initialized via object_new() rather than object_initialized()).

That's not a big deal though, so I've applied this series to target-arm.next; you can change the above in a followup patch, or not, as you choose.

Quoted 5 lines

include/hw/arm/stm32f205_soc.h +0 -1
 } STM32F205State;
 
 #endif
--
2.7.4

thanks
-- PMM

Alistair Francis

author

2016-09-30 00:45 UTC #10 lore raw

Re: [Qemu-devel] [PATCH v8 6/8] STM32F205: Connect the ADC devices

Quoted 21 lines · Peter Maydell

Quoted 8 lines · Alistair Francis
Connect the ADC devices to the STM32F205 SoC.
Signed-off-by Alistair Francis <[email protected]>
---
#define FLASH_BASE_ADDRESS 0x08000000
#define FLASH_SIZE (1024 * 1024)
include/hw/arm/stm32f205_soc.h typedef struct STM32F205State { · line 60
Quoted 6 lines
include/hw/arm/stm32f205_soc.h +3 -0
@@ -52,6 +55,9 @@ typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXADCState adc[STM_NUM_ADCS];
+
+    qemu_or_irq *adc_irqs;
Seems mildly inconsistent that all the other devices "owned" by this SoC are embedded in the struct but this one is a pointer (and so initialized via object_new() rather than object_initialized()).

Quoted 3 lines

That's not a big deal though, so I've applied this series to target-arm.next; you can change the above in a followup patch, or not, as you choose.

Good point, I didn't really think of it like that.

I don't mind it this way, hopefully I will set up another patch series and I'll update it then if need be.

Thanks,

Alistair

Quoted 9 lines

Quoted 6 lines
include/hw/arm/stm32f205_soc.h +0 -1
 } STM32F205State;
 
 #endif
--
2.7.4
thanks
-- PMM

Alistair Francis

author

2016-09-24 19:21 UTC #11 lore raw

PATCH v8 7/8 STM32F205: Connect the SPI devices

In reply to Alistair Francis

Connect the SPI devices to the STM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Crosthwaite <[email protected]>

---
V2:
- Fix up the device/devices commit message

 hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  3 +++
 2 files changed, 25 insertions(+)

hw/arm/stm32f205_soc.c +22 -0

index 2feddc3..38425bd 100644
@@ -36,10 +36,13 @@ static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
     0x40012200 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
+    0x40003C00 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
 #define ADC_IRQ 18
+static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
 
 static void stm32f205_soc_initfn(Object *obj)
 {

@@ -68,6 +71,12 @@ static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_ADC);
         qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        object_initialize(&s->spi[i], sizeof(s->spi[i]),
+                          TYPE_STM32F2XX_SPI);
+        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -167,6 +176,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_connect_irq(busdev, 0,
                            qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
     }
+
+    /* SPI 1 and 2 */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
+    }
 }
 
 static Property stm32f205_soc_properties[] = {

include/hw/arm/stm32f205_soc.h +3 -0

index 1adf824..1332141 100644
@@ -30,6 +30,7 @@
 #include "hw/char/stm32f2xx_usart.h"
 #include "hw/adc/stm32f2xx_adc.h"
 #include "hw/or-irq.h"
+#include "hw/ssi/stm32f2xx_spi.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \

@@ -38,6 +39,7 @@
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
 #define STM_NUM_ADCS 3
+#define STM_NUM_SPIS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)

@@ -56,6 +58,7 @@ typedef struct STM32F205State {
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
     STM32F2XXADCState adc[STM_NUM_ADCS];
+    STM32F2XXSPIState spi[STM_NUM_SPIS];
 
     qemu_or_irq *adc_irqs;
 } STM32F205State;

Signature · 1 line

2.7.4

Alistair Francis

author

2016-09-24 19:21 UTC #12 lore raw

PATCH v8 8/8 MAINTAINERS: Add Alistair to the maintainers list

In reply to Alistair Francis

Add Alistair Francis as the maintainer for the Netduino 2 and SMM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Crosthwaite <[email protected]>

---

 MAINTAINERS | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

MAINTAINERS +15 -0

index a3a2ad7..30b1155 100644
@@ -479,6 +479,21 @@ S: Maintained
 F: hw/arm/virt-acpi-build.c
 F: include/hw/arm/virt-acpi-build.h
 
+STM32F205
+M: Alistair Francis <[email protected]>
+S: Maintained
+F: hw/arm/stm32f205_soc.c
+F: hw/misc/stm32f2xx_syscfg.c
+F: hw/char/stm32f2xx_usart.c
+F: hw/timer/stm32f2xx_timer.c
+F: hw/adc/*
+F: hw/ssi/stm32f2xx_spi.c
+
+Netduino 2
+M: Alistair Francis <[email protected]>
+S: Maintained
+F: hw/arm/netduino2.c
+
 CRIS Machines
 -------------
 Axis Dev88

Signature · 1 line

2.7.4