Update the Netduino 2 Machine

Cleanup the individual DeviceState and SysBusDevice variables to re-use the same variable for each device.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/arm/stm32f205_soc.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

hw/arm/stm32f205_soc.c +15 -16

index 0f3bdc7..63893f3 100644
@@ -59,8 +59,8 @@ static void stm32f205_soc_initfn(Object *obj)
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
 {
     STM32F205State *s = STM32F205_SOC(dev_soc);
-    DeviceState *syscfgdev, *usartdev, *timerdev;
-    SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
+    DeviceState *dev;
+    SysBusDevice *busdev;
     qemu_irq *pic;
     Error *err = NULL;
     int i;

@@ -92,41 +92,41 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
                       s->kernel_filename, s->cpu_model);
 
     /* System configuration controller */
-    syscfgdev = DEVICE(&s->syscfg);
+    dev = DEVICE(&s->syscfg);
     object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
     if (err != NULL) {
         error_propagate(errp, err);
         return;
     }
-    syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
-    sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
-    sysbus_connect_irq(syscfgbusdev, 0, pic[71]);
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, 0x40013800);
+    sysbus_connect_irq(busdev, 0, pic[71]);
 
     /* Attach UART (uses USART registers) and USART controllers */
     for (i = 0; i < STM_NUM_USARTS; i++) {
-        usartdev = DEVICE(&(s->usart[i]));
+        dev = DEVICE(&(s->usart[i]));
         object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
         if (err != NULL) {
             error_propagate(errp, err);
             return;
         }
-        usartbusdev = SYS_BUS_DEVICE(usartdev);
-        sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
-        sysbus_connect_irq(usartbusdev, 0, pic[usart_irq[i]]);
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[usart_irq[i]]);
     }
 
     /* Timer 2 to 5 */
     for (i = 0; i < STM_NUM_TIMERS; i++) {
-        timerdev = DEVICE(&(s->timer[i]));
-        qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
+        dev = DEVICE(&(s->timer[i]));
+        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
         if (err != NULL) {
             error_propagate(errp, err);
             return;
         }
-        timerbusdev = SYS_BUS_DEVICE(timerdev);
-        sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
-        sysbus_connect_irq(timerbusdev, 0, pic[timer_irq[i]]);
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, timer_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[timer_irq[i]]);
     }
 }
 
--

2.1.4

Quoted 5 lines · Alistair Francis

Cleanup the individual DeviceState and SysBusDevice variables to re-use the same variable for each device.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Crosthwaite <[email protected]>

Quoted 80 lines

---

 hw/arm/stm32f205_soc.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

hw/arm/stm32f205_soc.c +15 -16

index 0f3bdc7..63893f3 100644
@@ -59,8 +59,8 @@ static void stm32f205_soc_initfn(Object *obj)
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
 {
     STM32F205State *s = STM32F205_SOC(dev_soc);
-    DeviceState *syscfgdev, *usartdev, *timerdev;
-    SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
+    DeviceState *dev;
+    SysBusDevice *busdev;
     qemu_irq *pic;
     Error *err = NULL;
     int i;

@@ -92,41 +92,41 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
                       s->kernel_filename, s->cpu_model);
 
     /* System configuration controller */
-    syscfgdev = DEVICE(&s->syscfg);
+    dev = DEVICE(&s->syscfg);
     object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
     if (err != NULL) {
         error_propagate(errp, err);
         return;
     }
-    syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
-    sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
-    sysbus_connect_irq(syscfgbusdev, 0, pic[71]);
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, 0x40013800);
+    sysbus_connect_irq(busdev, 0, pic[71]);
 
     /* Attach UART (uses USART registers) and USART controllers */
     for (i = 0; i < STM_NUM_USARTS; i++) {
-        usartdev = DEVICE(&(s->usart[i]));
+        dev = DEVICE(&(s->usart[i]));
         object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
         if (err != NULL) {
             error_propagate(errp, err);
             return;
         }
-        usartbusdev = SYS_BUS_DEVICE(usartdev);
-        sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
-        sysbus_connect_irq(usartbusdev, 0, pic[usart_irq[i]]);
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[usart_irq[i]]);
     }
 
     /* Timer 2 to 5 */
     for (i = 0; i < STM_NUM_TIMERS; i++) {
-        timerdev = DEVICE(&(s->timer[i]));
-        qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
+        dev = DEVICE(&(s->timer[i]));
+        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
         if (err != NULL) {
             error_propagate(errp, err);
             return;
         }
-        timerbusdev = SYS_BUS_DEVICE(timerdev);
-        sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
-        sysbus_connect_irq(timerbusdev, 0, pic[timer_irq[i]]);
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, timer_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[timer_irq[i]]);
     }
 }
 
--

2.1.4

If correctly configured allow the STM32F2xx timer to print out the PWM duty cycle information.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/timer/stm32f2xx_timer.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

hw/timer/stm32f2xx_timer.c +0 -0

index ecadf9d..6f463e8 100644

hw/timer/stm32f2xx_timer.c +1 -1

+    }
 }
 
 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
--

2.1.4

Quoted 9 lines · Alistair Francis

If correctly configured allow the STM32F2xx timer to print out the PWM duty cycle information.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/timer/stm32f2xx_timer.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

hw/timer/stm32f2xx_timer.c static void stm32f2xx_timer_interrupt(void *opaque) · line 55

Quoted 12 lines

hw/timer/stm32f2xx_timer.c +4 -0

index ecadf9d..6f463e8 100644
@@ -49,6 +49,16 @@ static void stm32f2xx_timer_interrupt(void *opaque)
         qemu_irq_pulse(s->irq);
         stm32f2xx_timer_set_alarm(s, s->hit_time);
     }
+
+    if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 + TIM_CCMR1_OC2M1) &&
+        !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
+        (s->tim_ccmr1 & TIM_CCMR1_OC2PE) &&

Bracing looks inconsistent. Can you drop this set of () to make it consistent with one below?

hw/timer/stm32f2xx_timer.c static void stm32f2xx_timer_interrupt(void *opaque) · line 60

Quoted 6 lines

hw/timer/stm32f2xx_timer.c +5 -0

+        s->tim_ccer & TIM_CCER_CC2E) {
+        /* PWM 2 - Mode 1 */
+        DB_PRINT("Duty Cycle: %d%%\n",
+                s->tim_ccr2 / (100 * (s->tim_psc + 1)));
+        stm32f2xx_timer_set_alarm(s, s->hit_time);

This looks like a functional change - why do you need to set the alarm for PWM? Commit messages suggests this is supposed to just add debug printfs.

Regards,
Peter

Quoted 8 lines

hw/timer/stm32f2xx_timer.c +1 -1

+    }
 }
 
 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
--

2.1.4

Add the STM32F2xx ADC device. This device randomly generates values on each read.

Signed-off-by Alistair Francis <[email protected]>

---

 default-configs/arm-softmmu.mak |   1 +
 hw/misc/Makefile.objs           |   1 +
 hw/misc/stm32f2xx_adc.c         | 332 ++++++++++++++++++++++++++++++++++++++++
 include/hw/misc/stm32f2xx_adc.h |  96 ++++++++++++
 4 files changed, 430 insertions(+)
 create mode 100644 hw/misc/stm32f2xx_adc.c
 create mode 100644 include/hw/misc/stm32f2xx_adc.h

default-configs/arm-softmmu.mak +1 -0

index a767e4b..2b16590 100644
@@ -84,6 +84,7 @@ CONFIG_ZYNQ=y
 CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
 CONFIG_STM32F2XX_SYSCFG=y
+CONFIG_STM32F2XX_ADC=y
 CONFIG_STM32F205_SOC=y
 
 CONFIG_VERSATILE_PCI=y

hw/misc/Makefile.objs +1 -0

index 4aa76ff..b65ec3d 100644
@@ -37,6 +37,7 @@ obj-$(CONFIG_OMAP) += omap_tap.o
 obj-$(CONFIG_SLAVIO) += slavio_misc.o
 obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
+obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_EDU) += edu.o

hw/misc/stm32f2xx_adc.c new file +18 -0

new file mode 100644
index 0000000..659f14f
@@ -0,0 +1,332 @@
+/*
+ * STM32F2XX ADC
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

hw/misc/stm32f2xx_adc.c new file +26 -0

+#ifndef STM_ADC_ERR_DEBUG
+#define STM_ADC_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (STM_ADC_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt, __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_adc_reset(DeviceState *dev)
+{
+    STM32F2XXAdcState *s = STM32F2XX_ADC(dev);
+
+    s->adc_sr = 0x00000000;
+    s->adc_cr1 = 0x00000000;
+    s->adc_cr2 = 0x00000000;
+    s->adc_smpr1 = 0x00000000;
+    s->adc_smpr2 = 0x00000000;
+    s->adc_jofr1 = 0x00000000;
+    s->adc_jofr2 = 0x00000000;
+    s->adc_jofr3 = 0x00000000;
+    s->adc_jofr4 = 0x00000000;
+    s->adc_htr = 0x00000FFF;

hw/misc/stm32f2xx_adc.c new file +16 -0

+    } else if (((s->adc_cr1 & ADC_CR1_RES) >> 24) == 1) {
+        /* 10-bit */
+        s->adc_dr = s->adc_dr & 0x3FF;
+    } else if (((s->adc_cr1 & ADC_CR1_RES) >> 24) == 2) {
+        /* 8-bit */
+        s->adc_dr = s->adc_dr & 0xFF;
+    } else {
+        /* 6-bit */
+        s->adc_dr = s->adc_dr & 0x3F;
+    }
+
+    if (s->adc_cr2 & ADC_CR2_ALIGN) {
+        return (s->adc_dr << 1) & 0xFFF0;
+    } else {
+        return s->adc_dr;
+    }

hw/misc/stm32f2xx_adc.c new file +9 -0

+        qemu_log_mask(LOG_UNIMP,
+                      "%s: ADC Common Register Unsupported\n", __func__);
+    }
+
+    switch (addr) {
+    case ADC_SR:
+        return s->adc_sr;
+    case ADC_CR1:
+        return s->adc_cr1;

hw/misc/stm32f2xx_adc.c new file +9 -0

+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jofr2;
+    case ADC_JOFR3:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jofr3;

hw/misc/stm32f2xx_adc.c new file +177 -0

+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr1 - s->adc_jofr1;
+    case ADC_JDR2:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr2 - s->adc_jofr2;
+    case ADC_JDR3:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr3 - s->adc_jofr3;
+    case ADC_JDR4:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr4 - s->adc_jofr4;
+    case ADC_DR:
+        if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) {
+            s->adc_cr2 ^= ADC_CR2_SWSTART;
+            return stm32f2xx_adc_generate_value(s);
+        } else {
+            return 0x00000000;
+        }
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+
+    return 0;
+}
+
+static void stm32f2xx_adc_write(void *opaque, hwaddr addr,
+                       uint64_t val64, unsigned int size)
+{
+    STM32F2XXAdcState *s = opaque;
+    uint32_t value = (uint32_t) val64;
+
+    DB_PRINT("%s: Address: 0x%"HWADDR_PRIx", Value: 0x%x\n",
+             __func__, addr, value);
+
+    if (addr >= 0x100) {
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: ADC Common Register Unsupported\n", __func__);
+    }
+
+    switch (addr) {
+    case ADC_SR:
+        s->adc_sr &= (value & 0x3F);
+        break;
+    case ADC_CR1:
+        s->adc_cr1 = value;
+        break;
+    case ADC_CR2:
+        s->adc_cr2 = value;
+        break;
+    case ADC_SMPR1:
+        s->adc_smpr1 = value;
+        break;
+    case ADC_SMPR2:
+        s->adc_smpr2 = value;
+        break;
+    case ADC_JOFR1:
+        s->adc_jofr1 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JOFR2:
+        s->adc_jofr2 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JOFR3:
+        s->adc_jofr3 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JOFR4:
+        s->adc_jofr4 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_HTR:
+        s->adc_htr = value;
+        break;
+    case ADC_LTR:
+        s->adc_ltr = value;
+        break;
+    case ADC_SQR1:
+        s->adc_sqr1 = value;
+        break;
+    case ADC_SQR2:
+        s->adc_sqr2 = value;
+        break;
+    case ADC_SQR3:
+        s->adc_sqr3 = value;
+        break;
+    case ADC_JSQR:
+        s->adc_jsqr = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR1:
+        s->adc_jdr1 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR2:
+        s->adc_jdr2 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR3:
+        s->adc_jdr3 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR4:
+        s->adc_jdr4 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps stm32f2xx_adc_ops = {
+    .read = stm32f2xx_adc_read,
+    .write = stm32f2xx_adc_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f2xx_adc_init(Object *obj)
+{
+    STM32F2XXAdcState *s = STM32F2XX_ADC(obj);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
+                          TYPE_STM32F2XX_ADC, 0xFF);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f2xx_adc_reset;
+}
+
+static const TypeInfo stm32f2xx_adc_info = {
+    .name          = TYPE_STM32F2XX_ADC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F2XXAdcState),
+    .instance_init = stm32f2xx_adc_init,
+    .class_init    = stm32f2xx_adc_class_init,
+};
+
+static void stm32f2xx_adc_register_types(void)
+{
+    type_register_static(&stm32f2xx_adc_info);
+}
+
+type_init(stm32f2xx_adc_register_types)

include/hw/misc/stm32f2xx_adc.h new file +45 -0

new file mode 100644
index 0000000..e0ec1d7
@@ -0,0 +1,96 @@
+/*
+ * STM32F2XX ADC
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_ADC_H
+#define HW_STM32F2XX_ADC_H
+
+#define ADC_SR    0x00
+#define ADC_CR1   0x04
+#define ADC_CR2   0x08
+#define ADC_SMPR1 0x0C
+#define ADC_SMPR2 0x10
+#define ADC_JOFR1 0x14
+#define ADC_JOFR2 0x18
+#define ADC_JOFR3 0x1C
+#define ADC_JOFR4 0x20
+#define ADC_HTR   0x24
+#define ADC_LTR   0x28
+#define ADC_SQR1  0x2C
+#define ADC_SQR2  0x30
+#define ADC_SQR3  0x34
+#define ADC_JSQR  0x38
+#define ADC_JDR1  0x3C
+#define ADC_JDR2  0x40
+#define ADC_JDR3  0x44

include/hw/misc/stm32f2xx_adc.h new file +15 -0

+    MemoryRegion mmio;
+
+    uint32_t adc_sr;
+    uint32_t adc_cr1;
+    uint32_t adc_cr2;
+    uint32_t adc_smpr1;
+    uint32_t adc_smpr2;
+    uint32_t adc_jofr1;
+    uint32_t adc_jofr2;
+    uint32_t adc_jofr3;
+    uint32_t adc_jofr4;
+    uint32_t adc_htr;
+    uint32_t adc_ltr;
+    uint32_t adc_sqr1;
+    uint32_t adc_sqr2;

include/hw/misc/stm32f2xx_adc.h new file +2 -1

+
+#endif /* HW_STM32F2XX_ADC_H */
--

2.1.4

Quoted 68 lines · Alistair Francis

Add the STM32F2xx ADC device. This device randomly generates values on each read.

Signed-off-by Alistair Francis <[email protected]>

---

 default-configs/arm-softmmu.mak |   1 +
 hw/misc/Makefile.objs           |   1 +
 hw/misc/stm32f2xx_adc.c         | 332 ++++++++++++++++++++++++++++++++++++++++
 include/hw/misc/stm32f2xx_adc.h |  96 ++++++++++++
 4 files changed, 430 insertions(+)
 create mode 100644 hw/misc/stm32f2xx_adc.c
 create mode 100644 include/hw/misc/stm32f2xx_adc.h

default-configs/arm-softmmu.mak +1 -0

index a767e4b..2b16590 100644
@@ -84,6 +84,7 @@ CONFIG_ZYNQ=y
 CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
 CONFIG_STM32F2XX_SYSCFG=y
+CONFIG_STM32F2XX_ADC=y
 CONFIG_STM32F205_SOC=y
 
 CONFIG_VERSATILE_PCI=y

hw/misc/Makefile.objs +1 -0

index 4aa76ff..b65ec3d 100644
@@ -37,6 +37,7 @@ obj-$(CONFIG_OMAP) += omap_tap.o
 obj-$(CONFIG_SLAVIO) += slavio_misc.o
 obj-$(CONFIG_ZYNQ) += zynq_slcr.o
 obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
+obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_EDU) += edu.o

hw/misc/stm32f2xx_adc.c new file +24 -0

new file mode 100644
index 0000000..659f14f
@@ -0,0 +1,332 @@
+/*
+ * STM32F2XX ADC
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+

hw/misc/stm32f2xx_adc.c line 28

Quoted 4 lines

hw/misc/stm32f2xx_adc.c new file +4 -0

+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/misc/stm32f2xx_adc.h"
+

Misc is starting to pile up in random features whereas ADC seems to be a nice self contained category. Can we create hw/adc? Are there any other ADCs in misc?

Quoted 36 lines

hw/misc/stm32f2xx_adc.c new file +35 -0

+#ifndef STM_ADC_ERR_DEBUG
+#define STM_ADC_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (STM_ADC_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt, __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_adc_reset(DeviceState *dev)
+{
+    STM32F2XXAdcState *s = STM32F2XX_ADC(dev);
+
+    s->adc_sr = 0x00000000;
+    s->adc_cr1 = 0x00000000;
+    s->adc_cr2 = 0x00000000;
+    s->adc_smpr1 = 0x00000000;
+    s->adc_smpr2 = 0x00000000;
+    s->adc_jofr1 = 0x00000000;
+    s->adc_jofr2 = 0x00000000;
+    s->adc_jofr3 = 0x00000000;
+    s->adc_jofr4 = 0x00000000;
+    s->adc_htr = 0x00000FFF;
+    s->adc_ltr = 0x00000000;
+    s->adc_sqr1 = 0x00000000;
+    s->adc_sqr2 = 0x00000000;
+    s->adc_sqr3 = 0x00000000;
+    s->adc_jsqr = 0x00000000;
+    s->adc_jdr1 = 0x00000000;
+    s->adc_jdr2 = 0x00000000;
+    s->adc_jdr3 = 0x00000000;
+    s->adc_jdr4 = 0x00000000;

hw/misc/stm32f2xx_adc.c line 64

Quoted 1 line

hw/misc/stm32f2xx_adc.c new file +1 -0

+    s->adc_dr = 0x00000000;

I'm guessing the documentation prefixes all the register symbolic names with "ADC". In these cases where the doc adds such prefixes I usually drop them from variables names as the doc is usually documenting them as part of a bigger register block. In this case the fact that it is adc is implicit so can the prefix be dropped and save some text?

hw/misc/stm32f2xx_adc.c line 70

Quoted 7 lines

hw/misc/stm32f2xx_adc.c new file +6 -0

+}
+
+static uint32_t stm32f2xx_adc_generate_value(STM32F2XXAdcState *s)
+{
+    /* Attempts to fake some ADC values */
+    #ifdef RAND_AVALIABLE

#ifdef should be non-indented.

Although I have been thinking about this, and perhaps it is better to make the value (or its randomization factor) runtime controllable. Can you propertyify something and then you can set the ADC value from the monitor using a property setter? Even if it cannot be set from the monitor it might help to at least be start-time configurable using -global.

hw/misc/stm32f2xx_adc.c line 76

Quoted 7 lines

hw/misc/stm32f2xx_adc.c new file +6 -0

+    s->adc_dr = s->adc_dr + rand();
+    #else
+    s->adc_dr = s->adc_dr + 7;
+    #endif
+
+    if (((s->adc_cr1 & ADC_CR1_RES) >> 24) == 0) {

extract to get field value.

switch (s->adc_cr1 & ADC_CR1_RES) >> 24

But could be handled with:

bit_width = 12 - 2 * extract32(a->adc_cr1, ADC_CR1_RES_SHIFT, ADC_CR1_RES_LENGTH);
s->adc_dr &= (1 << bit_width) - 1;

hw/misc/stm32f2xx_adc.c line 78

Quoted 3 lines

hw/misc/stm32f2xx_adc.c new file +2 -0

+        /* 12-bit */
+        s->adc_dr = s->adc_dr & 0xFFF;

&=

Quoted 21 lines

hw/misc/stm32f2xx_adc.c new file +20 -0

+    } else if (((s->adc_cr1 & ADC_CR1_RES) >> 24) == 1) {
+        /* 10-bit */
+        s->adc_dr = s->adc_dr & 0x3FF;
+    } else if (((s->adc_cr1 & ADC_CR1_RES) >> 24) == 2) {
+        /* 8-bit */
+        s->adc_dr = s->adc_dr & 0xFF;
+    } else {
+        /* 6-bit */
+        s->adc_dr = s->adc_dr & 0x3F;
+    }
+
+    if (s->adc_cr2 & ADC_CR2_ALIGN) {
+        return (s->adc_dr << 1) & 0xFFF0;
+    } else {
+        return s->adc_dr;
+    }
+}
+
+static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr,
+                                     unsigned int size)

hw/misc/stm32f2xx_adc.c line 104

Quoted 6 lines

hw/misc/stm32f2xx_adc.c new file +6 -0

+{
+    STM32F2XXAdcState *s = opaque;
+
+    DB_PRINT("%s: Address: 0x%"HWADDR_PRIx"\n", __func__, addr);
+
+    if (addr >= 0x100) {

Macro for register offset (even if unimplemented)

Quoted 10 lines

hw/misc/stm32f2xx_adc.c new file +9 -0

+        qemu_log_mask(LOG_UNIMP,
+                      "%s: ADC Common Register Unsupported\n", __func__);
+    }
+
+    switch (addr) {
+    case ADC_SR:
+        return s->adc_sr;
+    case ADC_CR1:
+        return s->adc_cr1;

hw/misc/stm32f2xx_adc.c line 123

Quoted 10 lines

hw/misc/stm32f2xx_adc.c new file +10 -0

+    case ADC_CR2:
+        return s->adc_cr2 & 0xFFFFFFF;
+    case ADC_SMPR1:
+        return s->adc_smpr1;
+    case ADC_SMPR2:
+        return s->adc_smpr2;
+    case ADC_JOFR1:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);

"included"

hw/misc/stm32f2xx_adc.c line 125

Quoted 3 lines

hw/misc/stm32f2xx_adc.c new file +2 -0

+        return s->adc_jofr1;
+    case ADC_JOFR2:

Can you use an array for the JOFRs as they are consecutive registers with the same semantics. Then the 4X repitition can be removed.

Quoted 10 lines

hw/misc/stm32f2xx_adc.c new file +9 -0

+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jofr2;
+    case ADC_JOFR3:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jofr3;

hw/misc/stm32f2xx_adc.c line 144

Quoted 10 lines

hw/misc/stm32f2xx_adc.c new file +10 -0

+    case ADC_JOFR4:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jofr4;
+    case ADC_HTR:
+        return s->adc_htr;
+    case ADC_LTR:
+        return s->adc_ltr;
+    case ADC_SQR1:

Same for SQRs

hw/misc/stm32f2xx_adc.c line 153

Quoted 10 lines

hw/misc/stm32f2xx_adc.c new file +9 -0

+        return s->adc_sqr1;
+    case ADC_SQR2:
+        return s->adc_sqr2;
+    case ADC_SQR3:
+        return s->adc_sqr3;
+    case ADC_JSQR:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);

"Included".

hw/misc/stm32f2xx_adc.c line 155

Quoted 2 lines

hw/misc/stm32f2xx_adc.c new file +2 -0

+        return s->adc_jsqr;
+    case ADC_JDR1:

Array here too.

Quoted 229 lines

hw/misc/stm32f2xx_adc.c new file +177 -0

+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr1 - s->adc_jofr1;
+    case ADC_JDR2:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr2 - s->adc_jofr2;
+    case ADC_JDR3:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr3 - s->adc_jofr3;
+    case ADC_JDR4:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        return s->adc_jdr4 - s->adc_jofr4;
+    case ADC_DR:
+        if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) {
+            s->adc_cr2 ^= ADC_CR2_SWSTART;
+            return stm32f2xx_adc_generate_value(s);
+        } else {
+            return 0x00000000;
+        }
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+
+    return 0;
+}
+
+static void stm32f2xx_adc_write(void *opaque, hwaddr addr,
+                       uint64_t val64, unsigned int size)
+{
+    STM32F2XXAdcState *s = opaque;
+    uint32_t value = (uint32_t) val64;
+
+    DB_PRINT("%s: Address: 0x%"HWADDR_PRIx", Value: 0x%x\n",
+             __func__, addr, value);
+
+    if (addr >= 0x100) {
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: ADC Common Register Unsupported\n", __func__);
+    }
+
+    switch (addr) {
+    case ADC_SR:
+        s->adc_sr &= (value & 0x3F);
+        break;
+    case ADC_CR1:
+        s->adc_cr1 = value;
+        break;
+    case ADC_CR2:
+        s->adc_cr2 = value;
+        break;
+    case ADC_SMPR1:
+        s->adc_smpr1 = value;
+        break;
+    case ADC_SMPR2:
+        s->adc_smpr2 = value;
+        break;
+    case ADC_JOFR1:
+        s->adc_jofr1 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JOFR2:
+        s->adc_jofr2 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JOFR3:
+        s->adc_jofr3 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JOFR4:
+        s->adc_jofr4 = (value & 0xFFF);
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_HTR:
+        s->adc_htr = value;
+        break;
+    case ADC_LTR:
+        s->adc_ltr = value;
+        break;
+    case ADC_SQR1:
+        s->adc_sqr1 = value;
+        break;
+    case ADC_SQR2:
+        s->adc_sqr2 = value;
+        break;
+    case ADC_SQR3:
+        s->adc_sqr3 = value;
+        break;
+    case ADC_JSQR:
+        s->adc_jsqr = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR1:
+        s->adc_jdr1 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR2:
+        s->adc_jdr2 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR3:
+        s->adc_jdr3 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    case ADC_JDR4:
+        s->adc_jdr4 = value;
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Injection ADC is not implemented, the registers are " \
+                      "includded for compatability\n", __func__);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps stm32f2xx_adc_ops = {
+    .read = stm32f2xx_adc_read,
+    .write = stm32f2xx_adc_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f2xx_adc_init(Object *obj)
+{
+    STM32F2XXAdcState *s = STM32F2XX_ADC(obj);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s,
+                          TYPE_STM32F2XX_ADC, 0xFF);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+}
+
+static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f2xx_adc_reset;
+}
+
+static const TypeInfo stm32f2xx_adc_info = {
+    .name          = TYPE_STM32F2XX_ADC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F2XXAdcState),
+    .instance_init = stm32f2xx_adc_init,
+    .class_init    = stm32f2xx_adc_class_init,
+};
+
+static void stm32f2xx_adc_register_types(void)
+{
+    type_register_static(&stm32f2xx_adc_info);
+}
+
+type_init(stm32f2xx_adc_register_types)

include/hw/misc/stm32f2xx_adc.h new file +45 -0

new file mode 100644
index 0000000..e0ec1d7
@@ -0,0 +1,96 @@
+/*
+ * STM32F2XX ADC
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_ADC_H
+#define HW_STM32F2XX_ADC_H
+
+#define ADC_SR    0x00
+#define ADC_CR1   0x04
+#define ADC_CR2   0x08
+#define ADC_SMPR1 0x0C
+#define ADC_SMPR2 0x10
+#define ADC_JOFR1 0x14
+#define ADC_JOFR2 0x18
+#define ADC_JOFR3 0x1C
+#define ADC_JOFR4 0x20
+#define ADC_HTR   0x24
+#define ADC_LTR   0x28
+#define ADC_SQR1  0x2C
+#define ADC_SQR2  0x30
+#define ADC_SQR3  0x34
+#define ADC_JSQR  0x38
+#define ADC_JDR1  0x3C
+#define ADC_JDR2  0x40
+#define ADC_JDR3  0x44

include/hw/misc/stm32f2xx_adc.h line 55

Quoted 10 lines

include/hw/misc/stm32f2xx_adc.h new file +10 -0

+#define ADC_JDR4  0x48
+#define ADC_DR    0x4C
+
+#define ADC_CR2_ADON    0x01
+#define ADC_CR2_CONT    0x02
+#define ADC_CR2_ALIGN   0x800
+#define ADC_CR2_SWSTART 0x40000000
+
+#define ADC_CR1_RES 0x3000000
+

I'm acutally starting to see a big problem with having the reg defs in the common header, as it is not namespace safe. If you have two periphs defining a reg with the same name in the same soc you get a collision. The only safe way to do it would be to preface every symbol with the full type name. This would be super verbose.

On the other side if we don't headerify them they are not available to test code.

Out of scope so don't need to do anything for now but maybe we need to start a top lvl thread.

include/hw/misc/stm32f2xx_adc.h line 62

Quoted 8 lines

include/hw/misc/stm32f2xx_adc.h new file +7 -0

+#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
+#define STM32F2XX_ADC(obj) \
+    OBJECT_CHECK(STM32F2XXAdcState, (obj), TYPE_STM32F2XX_ADC)
+
+#ifdef RAND_MAX
+/* The rand() function is avaliable */
+#define RAND_AVALIABLE

RAND_AVAILABLE

include/hw/misc/stm32f2xx_adc.h line 67

Quoted 6 lines

include/hw/misc/stm32f2xx_adc.h new file +5 -0

+#undef RAND_MAX
+#define RAND_MAX 0xFF
+#endif /* RAND_MAX */
+
+typedef struct {

/* <private> */

include/hw/misc/stm32f2xx_adc.h line 69

Quoted 2 lines

include/hw/misc/stm32f2xx_adc.h new file +2 -0

+    SysBusDevice parent_obj;
+

/* <public> */

Quoted 20 lines

include/hw/misc/stm32f2xx_adc.h new file +19 -0

+    MemoryRegion mmio;
+
+    uint32_t adc_sr;
+    uint32_t adc_cr1;
+    uint32_t adc_cr2;
+    uint32_t adc_smpr1;
+    uint32_t adc_smpr2;
+    uint32_t adc_jofr1;
+    uint32_t adc_jofr2;
+    uint32_t adc_jofr3;
+    uint32_t adc_jofr4;
+    uint32_t adc_htr;
+    uint32_t adc_ltr;
+    uint32_t adc_sqr1;
+    uint32_t adc_sqr2;
+    uint32_t adc_sqr3;
+    uint32_t adc_jsqr;
+    uint32_t adc_jdr1;
+    uint32_t adc_jdr2;

include/hw/misc/stm32f2xx_adc.h line 94

Quoted 6 lines

include/hw/misc/stm32f2xx_adc.h new file +6 -0

+    uint32_t adc_jdr3;
+    uint32_t adc_jdr4;
+    uint32_t adc_dr;
+
+    qemu_irq irq;
+} STM32F2XXAdcState;

STM32F2XXADCState

Regards,
Peter

Quoted 6 lines

include/hw/misc/stm32f2xx_adc.h new file +2 -1

+
+#endif /* HW_STM32F2XX_ADC_H */
--

2.1.4

Add the STM32F2xx SPI device.

Signed-off-by Alistair Francis <[email protected]>

---

 default-configs/arm-softmmu.mak |   1 +
 hw/ssi/Makefile.objs            |   1 +
 hw/ssi/stm32f2xx_spi.c          | 211 ++++++++++++++++++++++++++++++++++++++++
 include/hw/ssi/stm32f2xx_spi.h  |  74 ++++++++++++++
 4 files changed, 287 insertions(+)
 create mode 100644 hw/ssi/stm32f2xx_spi.c
 create mode 100644 include/hw/ssi/stm32f2xx_spi.h

default-configs/arm-softmmu.mak +1 -0

index 2b16590..580fac3 100644
@@ -85,6 +85,7 @@ CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
 CONFIG_STM32F2XX_SYSCFG=y
 CONFIG_STM32F2XX_ADC=y
+CONFIG_STM32F2XX_SPI=y
 CONFIG_STM32F205_SOC=y
 
 CONFIG_VERSATILE_PCI=y

hw/ssi/Makefile.objs +1 -0

index 9555825..c674247 100644
@@ -2,5 +2,6 @@ common-obj-$(CONFIG_PL022) += pl022.o
 common-obj-$(CONFIG_SSI) += ssi.o
 common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
+common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
 
 obj-$(CONFIG_OMAP) += omap_spi.o

hw/ssi/stm32f2xx_spi.c new file +51 -0

new file mode 100644
index 0000000..11bbdef
@@ -0,0 +1,211 @@
+/*
+ * STM32F405 SPI
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/ssi/stm32f2xx_spi.h"
+
+#ifndef STM_SPI_ERR_DEBUG
+#define STM_SPI_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (STM_SPI_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt, __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_spi_reset(DeviceState *dev)
+{
+    STM32F2XXSpiState *s = STM32F2XX_SPI(dev);
+
+    s->spi_cr1 = 0x00000000;
+    s->spi_cr2 = 0x00000000;
+    s->spi_sr = 0x0000000A;
+    s->spi_dr = 0x0000000C;
+    s->spi_crcpr = 0x00000007;
+    s->spi_rxcrcr = 0x00000000;
+    s->spi_txcrcr = 0x00000000;
+    s->spi_i2scfgr = 0x00000000;
+    s->spi_i2spr = 0x00000002;

hw/ssi/stm32f2xx_spi.c new file +4 -0

+
+    switch (addr) {
+    case STM_SPI_CR1:
+        return s->spi_cr1;

hw/ssi/stm32f2xx_spi.c new file +34 -0

+        return s->spi_txcrcr;
+    case STM_SPI_I2SCFGR:
+        qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+                      "are includded for compatability\n", __func__);
+        return s->spi_i2scfgr;
+    case STM_SPI_I2SPR:
+        qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+                      "are includded for compatability\n", __func__);
+        return s->spi_i2spr;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
+    }
+
+    return 0;
+}
+
+static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
+                                uint64_t val64, unsigned int size)
+{
+    STM32F2XXSpiState *s = opaque;
+    uint32_t value = val64;
+
+    DB_PRINT("Write 0x%x at 0x%"HWADDR_PRIx"\n", value, addr);
+
+    switch (addr) {
+    case STM_SPI_CR1:
+        s->spi_cr1 = value;
+        return;
+    case STM_SPI_CR2:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Interrupts and DMA are not implemented\n", __func__);
+        s->spi_cr2 = value;
+        return;

hw/ssi/stm32f2xx_spi.c new file +69 -0

+        s->spi_sr |= STM_SPI_SR_TXE;
+        s->spi_sr &= ~STM_SPI_SR_BSY;
+        return;
+    case STM_SPI_CRCPR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__);
+        return;
+    case STM_SPI_RXCRCR:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
+                      "0x%"HWADDR_PRIx"\n", __func__, addr);
+        return;
+    case STM_SPI_TXCRCR:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
+                      "0x%"HWADDR_PRIx"\n", __func__, addr);
+        return;
+    case STM_SPI_I2SCFGR:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "I2S is not implemented\n", __func__);
+        return;
+    case STM_SPI_I2SPR:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "I2S is not implemented\n", __func__);
+        return;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps stm32f2xx_spi_ops = {
+    .read = stm32f2xx_spi_read,
+    .write = stm32f2xx_spi_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f2xx_spi_init(Object *obj)
+{
+    STM32F2XXSpiState *s = STM32F2XX_SPI(obj);
+    DeviceState *dev = DEVICE(obj);
+
+    memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s,
+                          TYPE_STM32F2XX_SPI, 0x400);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    s->ssi = ssi_create_bus(dev, "ssi");
+}
+
+static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f2xx_spi_reset;
+}
+
+static const TypeInfo stm32f2xx_spi_info = {
+    .name          = TYPE_STM32F2XX_SPI,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F2XXSpiState),
+    .instance_init = stm32f2xx_spi_init,
+    .class_init    = stm32f2xx_spi_class_init,
+};
+
+static void stm32f2xx_spi_register_types(void)
+{
+    type_register_static(&stm32f2xx_spi_info);
+}
+
+type_init(stm32f2xx_spi_register_types)

include/hw/ssi/stm32f2xx_spi.h new file +62 -0

new file mode 100644
index 0000000..75dd6a8
@@ -0,0 +1,74 @@
+/*
+ * STM32F2XX SPI
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_SPI_H
+#define HW_STM32F2XX_SPI_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/ssi.h"
+
+#define STM_SPI_CR1     0x00
+#define STM_SPI_CR2     0x04
+#define STM_SPI_SR      0x08
+#define STM_SPI_DR      0x0C
+#define STM_SPI_CRCPR   0x10
+#define STM_SPI_RXCRCR  0x14
+#define STM_SPI_TXCRCR  0x18
+#define STM_SPI_I2SCFGR 0x1C
+#define STM_SPI_I2SPR   0x20
+
+#define STM_SPI_CR1_SPE  (1 << 6)
+#define STM_SPI_CR1_MSTR (1 << 2)
+
+#define STM_SPI_SR_BSY   (1 << 7)
+#define STM_SPI_SR_TXE   (1 << 1)
+#define STM_SPI_SR_RXNE   1
+
+#define TYPE_STM32F2XX_SPI "stm32f2xx-spi"
+#define STM32F2XX_SPI(obj) \
+    OBJECT_CHECK(STM32F2XXSpiState, (obj), TYPE_STM32F2XX_SPI)
+
+typedef struct {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+
+    uint32_t spi_cr1;
+    uint32_t spi_cr2;
+    uint32_t spi_sr;

include/hw/ssi/stm32f2xx_spi.h new file +2 -1

+
+#endif /* HW_STM32F2XX_SPI_H */
--

2.1.4

Quoted 97 lines · Alistair Francis

Add the STM32F2xx SPI device.

Signed-off-by Alistair Francis <[email protected]>

---

 default-configs/arm-softmmu.mak |   1 +
 hw/ssi/Makefile.objs            |   1 +
 hw/ssi/stm32f2xx_spi.c          | 211 ++++++++++++++++++++++++++++++++++++++++
 include/hw/ssi/stm32f2xx_spi.h  |  74 ++++++++++++++
 4 files changed, 287 insertions(+)
 create mode 100644 hw/ssi/stm32f2xx_spi.c
 create mode 100644 include/hw/ssi/stm32f2xx_spi.h

default-configs/arm-softmmu.mak +1 -0

index 2b16590..580fac3 100644
@@ -85,6 +85,7 @@ CONFIG_STM32F2XX_TIMER=y
 CONFIG_STM32F2XX_USART=y
 CONFIG_STM32F2XX_SYSCFG=y
 CONFIG_STM32F2XX_ADC=y
+CONFIG_STM32F2XX_SPI=y
 CONFIG_STM32F205_SOC=y
 
 CONFIG_VERSATILE_PCI=y

hw/ssi/Makefile.objs +1 -0

index 9555825..c674247 100644
@@ -2,5 +2,6 @@ common-obj-$(CONFIG_PL022) += pl022.o
 common-obj-$(CONFIG_SSI) += ssi.o
 common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
+common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
 
 obj-$(CONFIG_OMAP) += omap_spi.o

hw/ssi/stm32f2xx_spi.c new file +55 -0

new file mode 100644
index 0000000..11bbdef
@@ -0,0 +1,211 @@
+/*
+ * STM32F405 SPI
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/ssi/stm32f2xx_spi.h"
+
+#ifndef STM_SPI_ERR_DEBUG
+#define STM_SPI_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (STM_SPI_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt, __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f2xx_spi_reset(DeviceState *dev)
+{
+    STM32F2XXSpiState *s = STM32F2XX_SPI(dev);
+
+    s->spi_cr1 = 0x00000000;
+    s->spi_cr2 = 0x00000000;
+    s->spi_sr = 0x0000000A;
+    s->spi_dr = 0x0000000C;
+    s->spi_crcpr = 0x00000007;
+    s->spi_rxcrcr = 0x00000000;
+    s->spi_txcrcr = 0x00000000;
+    s->spi_i2scfgr = 0x00000000;
+    s->spi_i2spr = 0x00000002;
+}
+
+static void stm32f2xx_spi_transfer(STM32F2XXSpiState *s)
+{

hw/ssi/stm32f2xx_spi.c line 61

Quoted 6 lines

hw/ssi/stm32f2xx_spi.c new file +6 -0

+    DB_PRINT("Data to send: 0x%x\n", s->spi_dr);
+
+    s->spi_dr = ssi_transfer(s->ssi, s->spi_dr);
+    s->spi_sr |= STM_SPI_SR_RXNE;
+
+    DB_PRINT("Data recieved: 0x%x\n", s->spi_dr);

"received". I usually just us "tx" and "rx" in the strings though.

Using a %s __func__ you could probably dropthe sentance altogether.

hw/ssi/stm32f2xx_spi.c line 70

Quoted 10 lines

hw/ssi/stm32f2xx_spi.c new file +9 -0

+}
+
+static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
+                                     unsigned int size)
+{
+    STM32F2XXSpiState *s = opaque;
+    uint32_t retval;
+
+    DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);

__func__

Makes it sef contained and also consistent with ADC (and other devs).

Quoted 5 lines

hw/ssi/stm32f2xx_spi.c new file +4 -0

+
+    switch (addr) {
+    case STM_SPI_CR1:
+        return s->spi_cr1;

hw/ssi/stm32f2xx_spi.c line 84

Quoted 10 lines

hw/ssi/stm32f2xx_spi.c new file +10 -0

+    case STM_SPI_CR2:
+        qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n",
+                      __func__);
+        return s->spi_cr2;
+    case STM_SPI_SR:
+        retval = s->spi_sr;
+        return retval;
+    case STM_SPI_DR:
+        s->spi_sr |= STM_SPI_SR_BSY;
+        stm32f2xx_spi_transfer(s);

This seems unusual to trigger the actual SPI transfer using the read txn. This would mean that this would be a very long bus transaction as you need to wait for the actual SPI byte txrx to happen during a single MMIO read. This can be very slow. Does the transfer occur on the write instead?

From the data sheet it looks like the SPI transfer occurs on both reads/writes,

From the data sheet:

hw/ssi/stm32f2xx_spi.c line 86

Quoted 3 lines

hw/ssi/stm32f2xx_spi.c new file +2 -0

+        s->spi_sr &= ~STM_SPI_SR_RXNE;
+        s->spi_sr &= ~STM_SPI_SR_BSY;

This (and the |= of same above) should be unneeded as it will never be visible to the guest.

hw/ssi/stm32f2xx_spi.c line 90

Quoted 5 lines

hw/ssi/stm32f2xx_spi.c new file +4 -0

+        return s->spi_dr;
+    case STM_SPI_CRCPR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are includded for compatability\n", __func__);

"included"

hw/ssi/stm32f2xx_spi.c line 98

Quoted 9 lines

hw/ssi/stm32f2xx_spi.c new file +8 -0

+        return s->spi_crcpr;
+    case STM_SPI_RXCRCR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are includded for compatability\n", __func__);
+        return s->spi_rxcrcr;
+    case STM_SPI_TXCRCR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
+                      "are includded for compatability\n", __func__);

You could perhaps factor out a lot of this string into a const variable to avoid the repetition.

Quoted 35 lines

hw/ssi/stm32f2xx_spi.c new file +34 -0

+        return s->spi_txcrcr;
+    case STM_SPI_I2SCFGR:
+        qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+                      "are includded for compatability\n", __func__);
+        return s->spi_i2scfgr;
+    case STM_SPI_I2SPR:
+        qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
+                      "are includded for compatability\n", __func__);
+        return s->spi_i2spr;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
+                      __func__, addr);
+    }
+
+    return 0;
+}
+
+static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
+                                uint64_t val64, unsigned int size)
+{
+    STM32F2XXSpiState *s = opaque;
+    uint32_t value = val64;
+
+    DB_PRINT("Write 0x%x at 0x%"HWADDR_PRIx"\n", value, addr);
+
+    switch (addr) {
+    case STM_SPI_CR1:
+        s->spi_cr1 = value;
+        return;
+    case STM_SPI_CR2:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "Interrupts and DMA are not implemented\n", __func__);
+        s->spi_cr2 = value;
+        return;

hw/ssi/stm32f2xx_spi.c line 142

Quoted 10 lines

hw/ssi/stm32f2xx_spi.c new file +10 -0

+    case STM_SPI_SR:
+        /* Read only register, except for clearing the CRCERR bit, which
+         * is not supported
+         */
+        return;
+    case STM_SPI_DR:
+        s->spi_sr |= STM_SPI_SR_BSY;
+        s->spi_sr &= ~STM_SPI_SR_TXE;
+        s->spi_dr = value;
+        stm32f2xx_spi_transfer(s);

So it does a transfer on the write as well. This means there are actually two transfers per write/read pair. One will be read only, the other write only. It is possible to do concurrent read and write with this IP?

From what I get from the data sheet I don't think so. See the quote from

Quoted 142 lines

hw/ssi/stm32f2xx_spi.c new file +69 -0

+        s->spi_sr |= STM_SPI_SR_TXE;
+        s->spi_sr &= ~STM_SPI_SR_BSY;
+        return;
+    case STM_SPI_CRCPR:
+        qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__);
+        return;
+    case STM_SPI_RXCRCR:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
+                      "0x%"HWADDR_PRIx"\n", __func__, addr);
+        return;
+    case STM_SPI_TXCRCR:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
+                      "0x%"HWADDR_PRIx"\n", __func__, addr);
+        return;
+    case STM_SPI_I2SCFGR:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "I2S is not implemented\n", __func__);
+        return;
+    case STM_SPI_I2SPR:
+        qemu_log_mask(LOG_UNIMP, "%s: " \
+                      "I2S is not implemented\n", __func__);
+        return;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+    }
+}
+
+static const MemoryRegionOps stm32f2xx_spi_ops = {
+    .read = stm32f2xx_spi_read,
+    .write = stm32f2xx_spi_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void stm32f2xx_spi_init(Object *obj)
+{
+    STM32F2XXSpiState *s = STM32F2XX_SPI(obj);
+    DeviceState *dev = DEVICE(obj);
+
+    memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s,
+                          TYPE_STM32F2XX_SPI, 0x400);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    s->ssi = ssi_create_bus(dev, "ssi");
+}
+
+static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f2xx_spi_reset;
+}
+
+static const TypeInfo stm32f2xx_spi_info = {
+    .name          = TYPE_STM32F2XX_SPI,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F2XXSpiState),
+    .instance_init = stm32f2xx_spi_init,
+    .class_init    = stm32f2xx_spi_class_init,
+};
+
+static void stm32f2xx_spi_register_types(void)
+{
+    type_register_static(&stm32f2xx_spi_info);
+}
+
+type_init(stm32f2xx_spi_register_types)

include/hw/ssi/stm32f2xx_spi.h new file +66 -0

new file mode 100644
index 0000000..75dd6a8
@@ -0,0 +1,74 @@
+/*
+ * STM32F2XX SPI
+ *
+ * Copyright (c) 2014 Alistair Francis <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_STM32F2XX_SPI_H
+#define HW_STM32F2XX_SPI_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/ssi.h"
+
+#define STM_SPI_CR1     0x00
+#define STM_SPI_CR2     0x04
+#define STM_SPI_SR      0x08
+#define STM_SPI_DR      0x0C
+#define STM_SPI_CRCPR   0x10
+#define STM_SPI_RXCRCR  0x14
+#define STM_SPI_TXCRCR  0x18
+#define STM_SPI_I2SCFGR 0x1C
+#define STM_SPI_I2SPR   0x20
+
+#define STM_SPI_CR1_SPE  (1 << 6)
+#define STM_SPI_CR1_MSTR (1 << 2)
+
+#define STM_SPI_SR_BSY   (1 << 7)
+#define STM_SPI_SR_TXE   (1 << 1)
+#define STM_SPI_SR_RXNE   1
+
+#define TYPE_STM32F2XX_SPI "stm32f2xx-spi"
+#define STM32F2XX_SPI(obj) \
+    OBJECT_CHECK(STM32F2XXSpiState, (obj), TYPE_STM32F2XX_SPI)
+
+typedef struct {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion mmio;
+
+    uint32_t spi_cr1;
+    uint32_t spi_cr2;
+    uint32_t spi_sr;
+    uint32_t spi_dr;
+    uint32_t spi_crcpr;
+    uint32_t spi_rxcrcr;
+    uint32_t spi_txcrcr;

include/hw/ssi/stm32f2xx_spi.h line 72

Quoted 6 lines

include/hw/ssi/stm32f2xx_spi.h new file +6 -0

+    uint32_t spi_i2scfgr;
+    uint32_t spi_i2spr;
+
+    qemu_irq irq;
+    SSIBus *ssi;
+} STM32F2XXSpiState;

STM32F2XXSPIState

Regards,
Peter

Quoted 6 lines

include/hw/ssi/stm32f2xx_spi.h new file +2 -1

+
+#endif /* HW_STM32F2XX_SPI_H */
--

2.1.4

Connect the ADC device to the STM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  3 +++
 2 files changed, 25 insertions(+)

hw/arm/stm32f205_soc.c +11 -0

index 63893f3..641ecbb 100644
@@ -31,9 +31,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
     0x40000800, 0x40000C00 };
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
+    0x40012200 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+#define ADC_IRQ 18
 
 static void stm32f205_soc_initfn(Object *obj)
 {

@@ -54,6 +57,12 @@ static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_TIMER);
         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        object_initialize(&s->adc[i], sizeof(s->adc[i]),
+                          TYPE_STM32F2XX_ADC);
+        qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -128,6 +137,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, pic[timer_irq[i]]);
     }
+
+    /* ADC 1 to 3 */

hw/arm/stm32f205_soc.c +1 -0

+    }
 }
 
 static Property stm32f205_soc_properties[] = {

include/hw/arm/stm32f205_soc.h +3 -1

index 0390eff..7d6603b 100644
@@ -28,6 +28,7 @@
 #include "hw/misc/stm32f2xx_syscfg.h"
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
+#include "hw/misc/stm32f2xx_adc.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \

@@ -35,6 +36,7 @@
 
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)

@@ -52,6 +54,7 @@ typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXAdcState adc[STM_NUM_ADCS];
 } STM32F205State;
 
 #endif
--

2.1.4

"devices"

Quoted 2 lines · Alistair Francis

Connect the ADC device to the STM32F205 SoC.

"devices"

Quoted 48 lines

Signed-off-by Alistair Francis <[email protected]>

---

 hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  3 +++
 2 files changed, 25 insertions(+)

hw/arm/stm32f205_soc.c +15 -0

index 63893f3..641ecbb 100644
@@ -31,9 +31,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
     0x40000800, 0x40000C00 };
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
+    0x40012200 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+#define ADC_IRQ 18
 
 static void stm32f205_soc_initfn(Object *obj)
 {

@@ -54,6 +57,12 @@ static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_TIMER);
         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        object_initialize(&s->adc[i], sizeof(s->adc[i]),
+                          TYPE_STM32F2XX_ADC);
+        qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -128,6 +137,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, pic[timer_irq[i]]);
     }
+
+    /* ADC 1 to 3 */
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+        if (err != NULL) {

hw/arm/stm32f205_soc.c static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) · line 151

Quoted 6 lines

hw/arm/stm32f205_soc.c +6 -0

+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, adc_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[ADC_IRQ]);

This looks inconsistent with other devs. Is it a shared IRQ?

Regards,
Peter

Quoted 36 lines

hw/arm/stm32f205_soc.c +1 -0

+    }
 }
 
 static Property stm32f205_soc_properties[] = {

include/hw/arm/stm32f205_soc.h +3 -1

index 0390eff..7d6603b 100644
@@ -28,6 +28,7 @@
 #include "hw/misc/stm32f2xx_syscfg.h"
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
+#include "hw/misc/stm32f2xx_adc.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \

@@ -35,6 +36,7 @@
 
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)

@@ -52,6 +54,7 @@ typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXAdcState adc[STM_NUM_ADCS];
 } STM32F205State;
 
 #endif
--

2.1.4

Quoted 7 lines · Peter Crosthwaite

"devices"

Quoted 2 lines · Alistair Francis

Connect the ADC device to the STM32F205 SoC.

"devices"

Will fix both.

Quoted 48 lines

Quoted 48 lines

Signed-off-by Alistair Francis <[email protected]>

---

 hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  3 +++
 2 files changed, 25 insertions(+)

hw/arm/stm32f205_soc.c +15 -0

index 63893f3..641ecbb 100644
@@ -31,9 +31,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
     0x40000800, 0x40000C00 };
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
+    0x40012200 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+#define ADC_IRQ 18
 
 static void stm32f205_soc_initfn(Object *obj)
 {

@@ -54,6 +57,12 @@ static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_TIMER);
         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        object_initialize(&s->adc[i], sizeof(s->adc[i]),
+                          TYPE_STM32F2XX_ADC);
+        qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -128,6 +137,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, pic[timer_irq[i]]);
     }
+
+    /* ADC 1 to 3 */
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+        if (err != NULL) {

Quoted 8 lines

hw/arm/stm32f205_soc.c static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) · line 151

Quoted 6 lines

hw/arm/stm32f205_soc.c +6 -0

+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, adc_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[ADC_IRQ]);

This looks inconsistent with other devs. Is it a shared IRQ?

Yeah, all the ADCs use the same IRQ. I guess I could have an array like the others with the three values repeated, but it seemed unnecessary. I'm ambivalent though, so happy to change it if you think the consistency is better.

Thanks,

Alistair

Quoted 40 lines

Regards,
Peter

Quoted 36 lines

hw/arm/stm32f205_soc.c +1 -0

+    }
 }
 
 static Property stm32f205_soc_properties[] = {

include/hw/arm/stm32f205_soc.h +3 -1

index 0390eff..7d6603b 100644
@@ -28,6 +28,7 @@
 #include "hw/misc/stm32f2xx_syscfg.h"
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
+#include "hw/misc/stm32f2xx_adc.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \

@@ -35,6 +36,7 @@
 
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)

@@ -52,6 +54,7 @@ typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXAdcState adc[STM_NUM_ADCS];
 } STM32F205State;
 
 #endif
--

2.1.4

Quoted 69 lines · Alistair Francis

Quoted 7 lines · Peter Crosthwaite

"devices"

Quoted 2 lines · Alistair Francis

Connect the ADC device to the STM32F205 SoC.

"devices"

Will fix both.

Quoted 56 lines

Quoted 44 lines

Signed-off-by Alistair Francis <[email protected]>

---

 hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  3 +++
 2 files changed, 25 insertions(+)

hw/arm/stm32f205_soc.c +11 -0

index 63893f3..641ecbb 100644
@@ -31,9 +31,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
     0x40000800, 0x40000C00 };
 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
+static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
+    0x40012200 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
+#define ADC_IRQ 18
 
 static void stm32f205_soc_initfn(Object *obj)
 {

@@ -54,6 +57,12 @@ static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_TIMER);
         qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        object_initialize(&s->adc[i], sizeof(s->adc[i]),
+                          TYPE_STM32F2XX_ADC);
+        qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -128,6 +137,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
         sysbus_connect_irq(busdev, 0, pic[timer_irq[i]]);
     }
+
+    /* ADC 1 to 3 */

hw/arm/stm32f205_soc.c static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) · line 151

Quoted 10 lines

hw/arm/stm32f205_soc.c +10 -0

+    for (i = 0; i < STM_NUM_ADCS; i++) {
+        dev = DEVICE(&(s->adc[i]));
+        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, adc_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[ADC_IRQ]);

This looks inconsistent with other devs. Is it a shared IRQ?

Quoted 5 lines

Yeah, all the ADCs use the same IRQ. I guess I could have an array like the others with the three values repeated, but it seemed unnecessary. I'm ambivalent though, so happy to change it if you think the consistency is better.

So shared IRQs are shaky, as they only work if its an edge sensitive semantic. Is that the case (I found the datasheet confusing on this)?

But as you aren't using the IRQ yet, you could just remove the connection completely.

Regards,
Peter

Quoted 45 lines

Thanks,

Alistair

Quoted 40 lines

Regards,
Peter

Quoted 36 lines

hw/arm/stm32f205_soc.c +1 -0

+    }
 }
 
 static Property stm32f205_soc_properties[] = {

include/hw/arm/stm32f205_soc.h +3 -1

index 0390eff..7d6603b 100644
@@ -28,6 +28,7 @@
 #include "hw/misc/stm32f2xx_syscfg.h"
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
+#include "hw/misc/stm32f2xx_adc.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \

@@ -35,6 +36,7 @@
 
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
+#define STM_NUM_ADCS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)

@@ -52,6 +54,7 @@ typedef struct STM32F205State {
     STM32F2XXSyscfgState syscfg;
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
+    STM32F2XXAdcState adc[STM_NUM_ADCS];
 } STM32F205State;
 
 #endif
--

2.1.4

Connect the SPI device to the STM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

---

 hw/arm/stm32f205_soc.c         | 22 ++++++++++++++++++++++
 include/hw/arm/stm32f205_soc.h |  3 +++
 2 files changed, 25 insertions(+)

hw/arm/stm32f205_soc.c +22 -0

index 641ecbb..cb8884f 100644
@@ -33,10 +33,13 @@ static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
     0x40012200 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
+    0x40003C00 };
 
 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
 #define ADC_IRQ 18
+static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
 
 static void stm32f205_soc_initfn(Object *obj)
 {

@@ -63,6 +66,12 @@ static void stm32f205_soc_initfn(Object *obj)
                           TYPE_STM32F2XX_ADC);
         qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        object_initialize(&s->spi[i], sizeof(s->spi[i]),
+                          TYPE_STM32F2XX_SPI);
+        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

@@ -150,6 +159,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, adc_addr[i]);
         sysbus_connect_irq(busdev, 0, pic[ADC_IRQ]);
     }
+
+    /* SPI 1 and 2 */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, pic[spi_irq[i]]);
+    }
 }
 
 static Property stm32f205_soc_properties[] = {

include/hw/arm/stm32f205_soc.h +3 -1

index 7d6603b..00c2f3d 100644
@@ -29,6 +29,7 @@
 #include "hw/timer/stm32f2xx_timer.h"
 #include "hw/char/stm32f2xx_usart.h"
 #include "hw/misc/stm32f2xx_adc.h"
+#include "hw/ssi/stm32f2xx_spi.h"
 
 #define TYPE_STM32F205_SOC "stm32f205-soc"
 #define STM32F205_SOC(obj) \

@@ -37,6 +38,7 @@
 #define STM_NUM_USARTS 6
 #define STM_NUM_TIMERS 4
 #define STM_NUM_ADCS 3
+#define STM_NUM_SPIS 3
 
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)

@@ -55,6 +57,7 @@ typedef struct STM32F205State {
     STM32F2XXUsartState usart[STM_NUM_USARTS];
     STM32F2XXTimerState timer[STM_NUM_TIMERS];
     STM32F2XXAdcState adc[STM_NUM_ADCS];
+    STM32F2XXSpiState spi[STM_NUM_SPIS];
 } STM32F205State;
 
 #endif
--

2.1.4

Add Alistair Francis as the maintainer for the Netduino 2 and SMM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

---

 MAINTAINERS | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

MAINTAINERS +15 -1

index d7e9ba2..ad9827a 100644
@@ -355,6 +355,21 @@ F: hw/misc/zynq_slcr.c
 F: hw/*/cadence_*
 F: hw/ssi/xilinx_spips.c
 
+STM32F205
+M: Alistair Francis <[email protected]>
+S: Maintained
+F: hw/arm/stm32f205_soc.c
+F: hw/misc/stm32f2xx_syscfg.c
+F: hw/char/stm32f2xx_usart.c
+F: hw/timer/stm32f2xx_timer.c
+F: hw/misc/stm32f2xx_adc.c
+F: hw/ssi/stm32f2xx_spi.c
+
+Netduino 2
+M: Alistair Francis <[email protected]>
+S: Maintained
+F: hw/arm/netduino2.c
+
 CRIS Machines
 -------------
 Axis Dev88
--

2.1.4

Quoted 4 lines · Alistair Francis

Add Alistair Francis as the maintainer for the Netduino 2 and SMM32F205 SoC.

Signed-off-by Alistair Francis <[email protected]>

Reviewed-by Peter Crosthwaite <[email protected]>

Quoted 36 lines

---

 MAINTAINERS | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

MAINTAINERS +15 -1

index d7e9ba2..ad9827a 100644
@@ -355,6 +355,21 @@ F: hw/misc/zynq_slcr.c
 F: hw/*/cadence_*
 F: hw/ssi/xilinx_spips.c
 
+STM32F205
+M: Alistair Francis <[email protected]>
+S: Maintained
+F: hw/arm/stm32f205_soc.c
+F: hw/misc/stm32f2xx_syscfg.c
+F: hw/char/stm32f2xx_usart.c
+F: hw/timer/stm32f2xx_timer.c
+F: hw/misc/stm32f2xx_adc.c
+F: hw/ssi/stm32f2xx_spi.c
+
+Netduino 2
+M: Alistair Francis <[email protected]>
+S: Maintained
+F: hw/arm/netduino2.c
+
 CRIS Machines
 -------------
 Axis Dev88
--

2.1.4