Initial support for Cadence MHDP(HDMI/DP) for i.MX8MQ

PATCH Superseded Sandor Yu 5 participants 25 messages Nov 8, 2022 – Nov 17, 2022

Subsystems (6)

Device tree bindings DRM drivers DRM misc Arm i.MX and Layerscape +2 more subsystems

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Sandor Yu

author

2022-11-08 13:01 UTC #0 lore raw

v3 cover Initial support for Cadence MHDP(HDMI/DP) for i.MX8MQ

The patch set initial support for Cadence MHDP(HDMI/DP) DRM bridge drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for iMX8MQ.

v2->v3:
Address comments for dt-bindings files.
- Correct dts-bindings file names
Rename phy-cadence-hdptx-dp.yaml to cdns,mhdp-imx8mq-dp.yaml Rename phy-cadence-hdptx-hdmi.yaml to cdns,mhdp-imx8mq-hdmi.yaml
- Drop redundant words and descriptions.
- Correct hdmi/dp node name.

v2 is a completely different version compared to v1. Previous v1 can be available here [1].

v1->v2:
- Reuse Cadence mailbox access functions from mhdp8546 instead of rockchip DP.
- Mailbox access functions be convert to marco functions that will be referenced by HDP-TX PHY(HDMI/DP) driver too.
- Plain bridge instead of component driver.
- Standalone Cadence HDP-TX PHY(HDMI/DP) driver.
- Audio driver are removed from the patch set, it will be add in another patch set later.

The patch set compose of DRM bridge drivers and PHY drivers. Both of them need the followed two patches to pass build.
drm: bridge: cadence: convert mailbox functions to macro functions
phy: Add HDMI configuration options

DRM bridges driver patches:
dts-bingings: display: bridge: Add MHDP HDMI bindings for i.MX8MQ
drm: bridge: cadence: Add MHDP DP driver for i.MX8MQ
dts-bindings: display: bridge: Add MHDP DP bindings for i.MX8MQ
drm: bridge: cadence: Add MHDP HDMI driver for i.MX8MQ

PHY driver patches:
dts-bindings: phy: Add Cadence HDP-TX DP PHY bindings
phy: cadence: Add driver for HDP-TX DisplyPort PHY
dts-bindings: phy: Add Cadence HDP-TX HDMI PHY bindings
phy: cadence: Add driver for HDP-TX HDMI PHY

[1] https://patchwork.kernel.org/project/linux-rockchip/cover/[email protected]/

Sandor Yu (10):
drm: bridge: cadence: convert mailbox functions to macro functions
dt-bindings: display: bridge: Add MHDP HDMI for i.MX8MQ
drm: bridge: cadence: Add MHDP DP driver for i.MX8MQ
phy: Add HDMI configuration options
dt-bindings: display: bridge: Add MHDP DP for i.MX8MQ
drm: bridge: cadence: Add MHDP HDMI driver for i.MX8MQ
dt-bindings: phy: Add Cadence HDP-TX DP PHY
phy: cadence: Add driver for HDP-TX DisplyPort PHY
dt-bindings: phy: Add Cadence HDP-TX HDMI PHY
phy: cadence: Add driver for HDP-TX HDMI PHY

 .../display/bridge/cdns,mhdp-imx8mq-dp.yaml   |   59 +
 .../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml |   59 +
 .../bindings/phy/cdns,hdptx-dp-phy.yaml       |   66 +
 .../bindings/phy/cdns,hdptx-hdmi-phy.yaml     |   50 +
 drivers/gpu/drm/bridge/cadence/Kconfig        |   25 +
 drivers/gpu/drm/bridge/cadence/Makefile       |    3 +
 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 1070 +++++++++++++++++
 .../gpu/drm/bridge/cadence/cdns-hdmi-core.c   | 1038 ++++++++++++++++
 .../gpu/drm/bridge/cadence/cdns-mhdp-common.h |  402 +++++++
 .../drm/bridge/cadence/cdns-mhdp8546-core.c   |  197 +--
 .../drm/bridge/cadence/cdns-mhdp8546-core.h   |    1 -
 drivers/phy/cadence/Kconfig                   |   16 +
 drivers/phy/cadence/Makefile                  |    2 +
 drivers/phy/cadence/phy-cadence-hdptx-dp.c    |  774 ++++++++++++
 drivers/phy/cadence/phy-cadence-hdptx-hdmi.c  |  948 +++++++++++++++
 include/drm/bridge/cdns-mhdp-mailbox.h        |  240 ++++
 include/linux/phy/phy-hdmi.h                  |   33 +
 include/linux/phy/phy.h                       |    7 +-
 18 files changed, 4793 insertions(+), 197 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.h
 create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-dp.c
 create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-hdmi.c
 create mode 100644 include/drm/bridge/cdns-mhdp-mailbox.h
 create mode 100644 include/linux/phy/phy-hdmi.h

Signature · 1 line

2.34.1

Sandor Yu

author

2022-11-08 13:01 UTC #1 lore raw

PATCH v3 1/10 drm: bridge: cadence: convert mailbox functions to macro functions

Mailbox access functions could be share to other mhdp driver and HDP-TX HDMI/DP PHY drivers, move those functions to head file include/drm/bridge/cdns-mhdp-mailbox.h and convert them to macro functions.

Signed-off-by Sandor Yu <[email protected]>

---
 .../drm/bridge/cadence/cdns-mhdp8546-core.c   | 197 +-------------
 .../drm/bridge/cadence/cdns-mhdp8546-core.h   |   1 -
 include/drm/bridge/cdns-mhdp-mailbox.h        | 240 ++++++++++++++++++
 3 files changed, 242 insertions(+), 196 deletions(-)
 create mode 100644 include/drm/bridge/cdns-mhdp-mailbox.h

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 ~~-195~~

index 31442a922502..b77b0ddcc9b3 100644
@@ -36,6 +36,7 @@
 #include <linux/slab.h>
 #include <linux/wait.h>
 
+#include <drm/bridge/cdns-mhdp-mailbox.h>
 #include <drm/display/drm_dp_helper.h>
 #include <drm/display/drm_hdcp_helper.h>
 #include <drm/drm_atomic.h>

@@ -55,200 +56,6 @@
 #include "cdns-mhdp8546-hdcp.h"
 #include "cdns-mhdp8546-j721e.h"
 
-static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
-{
-	int ret, empty;
-
-	WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
-	ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
-				 empty, !empty, MAILBOX_RETRY_US,
-				 MAILBOX_TIMEOUT_US);
-	if (ret < 0)
-		return ret;
-
-	return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
-}
-
-static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
-{
-	int ret, full;
-
-	WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
-	ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
-				 full, !full, MAILBOX_RETRY_US,
-				 MAILBOX_TIMEOUT_US);
-	if (ret < 0)
-		return ret;
-
-	writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
-
-	return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_device *mhdp,
-					 u8 module_id, u8 opcode,
-					 u16 req_size)
-{
-	u32 mbox_size, i;
-	u8 header[4];
-	int ret;
-
-	/* read the header of the message */
-	for (i = 0; i < sizeof(header); i++) {
-		ret = cdns_mhdp_mailbox_read(mhdp);
-		if (ret < 0)
-			return ret;
-
-		header[i] = ret;
-	}
-
-	mbox_size = get_unaligned_be16(header + 2);
-
-	if (opcode != header[0] || module_id != header[1] ||
-	    req_size != mbox_size) {
-		/*
-		 * If the message in mailbox is not what we want, we need to
-		 * clear the mailbox by reading its contents.
-		 */
-		for (i = 0; i < mbox_size; i++)
-			if (cdns_mhdp_mailbox_read(mhdp) < 0)
-				break;
-
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_device *mhdp,
-				       u8 *buff, u16 buff_size)
-{
-	u32 i;
-	int ret;
-
-	for (i = 0; i < buff_size; i++) {
-		ret = cdns_mhdp_mailbox_read(mhdp);
-		if (ret < 0)
-			return ret;
-
-		buff[i] = ret;
-	}
-
-	return 0;
-}
-
-static int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id,
-				  u8 opcode, u16 size, u8 *message)
-{
-	u8 header[4];
-	int ret, i;
-
-	header[0] = opcode;
-	header[1] = module_id;
-	put_unaligned_be16(size, header + 2);
-
-	for (i = 0; i < sizeof(header); i++) {
-		ret = cdns_mhdp_mailbox_write(mhdp, header[i]);
-		if (ret)
-			return ret;
-	}
-
-	for (i = 0; i < size; i++) {
-		ret = cdns_mhdp_mailbox_write(mhdp, message[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static
-int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr, u32 *value)
-{
-	u8 msg[4], resp[8];
-	int ret;
-
-	put_unaligned_be32(addr, msg);
-
-	mutex_lock(&mhdp->mbox_mutex);
-
-	ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL,
-				     GENERAL_REGISTER_READ,
-				     sizeof(msg), msg);
-	if (ret)
-		goto out;
-
-	ret = cdns_mhdp_mailbox_recv_header(mhdp, MB_MODULE_ID_GENERAL,
-					    GENERAL_REGISTER_READ,
-					    sizeof(resp));
-	if (ret)
-		goto out;
-
-	ret = cdns_mhdp_mailbox_recv_data(mhdp, resp, sizeof(resp));
-	if (ret)
-		goto out;
-
-	/* Returned address value should be the same as requested */
-	if (memcmp(msg, resp, sizeof(msg))) {
-		ret = -EINVAL;
-		goto out;
-	}
-
-	*value = get_unaligned_be32(resp + 4);
-
-out:
-	mutex_unlock(&mhdp->mbox_mutex);
-	if (ret) {
-		dev_err(mhdp->dev, "Failed to read register\n");
-		*value = 0;
-	}
-
-	return ret;
-}
-
-static
-int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u16 addr, u32 val)
-{
-	u8 msg[6];
-	int ret;
-
-	put_unaligned_be16(addr, msg);
-	put_unaligned_be32(val, msg + 2);
-
-	mutex_lock(&mhdp->mbox_mutex);
-
-	ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
-				     DPTX_WRITE_REGISTER, sizeof(msg), msg);
-
-	mutex_unlock(&mhdp->mbox_mutex);
-
-	return ret;
-}
-
-static
-int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr,
-			    u8 start_bit, u8 bits_no, u32 val)
-{
-	u8 field[8];
-	int ret;
-
-	put_unaligned_be16(addr, field);
-	field[2] = start_bit;
-	field[3] = bits_no;
-	put_unaligned_be32(val, field + 4);
-
-	mutex_lock(&mhdp->mbox_mutex);
-
-	ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
-				     DPTX_WRITE_FIELD, sizeof(field), field);
-
-	mutex_unlock(&mhdp->mbox_mutex);
-
-	return ret;
-}
-
 static
 int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
 			u32 addr, u8 *data, u16 len)

@@ -2058,7 +1865,7 @@ static void cdns_mhdp_atomic_disable(struct drm_bridge *bridge,
 				     struct drm_bridge_state *bridge_state)
 {
 	struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge);
-	u32 resp;
+	u32 resp = 0;
 
 	dev_dbg(mhdp->dev, "%s\n", __func__);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +0 -1

index bedddd510d17..10c878bf0e63 100644
@@ -212,7 +212,6 @@ struct phy;
 #define MB_MODULE_ID_HDCP_TX			0x07
 #define MB_MODULE_ID_HDCP_RX			0x08
 #define MB_MODULE_ID_HDCP_GENERAL		0x09
-#define MB_MODULE_ID_GENERAL			0x0a
 
 /* firmware and opcodes */
 #define FW_NAME					"cadence/mhdp8546.bin"

include/drm/bridge/cdns-mhdp-mailbox.h new file +240 -0

240 lines not on this page · raw message

Signature · 1 line

2.34.1

Sandor Yu

author

2022-11-08 13:01 UTC #2 lore raw

PATCH v3 2/10 dt-bindings: display: bridge: Add MHDP HDMI for i.MX8MQ

In reply to Sandor Yu

Add bindings for i.MX8MQ MHDP HDMI.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +59 -0

new file mode 100644
index 000000000000..8c0afef157aa
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP HDMI bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP TX HDMI interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp-imx8mq-hdmi
+
+  reg:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      A port node pointing to the output port of a display controller.
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mhdp_hdmi: hdmi-bridge@32c00000 {
+        compatible = "cdns,mhdp-imx8mq-hdmi";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        phys = <&hdmi_phy>;
+
+        port {
+            mhdp_in: endpoint {
+                remote-endpoint = <&dcss_out>;
+            };
+        };
+    };

Signature · 1 line

2.34.1

Krzysztof Kozlowski

2022-11-15 13:23 UTC #3 lore raw

Re: [PATCH v3 02/10] dt-bindings: display: bridge: Add MHDP HDMI for i.MX8MQ

Quoted 33 lines · Sandor Yu

Add bindings for i.MX8MQ MHDP HDMI.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +19 -0

new file mode 100644
index 000000000000..8c0afef157aa
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP HDMI bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP TX HDMI interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp-imx8mq-hdmi
+

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml line 29

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +10 -0

+  reg:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.

I don't know what is interrupter, so maybe just "cable plugin/plugout" or "Hotplug cable plugin/plugout"?

Sorry for not bringing this earlier.

Quoted 11 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +11 -0

+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      A port node pointing to the output port of a display controller.
+

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml line 50

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +10 -0

+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mhdp_hdmi: hdmi-bridge@32c00000 {
+        compatible = "cdns,mhdp-imx8mq-hdmi";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

Align with opening <

Best regards,
Krzysztof

Rob Herring

maintainer

2022-11-16 16:25 UTC #4 lore raw

Re: [PATCH v3 02/10] dt-bindings: display: bridge: Add MHDP HDMI for i.MX8MQ

In reply to Sandor Yu

Quoted 43 lines · Sandor Yu

Add bindings for i.MX8MQ MHDP HDMI.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +29 -0

new file mode 100644
index 000000000000..8c0afef157aa
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP HDMI bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP TX HDMI interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp-imx8mq-hdmi
+
+  reg:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml line 39

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +10 -0

+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      A port node pointing to the output port of a display controller.

You also need an output port to an HDMI connector node.

Quoted 24 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +20 -0

+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mhdp_hdmi: hdmi-bridge@32c00000 {
+        compatible = "cdns,mhdp-imx8mq-hdmi";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        phys = <&hdmi_phy>;
+
+        port {
+            mhdp_in: endpoint {
+                remote-endpoint = <&dcss_out>;
+            };
+        };
+    };

Signature · 1 line

2.34.1

Sandor Yu

author

2022-11-08 13:01 UTC #5 lore raw

PATCH v3 3/10 drm: bridge: cadence: Add MHDP DP driver for i.MX8MQ

In reply to Sandor Yu

Add a new DRM DisplayPort bridge driver for Candence MHDP used in i.MX8MQ SOC. MHDP IP could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SOC, the DisplayPort FW was loaded and activated by SOC ROM code. Bootload binary included HDMI FW was required for the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/gpu/drm/bridge/cadence/Kconfig        |   13 +
 drivers/gpu/drm/bridge/cadence/Makefile       |    3 +
 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 1070 +++++++++++++++++
 .../gpu/drm/bridge/cadence/cdns-mhdp-common.h |  402 +++++++
 4 files changed, 1488 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.h

drivers/gpu/drm/bridge/cadence/Kconfig +13 -0

index 1d06182bea71..e79ae1af3765 100644
@@ -25,3 +25,16 @@ config DRM_CDNS_MHDP8546_J721E
 	  initializes the J721E Display Port and sets up the
 	  clock and data muxes.
 endif
+
+config DRM_CDNS_DP
+	tristate "Cadence DP DRM driver"
+	select DRM_KMS_HELPER
+	select DRM_PANEL_BRIDGE
+	select DRM_DISPLAY_DP_HELPER
+	select DRM_DISPLAY_HELPER
+	select DRM_CDNS_AUDIO
+	depends on OF
+	help
+	  Support Cadence MHDP DisplayPort driver.
+	  Cadence MHDP Controller support one or more protocols,
+	  DisplayPort firmware is required for this driver.

drivers/gpu/drm/bridge/cadence/Makefile +3 -0

index 4d2db8df1bc6..269ef500c29d 100644
@@ -2,3 +2,6 @@
 obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
 cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
 cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+
+obj-$(CONFIG_DRM_CDNS_DP) += cdns-dp-core.o
+obj-$(CONFIG_DRM_CDNS_HDMI) += cdns-hdmi-core.o

drivers/gpu/drm/bridge/cadence/cdns-dp-core.c new file +1070 -0

1,070 lines not on this page · raw message

drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.h new file +402 -0

402 lines not on this page · raw message

Signature · 1 line

2.34.1

Sandor Yu

author

2022-11-08 13:02 UTC #6 lore raw

PATCH v3 4/10 phy: Add HDMI configuration options

In reply to Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
 include/linux/phy/phy-hdmi.h | 33 +++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h      |  7 ++++++-
 2 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/phy/phy-hdmi.h

include/linux/phy/phy-hdmi.h new file +33 -0

new file mode 100644
index 000000000000..73a32eb535b0
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+enum hdmi_phy_colorspace {
+	HDMI_PHY_COLORSPACE_RGB,
+	HDMI_PHY_COLORSPACE_YUV422,
+	HDMI_PHY_COLORSPACE_YUV444,
+	HDMI_PHY_COLORSPACE_YUV420,
+	HDMI_PHY_COLORSPACE_RESERVED4,
+	HDMI_PHY_COLORSPACE_RESERVED5,
+	HDMI_PHY_COLORSPACE_RESERVED6,
+};
+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:	Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+	unsigned int pixel_clk_rate;
+	unsigned int bpc;
+	enum hdmi_phy_colorspace color_space;
+};
+
+#endif /* __PHY_HDMI_H_ */

include/linux/phy/phy.h +6 -1

index b1413757fcc3..6f6873ea7270 100644
@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-hdmi.h>
 #include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>

@@ -42,7 +43,8 @@ enum phy_mode {
 	PHY_MODE_MIPI_DPHY,
 	PHY_MODE_SATA,
 	PHY_MODE_LVDS,
-	PHY_MODE_DP
+	PHY_MODE_DP,
+	PHY_MODE_HDMI,
 };
 
 enum phy_media {

@@ -60,11 +62,14 @@ enum phy_media {
  *		the DisplayPort protocol.
  * @lvds:	Configuration set applicable for phys supporting
  *		the LVDS phy mode.
+ * @hdmi:	Configuration set applicable for phys supporting
+ *		the HDMI phy mode.
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
 	struct phy_configure_opts_dp		dp;
 	struct phy_configure_opts_lvds		lvds;
+	struct phy_configure_opts_hdmi		hdmi;
 };
 
 /**

Signature · 1 line

2.34.1

Vinod Koul

maintainer

2022-11-10 07:39 UTC #7 lore raw

Re: [PATCH v3 04/10] phy: Add HDMI configuration options

Quoted 6 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Is there any dpendency b/w phy and hdmi, I dont see anything in cover..

Pls consider splitting the phy series ..

Quoted 21 lines

Signed-off-by Sandor Yu <[email protected]>

---
 include/linux/phy/phy-hdmi.h | 33 +++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h      |  7 ++++++-
 2 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/phy/phy-hdmi.h

include/linux/phy/phy-hdmi.h new file +7 -0

new file mode 100644
index 000000000000..73a32eb535b0
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_

include/linux/phy/phy-hdmi.h line 17

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+
+enum hdmi_phy_colorspace {
+	HDMI_PHY_COLORSPACE_RGB,
+	HDMI_PHY_COLORSPACE_YUV422,
+	HDMI_PHY_COLORSPACE_YUV444,
+	HDMI_PHY_COLORSPACE_YUV420,
+	HDMI_PHY_COLORSPACE_RESERVED4,
+	HDMI_PHY_COLORSPACE_RESERVED5,
+	HDMI_PHY_COLORSPACE_RESERVED6,
+};

kernel-doc style comments here too please

Quoted 55 lines

include/linux/phy/phy-hdmi.h new file +16 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:	Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+	unsigned int pixel_clk_rate;
+	unsigned int bpc;
+	enum hdmi_phy_colorspace color_space;
+};
+
+#endif /* __PHY_HDMI_H_ */

include/linux/phy/phy.h +6 -1

index b1413757fcc3..6f6873ea7270 100644
@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-hdmi.h>
 #include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>

@@ -42,7 +43,8 @@ enum phy_mode {
 	PHY_MODE_MIPI_DPHY,
 	PHY_MODE_SATA,
 	PHY_MODE_LVDS,
-	PHY_MODE_DP
+	PHY_MODE_DP,
+	PHY_MODE_HDMI,
 };
 
 enum phy_media {

@@ -60,11 +62,14 @@ enum phy_media {
  *		the DisplayPort protocol.
  * @lvds:	Configuration set applicable for phys supporting
  *		the LVDS phy mode.
+ * @hdmi:	Configuration set applicable for phys supporting
+ *		the HDMI phy mode.
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
 	struct phy_configure_opts_dp		dp;
 	struct phy_configure_opts_lvds		lvds;
+	struct phy_configure_opts_hdmi		hdmi;
 };
 
 /**

Signature · 1 line

2.34.1

Signature · 1 line

~Vinod

Sandor Yu

author

2022-11-10 08:09 UTC #8 lore raw

RE: [EXT] Re: [PATCH v3 04/10] phy: Add HDMI configuration options

Thanks your comments,

Quoted 24 lines

-----Original Message-----
From: Vinod Koul <[email protected]>
Sent: 2022年11月10日 15:39
To: Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v3 04/10] phy: Add HDMI configuration options
Caution: EXT Email
Quoted 3 lines · Sandor Yu
Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

Quoted 7 lines

Quoted 3 lines
The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.
Is there any dpendency b/w phy and hdmi, I dont see anything in cover..
Pls consider splitting the phy series ..

Both HDMI/DP and PHY patch set depend on each other to pass build. HDMI driver depend on phy-hdmi.h and
PHY driver depend on cdns-mhdp-mailbox.h to pass build. The followed description had in cover patch:
"The patch set compose of DRM bridge drivers and PHY drivers. Both of them need the followed two patches to pass build.
drm: bridge: cadence: convert mailbox functions to macro functions
phy: Add HDMI configuration options"

Quoted 27 lines

Quoted 5 lines
Signed-off-by Sandor Yu <[email protected]>
---
 include/linux/phy/phy-hdmi.h | 33
+++++++++++++++++++++++++++++++++
Quoted 21 lines
 include/linux/phy/phy.h      |  7 ++++++-
 2 files changed, 39 insertions(+), 1 deletion(-)  create mode 100644
include/linux/phy/phy-hdmi.h
(quoted diff) +0 -0
b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..73a32eb535b0
include/linux/phy/phy-hdmi.h new file +11 -0
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+enum hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,
+     HDMI_PHY_COLORSPACE_YUV422,

Quoted 8 lines

include/linux/phy/phy-hdmi.h line 17
Quoted 6 lines
include/linux/phy/phy-hdmi.h new file +6 -0
+     HDMI_PHY_COLORSPACE_YUV444,
+     HDMI_PHY_COLORSPACE_YUV420,
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6,
+};
kernel-doc style comments here too please

OK, I will add it.

Quoted 52 lines

include/linux/phy/phy-hdmi.h new file +15 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

include/linux/phy/phy.h index renamed from include/linux/phy/phy.h +0 -0

b1413757fcc3..6f6873ea7270 100644

include/linux/phy/phy.h +6 -1

@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-hdmi.h>
 #include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>

@@ -42,7 +43,8 @@ enum phy_mode {
      PHY_MODE_MIPI_DPHY,
      PHY_MODE_SATA,
      PHY_MODE_LVDS,
-     PHY_MODE_DP
+     PHY_MODE_DP,
+     PHY_MODE_HDMI,
 };
 
 enum phy_media {

@@ -60,11 +62,14 @@ enum phy_media {
  *           the DisplayPort protocol.
  * @lvds:    Configuration set applicable for phys supporting
  *           the LVDS phy mode.
+ * @hdmi:    Configuration set applicable for phys supporting
+ *           the HDMI phy mode.
  */
 union phy_configure_opts {
      struct phy_configure_opts_mipi_dphy     mipi_dphy;
      struct phy_configure_opts_dp            dp;
      struct phy_configure_opts_lvds          lvds;
+     struct phy_configure_opts_hdmi          hdmi;
 };

Quoted 6 lines

Quoted 3 lines
include/linux/phy/phy.h +0 -1
 /**
--
2.34.1
--
~Vinod

B.R
Sandor

Sandor Yu

author

2022-11-08 13:02 UTC #9 lore raw

PATCH v3 5/10 dt-bindings: display: bridge: Add MHDP DP for i.MX8MQ

In reply to Sandor Yu

Add bindings for i.MX8MQ MHDP DisplayPort.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-dp.yaml   | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +59 -0

new file mode 100644
index 000000000000..c4d5362db2b5
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP Displayport TX interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp-imx8mq-dp
+
+  reg:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      A port node pointing to the output port of a display controller.
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mhdp_dp: dp-bridge@32c00000 {
+        compatible = "cdns,mhdp-imx8mq-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        phys = <&dp_phy>;
+
+        port {
+            mhdp_in: endpoint {
+                remote-endpoint = <&dcss_out>;
+            };
+        };
+    };

Signature · 1 line

2.34.1

Rob Herring

maintainer

2022-11-16 16:27 UTC #10 lore raw

Re: [PATCH v3 05/10] dt-bindings: display: bridge: Add MHDP DP for i.MX8MQ

Quoted 43 lines · Sandor Yu

Add bindings for i.MX8MQ MHDP DisplayPort.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-dp.yaml   | 59 +++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +29 -0

new file mode 100644
index 000000000000..c4d5362db2b5
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP Displayport TX interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp-imx8mq-dp
+
+  reg:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml line 39

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +10 -0

+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      A port node pointing to the output port of a display controller.

Similarly, you need an output port to DP (or USB-C) connector.

Quoted 24 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +20 -0

+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mhdp_dp: dp-bridge@32c00000 {
+        compatible = "cdns,mhdp-imx8mq-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        phys = <&dp_phy>;
+
+        port {
+            mhdp_in: endpoint {
+                remote-endpoint = <&dcss_out>;
+            };
+        };
+    };

Signature · 1 line

2.34.1

Sandor Yu

author

2022-11-17 11:41 UTC #11 lore raw

RE: [EXT] Re: [PATCH v3 05/10] dt-bindings: display: bridge: Add MHDP DP for i.MX8MQ

Hi Rob,

Thanks your comments,

Quoted 114 lines

-----Original Message-----
From: Rob Herring <[email protected]>
Sent: 2022年11月17日 0:27
To: Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v3 05/10] dt-bindings: display: bridge: Add MHDP DP for i.MX8MQ
Caution: EXT Email
Quoted 5 lines · Sandor Yu
Add bindings for i.MX8MQ MHDP DisplayPort.
Signed-off-by Sandor Yu <[email protected]>
---
 .../display/bridge/cdns,mhdp-imx8mq-dp.yaml   | 59
+++++++++++++++++++
Quoted 3 lines
 1 file changed, 59 insertions(+)
 create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.y
Quoted 4 lines
aml
diff --git
a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp
Quoted 2 lines
.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp
Quoted 5 lines
.yaml
new file mode 100644
index 000000000000..c4d5362db2b5
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8m
Review line 4
Quoted 7 lines
+++ q-dp.yaml
(quoted diff) +4 -0
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
+---
+$id:
+https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
+cetree.org%2Fschemas%2Fdisplay%2Fbridge%2Fcdns%2Cmhdp-imx8mq-dp. yaml%
Quoted 1 line
+23&data=05%7C01%7CSandor.yu%40nxp.com%7Cfadde1cdcefe4c1e5f b108dac
Quoted 1 line
+7ef642f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63804212 82331650
Quoted 1 line
+96%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luM zIiLCJBTi
Quoted 1 line
+I6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=EjvtnWhP MVKgzlKC7f
Quoted 4 lines
+8GC3EtidDKgkU5vMSuRaz3Bqg%3D&reserved=0
+$schema:
+https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
+cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7CSa ndor.yu
Quoted 1 line
+%40nxp.com%7Cfadde1cdcefe4c1e5fb108dac7ef642f%7C686ea1d3bc2b4c 6fa92cd
Quoted 1 line
+99c5c301635%7C0%7C0%7C638042128233165096%7CUnknown%7CTWFp bGZsb3d8eyJW
Quoted 1 line
+IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 C3000
Quoted 1 line
+%7C%7C%7C&sdata=l0tVYsOuT6SNbREcg65s0FYjVVrpUM%2F5VztRvxE sgA8%3D&
Quoted 29 lines
Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +29 -0
+amp;reserved=0
+
+title: Cadence MHDP Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP Displayport TX interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp-imx8mq-dp
+
+  reg:
+    maxItems: 1
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.
+
+  interrupt-names:
+    items:
+      - const: plug_in

Quoted 9 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml line 39
Quoted 6 lines
Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +6 -0
+      - const: plug_out
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      A port node pointing to the output port of a display controller.
Similarly, you need an output port to DP (or USB-C) connector.

Both the HDMI and DP driver don't need the functions of display-connector, do we still need an output port to connector here?

B.R
Sandor

Quoted 24 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +20 -1

+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mhdp_dp: dp-bridge@32c00000 {
+        compatible = "cdns,mhdp-imx8mq-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        phys = <&dp_phy>;
+
+        port {
+            mhdp_in: endpoint {
+                remote-endpoint = <&dcss_out>;
+            };
+        };
+    };
--

2.34.1

Sandor Yu

author

2022-11-08 13:02 UTC #12 lore raw

PATCH v3 6/10 drm: bridge: cadence: Add MHDP HDMI driver for i.MX8MQ

In reply to Sandor Yu

Add a new DRM HDMI bridge driver for Candence MHDP used in i.MX8MQ SOC. MHDP IP could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SOC, the HDMI FW was loaded and activated by SOC ROM code. Bootload binary included HDMI FW was required for the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/gpu/drm/bridge/cadence/Kconfig        |   12 +
 .../gpu/drm/bridge/cadence/cdns-hdmi-core.c   | 1038 +++++++++++++++++
 2 files changed, 1050 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

drivers/gpu/drm/bridge/cadence/Kconfig +12 -0

index e79ae1af3765..377452d09992 100644
@@ -26,6 +26,18 @@ config DRM_CDNS_MHDP8546_J721E
 	  clock and data muxes.
 endif
 
+config DRM_CDNS_HDMI
+	tristate "Cadence HDMI DRM driver"
+	select DRM_KMS_HELPER
+	select DRM_PANEL_BRIDGE
+	select DRM_DISPLAY_HELPER
+	select DRM_CDNS_AUDIO
+	depends on OF
+	help
+	  Support Cadence MHDP HDMI driver.
+	  Cadence MHDP Controller support one or more protocols,
+	  HDMI firmware is required for this driver.
+
 config DRM_CDNS_DP
 	tristate "Cadence DP DRM driver"
 	select DRM_KMS_HELPER

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1038 -0

1,038 lines not on this page · raw message

Signature · 1 line

2.34.1

Sandor Yu

author

2022-11-08 13:02 UTC #13 lore raw

PATCH v3 7/10 dt-bindings: phy: Add Cadence HDP-TX DP PHY

In reply to Sandor Yu

Add bindings for Cadence HDP-TX DisplayPort PHY.

Signed-off-by Sandor Yu <[email protected]>

---
 .../bindings/phy/cdns,hdptx-dp-phy.yaml       | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml

Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml new file +66 -0

new file mode 100644
index 000000000000..8f9b8ba7d1c6
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,hdptx-dp-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX(HDMI/DisplayPort) PHY for DisplayPort protocol
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - cdns,hdptx-dp-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      description:
+        PHY reference clock.
+
+  clock-names:
+    items:
+      - const: refclk
+
+  "#phy-cells":
+    const: 0
+
+  cdns,num-lanes:
+    description:
+      Number of lanes.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [1, 2, 3, 4]
+    default: 4
+
+  cdns,max-bit-rate:
+    description:
+      Maximum DisplayPort link bit rate to use, in Mbps
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [2160, 2430, 2700, 3240, 4320, 5400]
+    default: 5400
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/phy/phy.h>
+    dp_phy: phy@32c00000 {
+        compatible = "cdns,hdptx-dp-phy";
+        reg = <0x32c00000 0x100000>;
+        #phy-cells = <0>;
+        clocks = <&hdmi_phy_27m>;
+        clock-names = "refclk";
+        cdns,num-lanes = <4>;
+        cdns,max-bit-rate = <5400>;
+    };

Signature · 1 line

2.34.1

Krzysztof Kozlowski

2022-11-15 13:27 UTC #14 lore raw

Re: [PATCH v3 07/10] dt-bindings: phy: Add Cadence HDP-TX DP PHY

Quoted 26 lines · Sandor Yu

Add bindings for Cadence HDP-TX DisplayPort PHY.

Signed-off-by Sandor Yu <[email protected]>

---
 .../bindings/phy/cdns,hdptx-dp-phy.yaml       | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml

Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml new file +12 -0

new file mode 100644
index 000000000000..8f9b8ba7d1c6
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,hdptx-dp-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX(HDMI/DisplayPort) PHY for DisplayPort protocol
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+properties:

Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml line 22

Quoted 10 lines

Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml new file +10 -0
+  compatible:
+    enum:
+      - cdns,hdptx-dp-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      description:

Missing -

Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml line 23

Quoted 1 line

Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml new file +1 -0
+        PHY reference clock.

Join with previous line.

- description: foo bar

Best regards,
Krzysztof

Sandor Yu

author

2022-11-08 13:02 UTC #15 lore raw

PATCH v3 8/10 phy: cadence: Add driver for HDP-TX DisplyPort PHY

In reply to Sandor Yu

Add Cadence HDP-TX DisplayPort PHY driver.

Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort PHY mode is configurated in the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/phy/cadence/Kconfig                |   8 +
 drivers/phy/cadence/Makefile               |   1 +
 drivers/phy/cadence/phy-cadence-hdptx-dp.c | 774 +++++++++++++++++++++
 3 files changed, 783 insertions(+)
 create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-dp.c

drivers/phy/cadence/Kconfig +8 -0

index 1adde2d99ae7..1e1914d3afdc 100644
@@ -46,3 +46,11 @@ config PHY_CADENCE_SALVO
 	  Enable this to support the Cadence SALVO PHY driver,
 	  this PHY is a legacy PHY, and only are used for USB3
 	  and USB2.
+
+config PHY_CADENCE_HDPTX_DP
+	tristate "Cadence HDPTX DP PHY Driver"
+	depends on OF && HAS_IOMEM
+	depends on COMMON_CLK
+	select GENERIC_PHY
+	help
+	  Enable this to support the Cadence HDPTX DP PHY driver

drivers/phy/cadence/Makefile +1 -0

index e17f035ddece..fbdb0bc5ff11 100644
@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_CADENCE_DPHY)	+= cdns-dphy.o
 obj-$(CONFIG_PHY_CADENCE_DPHY_RX)	+= cdns-dphy-rx.o
 obj-$(CONFIG_PHY_CADENCE_SIERRA)	+= phy-cadence-sierra.o
 obj-$(CONFIG_PHY_CADENCE_SALVO)	+= phy-cadence-salvo.o
+obj-$(CONFIG_PHY_CADENCE_HDPTX_DP)	+= phy-cadence-hdptx-dp.o

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +774 -0

774 lines not on this page · raw message

Signature · 1 line

2.34.1

Vinod Koul

maintainer

2022-11-10 07:40 UTC #16 lore raw

Re: [PATCH v3 08/10] phy: cadence: Add driver for HDP-TX DisplyPort PHY

Quoted 19 lines · Sandor Yu

Add Cadence HDP-TX DisplayPort PHY driver.
Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort PHY mode is configurated in the driver.
Signed-off-by Sandor Yu <[email protected]>
---
 drivers/phy/cadence/Kconfig                |   8 +
 drivers/phy/cadence/Makefile               |   1 +
 drivers/phy/cadence/phy-cadence-hdptx-dp.c | 774 +++++++++++++++++++++
 3 files changed, 783 insertions(+)
 create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-dp.c
drivers/phy/cadence/Kconfig +0 -0
index 1adde2d99ae7..1e1914d3afdc 100644

drivers/phy/cadence/Kconfig config PHY_CADENCE_SALVO · line 50

Quoted 5 lines

drivers/phy/cadence/Kconfig +2 -0

@@ -46,3 +46,11 @@ config PHY_CADENCE_SALVO
 	  Enable this to support the Cadence SALVO PHY driver,
 	  this PHY is a legacy PHY, and only are used for USB3
 	  and USB2.
+
+config PHY_CADENCE_HDPTX_DP

alphabetically sorted please

Quoted 11 lines

drivers/phy/cadence/Kconfig +6 -0

+	tristate "Cadence HDPTX DP PHY Driver"
+	depends on OF && HAS_IOMEM
+	depends on COMMON_CLK
+	select GENERIC_PHY
+	help
+	  Enable this to support the Cadence HDPTX DP PHY driver

drivers/phy/cadence/Makefile +0 -0

index e17f035ddece..fbdb0bc5ff11 100644

drivers/phy/cadence/Makefile obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o · line 7

Quoted 4 lines

drivers/phy/cadence/Makefile +1 -0

@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_CADENCE_DPHY)	+= cdns-dphy.o
 obj-$(CONFIG_PHY_CADENCE_DPHY_RX)	+= cdns-dphy-rx.o
 obj-$(CONFIG_PHY_CADENCE_SIERRA)	+= phy-cadence-sierra.o
 obj-$(CONFIG_PHY_CADENCE_SALVO)	+= phy-cadence-salvo.o
+obj-$(CONFIG_PHY_CADENCE_HDPTX_DP)	+= phy-cadence-hdptx-dp.o

here too

Quoted 148 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +142 -0

new file mode 100644
index 000000000000..079d43772d1d
@@ -0,0 +1,774 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence HDP-TX Display Port Interface (DP) PHY driver
+ *
+ * Copyright (C) 2022 NXP Semiconductor, Inc.
+ */
+#include <asm/unaligned.h>
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include <drm/bridge/cdns-mhdp-mailbox.h>
+
+#define ADDR_PHY_AFE	0x80000
+
+/* PHY registers */
+#define CMN_SSM_BIAS_TMR                0x0022
+#define CMN_PLLSM0_PLLEN_TMR            0x0029
+#define CMN_PLLSM0_PLLPRE_TMR           0x002A
+#define CMN_PLLSM0_PLLVREF_TMR          0x002B
+#define CMN_PLLSM0_PLLLOCK_TMR          0x002C
+#define CMN_PLLSM0_USER_DEF_CTRL        0x002F
+#define CMN_PSM_CLK_CTRL                0x0061
+#define CMN_CDIAG_REFCLK_CTRL           0x0062
+#define CMN_PLL0_VCOCAL_START           0x0081
+#define CMN_PLL0_VCOCAL_INIT_TMR        0x0084
+#define CMN_PLL0_VCOCAL_ITER_TMR        0x0085
+#define CMN_PLL0_INTDIV                 0x0094
+#define CMN_PLL0_FRACDIV                0x0095
+#define CMN_PLL0_HIGH_THR               0x0096
+#define CMN_PLL0_DSM_DIAG               0x0097
+#define CMN_PLL0_SS_CTRL1               0x0098
+#define CMN_PLL0_SS_CTRL2               0x0099
+#define CMN_ICAL_INIT_TMR               0x00C4
+#define CMN_ICAL_ITER_TMR               0x00C5
+#define CMN_RXCAL_INIT_TMR              0x00D4
+#define CMN_RXCAL_ITER_TMR              0x00D5
+#define CMN_TXPUCAL_CTRL                0x00E0
+#define CMN_TXPUCAL_INIT_TMR            0x00E4
+#define CMN_TXPUCAL_ITER_TMR            0x00E5
+#define CMN_TXPDCAL_CTRL                0x00F0
+#define CMN_TXPDCAL_INIT_TMR            0x00F4
+#define CMN_TXPDCAL_ITER_TMR            0x00F5
+#define CMN_ICAL_ADJ_INIT_TMR           0x0102
+#define CMN_ICAL_ADJ_ITER_TMR           0x0103
+#define CMN_RX_ADJ_INIT_TMR             0x0106
+#define CMN_RX_ADJ_ITER_TMR             0x0107
+#define CMN_TXPU_ADJ_CTRL               0x0108
+#define CMN_TXPU_ADJ_INIT_TMR           0x010A
+#define CMN_TXPU_ADJ_ITER_TMR           0x010B
+#define CMN_TXPD_ADJ_CTRL               0x010c
+#define CMN_TXPD_ADJ_INIT_TMR           0x010E
+#define CMN_TXPD_ADJ_ITER_TMR           0x010F
+#define CMN_DIAG_PLL0_FBH_OVRD          0x01C0
+#define CMN_DIAG_PLL0_FBL_OVRD          0x01C1
+#define CMN_DIAG_PLL0_OVRD              0x01C2
+#define CMN_DIAG_PLL0_TEST_MODE         0x01C4
+#define CMN_DIAG_PLL0_V2I_TUNE          0x01C5
+#define CMN_DIAG_PLL0_CP_TUNE           0x01C6
+#define CMN_DIAG_PLL0_LF_PROG           0x01C7
+#define CMN_DIAG_PLL0_PTATIS_TUNE1      0x01C8
+#define CMN_DIAG_PLL0_PTATIS_TUNE2      0x01C9
+#define CMN_DIAG_PLL0_INCLK_CTRL        0x01CA
+#define CMN_DIAG_PLL0_PXL_DIVH          0x01CB
+#define CMN_DIAG_PLL0_PXL_DIVL          0x01CC
+#define CMN_DIAG_HSCLK_SEL              0x01E0
+#define CMN_DIAG_PER_CAL_ADJ            0x01EC
+#define CMN_DIAG_CAL_CTRL               0x01ED
+#define CMN_DIAG_ACYA                   0x01FF
+#define XCVR_PSM_RCTRL                  0x4001
+#define XCVR_PSM_CAL_TMR                0x4002
+#define XCVR_PSM_A0IN_TMR               0x4003
+#define TX_TXCC_CAL_SCLR_MULT_0         0x4047
+#define TX_TXCC_CPOST_MULT_00_0         0x404C
+#define TX_TXCC_MGNFS_MULT_000_0        0x4050
+#define XCVR_DIAG_PLLDRC_CTRL           0x40E0
+#define XCVR_DIAG_PLLDRC_CTRL           0x40E0
+#define XCVR_DIAG_HSCLK_SEL             0x40E1
+#define XCVR_DIAG_BIDI_CTRL             0x40E8
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR   0x40F2
+#define XCVR_DIAG_LANE_FCM_EN_MGN       0x40F2
+#define TX_PSC_A0                       0x4100
+#define TX_PSC_A1                       0x4101
+#define TX_PSC_A2                       0x4102
+#define TX_PSC_A3                       0x4103
+#define TX_RCVDET_CTRL                  0x4120
+#define TX_RCVDET_EN_TMR                0x4122
+#define TX_RCVDET_EN_TMR                0x4122
+#define TX_RCVDET_ST_TMR                0x4123
+#define TX_RCVDET_ST_TMR                0x4123
+#define TX_BIST_CTRL                    0x4140
+#define TX_BIST_UDDWR                   0x4141
+#define TX_DIAG_TX_CTRL                 0x41E0
+#define TX_DIAG_TX_DRV                  0x41E1
+#define TX_DIAG_BGREF_PREDRV_DELAY      0x41E7
+#define TX_DIAG_BGREF_PREDRV_DELAY      0x41E7
+#define XCVR_PSM_RCTRL_1                0x4201
+#define TX_TXCC_CAL_SCLR_MULT_1         0x4247
+#define TX_TXCC_CPOST_MULT_00_1         0x424C
+#define TX_TXCC_MGNFS_MULT_000_1        0x4250
+#define XCVR_DIAG_PLLDRC_CTRL_1         0x42E0
+#define XCVR_DIAG_HSCLK_SEL_1           0x42E1
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_1 0x42F2
+#define TX_RCVDET_EN_TMR_1              0x4322
+#define TX_RCVDET_ST_TMR_1              0x4323
+#define TX_DIAG_ACYA_0                  0x41FF
+#define TX_DIAG_ACYA_1                  0x43FF
+#define TX_DIAG_ACYA_2                  0x45FF
+#define TX_DIAG_ACYA_3                  0x47FF
+#define TX_ANA_CTRL_REG_1               0x5020
+#define TX_ANA_CTRL_REG_2               0x5021
+#define TXDA_COEFF_CALC                 0x5022
+#define TX_DIG_CTRL_REG_1               0x5023
+#define TX_DIG_CTRL_REG_2               0x5024
+#define TXDA_CYA_AUXDA_CYA              0x5025
+#define TX_ANA_CTRL_REG_3               0x5026
+#define TX_ANA_CTRL_REG_4               0x5027
+#define TX_ANA_CTRL_REG_5               0x5029
+#define RX_PSC_A0                       0x8000
+#define RX_PSC_CAL                      0x8006
+#define PMA_LANE_CFG                    0xC000
+#define PIPE_CMN_CTRL1                  0xC001
+#define PIPE_CMN_CTRL2                  0xC002
+#define PIPE_COM_LOCK_CFG1              0xC003
+#define PIPE_COM_LOCK_CFG2              0xC004
+#define PIPE_RCV_DET_INH                0xC005
+#define PHY_HDP_MODE_CTRL               0xC008
+#define PHY_HDP_CLK_CTL                 0xC009
+#define STS                             0xC00F
+#define PHY_ISO_CMN_CTRL                0xC010
+#define PHY_ISO_CMN_CTRL                0xC010
+#define PHY_HDP_TX_CTL_L0               0xC408
+#define PHY_DP_TX_CTL                   0xC408
+#define PHY_HDP_TX_CTL_L1               0xC448
+#define PHY_HDP_TX_CTL_L2               0xC488
+#define PHY_HDP_TX_CTL_L3               0xC4C8
+#define PHY_PMA_CMN_CTRL1               0xC800
+#define PMA_CMN_CTRL1                   0xC800
+#define PHY_PMA_ISO_CMN_CTRL            0xC810

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 152

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+#define PHY_PMA_ISO_PLL_CTRL1           0xC812
+#define PHY_PMA_ISOLATION_CTRL          0xC81F
+#define PHY_ISOLATION_CTRL              0xC81F
+#define PHY_PMA_ISO_XCVR_CTRL           0xCC11
+#define PHY_PMA_ISO_LINK_MODE           0xCC12
+#define PHY_PMA_ISO_PWRST_CTRL          0xCC13
+#define PHY_PMA_ISO_TX_DATA_LO          0xCC14
+#define PHY_PMA_ISO_TX_DATA_HI          0xCC15
+#define PHY_PMA_ISO_RX_DATA_LO          0xCC16
+#define PHY_PMA_ISO_RX_DATA_HI          0xCC17

do you use all these?

Quoted 624 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +622 -0

+
+#define MAX_NUM_LANES		4
+#define DEFAULT_MAX_BIT_RATE	5400 /* in Mbps */
+
+#define REF_CLK_27MHZ		27000000
+
+enum dp_link_rate {
+	RATE_1_6 = 162000,
+	RATE_2_1 = 216000,
+	RATE_2_4 = 243000,
+	RATE_2_7 = 270000,
+	RATE_3_2 = 324000,
+	RATE_4_3 = 432000,
+	RATE_5_4 = 540000,
+	RATE_8_1 = 810000,
+};
+
+struct phy_pll_reg {
+	u16 val[7];
+	u32 addr;
+};
+
+static const struct phy_pll_reg phy_pll_27m_cfg[] = {
+	/*  1.62    2.16    2.43    2.7     3.24    4.32    5.4      register address */
+	{{ 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E }, CMN_PLL0_VCOCAL_INIT_TMR },
+	{{ 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B }, CMN_PLL0_VCOCAL_ITER_TMR },
+	{{ 0x30B9, 0x3087, 0x3096, 0x30B4, 0x30B9, 0x3087, 0x30B4 }, CMN_PLL0_VCOCAL_START },
+	{{ 0x0077, 0x009F, 0x00B3, 0x00C7, 0x0077, 0x009F, 0x00C7 }, CMN_PLL0_INTDIV },
+	{{ 0xF9DA, 0xF7CD, 0xF6C7, 0xF5C1, 0xF9DA, 0xF7CD, 0xF5C1 }, CMN_PLL0_FRACDIV },
+	{{ 0x001E, 0x0028, 0x002D, 0x0032, 0x001E, 0x0028, 0x0032 }, CMN_PLL0_HIGH_THR },
+	{{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_PLL0_DSM_DIAG },
+	{{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL },
+	{{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_OVRD },
+	{{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBH_OVRD },
+	{{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBL_OVRD },
+	{{ 0x0006, 0x0007, 0x0007, 0x0007, 0x0006, 0x0007, 0x0007 }, CMN_DIAG_PLL0_V2I_TUNE },
+	{{ 0x0043, 0x0043, 0x0043, 0x0042, 0x0043, 0x0043, 0x0042 }, CMN_DIAG_PLL0_CP_TUNE },
+	{{ 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 }, CMN_DIAG_PLL0_LF_PROG },
+	{{ 0x0100, 0x0001, 0x0001, 0x0001, 0x0100, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE1 },
+	{{ 0x0007, 0x0001, 0x0001, 0x0001, 0x0007, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE2 },
+	{{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_DIAG_PLL0_TEST_MODE},
+	{{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 }, CMN_PSM_CLK_CTRL }
+};
+
+struct cdns_hdptx_dp_phy {
+	void __iomem *regs;	/* DPTX registers base */
+	struct device *dev;
+	struct phy *phy;
+	struct mutex mbox_mutex; /* mutex to protect mailbox */
+	struct clk *ref_clk;
+	u32 ref_clk_rate;
+	u32 num_lanes;
+	u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
+	u32 link_rate;
+	bool power_up;
+};
+
+static int cdns_phy_reg_write(struct cdns_hdptx_dp_phy *cdns_phy, u32 addr, u32 val)
+{
+	return cdns_mhdp_reg_write(cdns_phy, ADDR_PHY_AFE + (addr << 2), val);
+}
+
+static u32 cdns_phy_reg_read(struct cdns_hdptx_dp_phy *cdns_phy, u32 addr)
+{
+	u32 reg32;
+
+	cdns_mhdp_reg_read(cdns_phy, ADDR_PHY_AFE + (addr << 2), &reg32);
+	return reg32;
+}
+
+static int link_rate_index(u32 rate)
+{
+	switch (rate) {
+	case RATE_1_6:
+		return 0;
+	case RATE_2_1:
+		return 1;
+	case RATE_2_4:
+		return 2;
+	case RATE_2_7:
+		return 3;
+	case RATE_3_2:
+		return 4;
+	case RATE_4_3:
+		return 5;
+	case RATE_5_4:
+		return 6;
+	default:
+		return -1;
+	}
+}
+
+static int hdptx_dp_ref_clk(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	struct device *dev = cdns_phy->dev;
+	u32 ref_clk_rate;
+	int ret;
+
+	cdns_phy->ref_clk = devm_clk_get(dev, "refclk");
+	if (IS_ERR(cdns_phy->ref_clk)) {
+		dev_err(dev, "phy ref clock not found\n");
+		return PTR_ERR(cdns_phy->ref_clk);
+	}
+
+	ret = clk_prepare_enable(cdns_phy->ref_clk);
+	if (ret) {
+		dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
+		return ret;
+	}
+
+	ref_clk_rate = clk_get_rate(cdns_phy->ref_clk);
+	if (!ref_clk_rate) {
+		dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
+		goto err_ref_clk;
+	}
+
+	if (ref_clk_rate == REF_CLK_27MHZ)
+		cdns_phy->ref_clk_rate = ref_clk_rate;
+	else {
+		dev_err(cdns_phy->dev, "Not support Ref Clock Rate(%dHz)\n", ref_clk_rate);
+		goto err_ref_clk;
+	}
+
+	return 0;
+
+err_ref_clk:
+	clk_disable_unprepare(cdns_phy->ref_clk);
+	return -EINVAL;
+}
+
+static void hdptx_dp_aux_cfg(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	/* Power up Aux */
+	cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 1);
+
+	cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_1, 0x3);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, 36);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA018);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030C);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0000);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x1001);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA098);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA198);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f);
+}
+
+/* PMA common configuration for 27MHz */
+static void hdptx_dp_phy_pma_cmn_cfg_27mhz(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 num_lanes = cdns_phy->num_lanes;
+	u16 val;
+	int k;
+
+	val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+	val &= 0xFFF7;
+	val |= 0x0008;
+	cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
+
+	/* Startup state machine registers */
+	cdns_phy_reg_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0087);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLEN_TMR, 0x001B);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0036);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLVREF_TMR, 0x001B);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x006C);
+
+	/* Current calibration registers */
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_INIT_TMR, 0x0044);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_ITER_TMR, 0x0006);
+
+	/* Resistor calibration registers */
+	cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_ITER_TMR, 0x0006);
+
+	for (k = 0; k < num_lanes; k = k + 1) {
+		/* Power state machine registers */
+		cdns_phy_reg_write(cdns_phy, XCVR_PSM_CAL_TMR  | (k << 9), 0x016D);
+		cdns_phy_reg_write(cdns_phy, XCVR_PSM_A0IN_TMR | (k << 9), 0x016D);
+		/* Transceiver control and diagnostic registers */
+		cdns_phy_reg_write(cdns_phy, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x00A2);
+		cdns_phy_reg_write(cdns_phy, TX_DIAG_BGREF_PREDRV_DELAY    | (k << 9), 0x0097);
+		/* Transmitter receiver detect registers */
+		cdns_phy_reg_write(cdns_phy, TX_RCVDET_EN_TMR | (k << 9), 0x0A8C);
+		cdns_phy_reg_write(cdns_phy, TX_RCVDET_ST_TMR | (k << 9), 0x0036);
+	}
+
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
+}
+
+static void hdptx_dp_phy_pma_cmn_pll0_27mhz(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 num_lanes = cdns_phy->num_lanes;
+	u32 link_rate = cdns_phy->link_rate;
+	u16 val;
+	int index, i, k;
+
+	/* DP PLL data rate 0/1 clock divider value */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= 0x00FF;
+	if (link_rate <= RATE_2_7)
+		val |= 0x2400;
+	else
+		val |= 0x1200;
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+
+	/* High speed clock 0/1 div */
+	val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
+	val &= 0xFFCC;
+	if (link_rate <= RATE_2_7)
+		val |= 0x0011;
+	cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
+
+	for (k = 0; k < num_lanes; k++) {
+		val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
+		val = val & 0xCFFF;
+		if (link_rate <= RATE_2_7)
+			val |= 0x1000;
+		cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val);
+	}
+
+	/* DP PHY PLL 27MHz configuration */
+	index = link_rate_index(link_rate);
+	for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
+		cdns_phy_reg_write(cdns_phy, phy_pll_27m_cfg[i].addr,
+				phy_pll_27m_cfg[i].val[index]);
+
+	/* Transceiver control and diagnostic registers */
+	for (k = 0; k < num_lanes; k++) {
+		val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
+		val = val & 0x8FFF;
+		if (link_rate <= RATE_2_7)
+			val |= 0x2000;
+		else
+			val |= 0x1000;
+		cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);
+	}
+
+	for (k = 0; k < num_lanes; k = k + 1) {
+		/* Power state machine registers */
+		cdns_phy_reg_write(cdns_phy, (XCVR_PSM_RCTRL | (k << 9)),  0xBEFC);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A0 | (k << 9)), 0x6799);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A1 | (k << 9)), 0x6798);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A2 | (k << 9)), 0x0098);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A3 | (k << 9)), 0x0098);
+		/* Receiver calibration power state definition register */
+		val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
+		val &= 0xFFBB;
+		cdns_phy_reg_write(cdns_phy, (RX_PSC_CAL | (k << 9)), val);
+		val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0  | (k << 9));
+		val &= 0xFFBB;
+		cdns_phy_reg_write(cdns_phy, (RX_PSC_A0  | (k << 9)), val);
+	}
+}
+
+static void hdptx_dp_phy_ref_clock_type(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 val;
+
+	val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+	val &= 0xFF8F;
+	/*
+	 * single ended reference clock (val |= 0x0030);
+	 * differential clock  (val |= 0x0000);
+	 *
+	 * for differential clock on the refclk_p and
+	 * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
+	 * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
+	 */
+	val |= 0x0030;
+	cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
+}
+
+static int hdptx_dp_phy_power_up(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 val, i;
+
+	/* Enable HDP PLL’s for high speed clocks */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val |= (1 << 0);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL ready ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (val & (1 << 1))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL Ack failed\n");
+		return -1;
+	}
+
+	/* Enable HDP PLL’s data rate and full rate clocks out of PMA. */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val |= (1 << 2);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL clock enable ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (val & (1 << 3))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL clock enable ACk failed\n");
+		return -1;
+	}
+
+	/* Configure PHY in A2 Mode */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x0004);
+	/* Wait for Power State A2 Ack */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
+		if (val & (1 << 6))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait A2 Ack failed\n");
+		return -1;
+	}
+
+	/* Configure PHY in A0 mode (PHY must be in the A0 power
+	 * state in order to transmit data)
+	 */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x0101);
+
+	/* Wait for Power State A0 Ack */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
+		if (val & (1 << 4))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait A0 Ack failed\n");
+		return -1;
+	}
+
+	cdns_phy->power_up = true;
+
+	return 0;
+}
+
+static void hdptx_dp_phy_power_down(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u16 val;
+	int i;
+
+	if (!cdns_phy->power_up)
+		return;
+
+	/* Place the PHY lanes in the A3 power state. */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x8);
+	/* Wait for Power State A3 Ack */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
+		if (val & (1 << 7))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait A3 Ack failed\n");
+		return;
+	}
+
+	/* Disable HDP PLL’s data rate and full rate clocks out of PMA. */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= ~(1 << 2);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL clock gate ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (!(val & (1 << 3)))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL clock gate Ack failed\n");
+		return;
+	}
+
+	/* Disable HDP PLL’s for high speed clocks */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= ~(1 << 0);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL disable ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (!(val & (1 << 1)))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL disable Ack failed\n");
+		return;
+	}
+}
+
+static int cdns_hdptx_dp_phy_on(struct phy *phy)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+
+	return hdptx_dp_phy_power_up(cdns_phy);
+}
+
+static int cdns_hdptx_dp_phy_off(struct phy *phy)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+
+	hdptx_dp_phy_power_down(cdns_phy);
+
+	return 0;
+}
+
+static int cdns_hdptx_dp_phy_init(struct phy *phy)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+	int ret;
+
+	hdptx_dp_phy_ref_clock_type(cdns_phy);
+
+	/* PHY power up */
+	ret = hdptx_dp_phy_power_up(cdns_phy);
+	if (ret < 0)
+		return ret;
+
+	hdptx_dp_aux_cfg(cdns_phy);
+
+	return ret;
+}
+
+static int cdns_hdptx_dp_configure(struct phy *phy,
+				     union phy_configure_opts *opts)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+	int ret;
+
+	cdns_phy->link_rate = opts->dp.link_rate;
+
+	/* Disable phy clock if PHY in power up state */
+	hdptx_dp_phy_power_down(cdns_phy);
+
+	if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) {
+		hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy);
+		hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy);
+	} else
+		dev_err(cdns_phy->dev, "Not support ref clock rate\n");
+
+	/* PHY power up */
+	ret = hdptx_dp_phy_power_up(cdns_phy);
+
+	return ret;
+}
+
+static const struct phy_ops cdns_hdptx_dp_phy_ops = {
+	.init		= cdns_hdptx_dp_phy_init,
+	.configure	= cdns_hdptx_dp_configure,
+	.power_on	= cdns_hdptx_dp_phy_on,
+	.power_off	= cdns_hdptx_dp_phy_off,
+	.owner		= THIS_MODULE,
+};
+
+static int cdns_hdptx_dp_phy_probe(struct platform_device *pdev)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
+	if (!cdns_phy)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, cdns_phy);
+	cdns_phy->dev = dev;
+	mutex_init(&cdns_phy->mbox_mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+	cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
+	if (IS_ERR(cdns_phy->regs))
+		return PTR_ERR(cdns_phy->regs);
+
+	if (of_property_read_u32(node, "cdns,num-lanes",
+				 &cdns_phy->num_lanes)) {
+		dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
+			node->full_name);
+		return -EINVAL;
+	}
+
+	phy = devm_phy_create(dev, node, &cdns_hdptx_dp_phy_ops);
+	if (IS_ERR(phy))
+		return PTR_ERR(phy);
+
+	cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
+	of_property_read_u32(node, "cdns,max-bit-rate",
+			     &cdns_phy->max_bit_rate);
+
+	switch (cdns_phy->max_bit_rate) {
+	/* valid bit rate */
+	case 1620:
+	case 2160:
+	case 2430:
+	case 2700:
+	case 3240:
+	case 4320:
+	case 5400:
+		break;
+	case 8100:
+	default:
+		dev_err(dev, "unsupported max bit rate: %dMbps\n",
+				cdns_phy->max_bit_rate);
+		return -EINVAL;
+	}
+
+	dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
+		cdns_phy->max_bit_rate / 1000,
+		cdns_phy->max_bit_rate % 1000);
+
+	phy->attrs.bus_width = cdns_phy->num_lanes;
+	phy->attrs.max_link_rate = cdns_phy->max_bit_rate;
+	phy->attrs.mode = PHY_MODE_DP;
+
+	cdns_phy->phy = phy;
+	phy_set_drvdata(phy, cdns_phy);
+
+	if (cdns_phy->num_lanes > MAX_NUM_LANES) {
+		dev_err(dev, "Invalid lane configuration\n");
+		return -EINVAL;
+	}
+
+	ret = hdptx_dp_ref_clk(cdns_phy);
+	if (ret) {
+		dev_err(dev, "Init clk fail\n");
+		return -EINVAL;
+	}
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		ret =  PTR_ERR(phy_provider);
+		goto clk_disable;
+	}
+
+	dev_dbg(dev, "link: (%d lanes)", cdns_phy->num_lanes);
+
+	return 0;
+
+clk_disable:
+	clk_disable_unprepare(cdns_phy->ref_clk);
+
+	return -EINVAL;
+}
+
+static int cdns_hdptx_dp_phy_remove(struct platform_device *pdev)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(cdns_phy->ref_clk);
+
+	return 0;
+}
+
+static const struct of_device_id cdns_hdptx_dp_phy_of_match[] = {
+	{
+		.compatible = "cdns,hdptx-dp-phy",
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(of, cdns_hdptx_dp_phy_of_match);
+
+static struct platform_driver cdns_hdptx_dp_phy_driver = {
+	.probe	= cdns_hdptx_dp_phy_probe,
+	.remove = cdns_hdptx_dp_phy_remove,
+	.driver = {
+		.name	= "cdns-hdptx-dp-phy",
+		.of_match_table	= cdns_hdptx_dp_phy_of_match,
+	}
+};
+module_platform_driver(cdns_hdptx_dp_phy_driver);
+
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_DESCRIPTION("Cadence HDP-TX DisplayPort PHY driver");
+MODULE_LICENSE("GPL");

Signature · 1 line

2.34.1

Signature · 1 line

~Vinod

Sandor Yu

author

2022-11-10 08:10 UTC #17 lore raw

RE: [EXT] Re: [PATCH v3 08/10] phy: cadence: Add driver for HDP-TX DisplyPort PHY

Thanks your comments,

Quoted 38 lines

-----Original Message-----
From: Vinod Koul <[email protected]>
Sent: 2022年11月10日 15:41
To: Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v3 08/10] phy: cadence: Add driver for HDP-TX DisplyPort PHY
Caution: EXT Email
Quoted 3 lines · Sandor Yu
Add Cadence HDP-TX DisplayPort PHY driver.
Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base
on
Quoted 12 lines
the configuration chosen.
DisplayPort PHY mode is configurated in the driver.
Signed-off-by Sandor Yu <[email protected]>
---
 drivers/phy/cadence/Kconfig                |   8 +
 drivers/phy/cadence/Makefile               |   1 +
 drivers/phy/cadence/phy-cadence-hdptx-dp.c | 774
+++++++++++++++++++++
 3 files changed, 783 insertions(+)
 create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 12 lines

drivers/phy/cadence/Kconfig config PHY_CADENCE_SALVO · line 50

Quoted 10 lines

drivers/phy/cadence/Kconfig +2 -0

index 1adde2d99ae7..1e1914d3afdc 100644
@@ -46,3 +46,11 @@ config PHY_CADENCE_SALVO
        Enable this to support the Cadence SALVO PHY driver,
        this PHY is a legacy PHY, and only are used for USB3
        and USB2.
+
+config PHY_CADENCE_HDPTX_DP

alphabetically sorted please

OK.

Quoted 13 lines

drivers/phy/cadence/Makefile obj-$(CONFIG_PHY_CADENCE_DPHY) +=
Quoted 12 lines
drivers/phy/cadence/Kconfig +6 -0
+     tristate "Cadence HDPTX DP PHY Driver"
+     depends on OF && HAS_IOMEM
+     depends on COMMON_CLK
+     select GENERIC_PHY
+     help
+       Enable this to support the Cadence HDPTX DP PHY driver
(quoted diff) +0 -0
b/drivers/phy/cadence/Makefile index e17f035ddece..fbdb0bc5ff11 100644
drivers/phy/cadence/Makefile +0 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_CADENCE_DPHY)        +=
cdns-dphy.o

Quoted 6 lines

drivers/phy/cadence/Makefile obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o · line 7
Quoted 4 lines
drivers/phy/cadence/Makefile +1 -0
 obj-$(CONFIG_PHY_CADENCE_DPHY_RX)    += cdns-dphy-rx.o
 obj-$(CONFIG_PHY_CADENCE_SIERRA)     += phy-cadence-sierra.o
 obj-$(CONFIG_PHY_CADENCE_SALVO)      += phy-cadence-salvo.o
+obj-$(CONFIG_PHY_CADENCE_HDPTX_DP)   += phy-cadence-hdptx-dp.o
here too

OK.

Quoted 154 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +146 -0

new file mode 100644
index 000000000000..079d43772d1d
@@ -0,0 +1,774 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence HDP-TX Display Port Interface (DP) PHY driver
+ *
+ * Copyright (C) 2022 NXP Semiconductor, Inc.
+ */
+#include <asm/unaligned.h>
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include <drm/bridge/cdns-mhdp-mailbox.h>
+
+#define ADDR_PHY_AFE 0x80000
+
+/* PHY registers */
+#define CMN_SSM_BIAS_TMR                0x0022
+#define CMN_PLLSM0_PLLEN_TMR            0x0029
+#define CMN_PLLSM0_PLLPRE_TMR           0x002A
+#define CMN_PLLSM0_PLLVREF_TMR          0x002B
+#define CMN_PLLSM0_PLLLOCK_TMR          0x002C
+#define CMN_PLLSM0_USER_DEF_CTRL        0x002F
+#define CMN_PSM_CLK_CTRL                0x0061
+#define CMN_CDIAG_REFCLK_CTRL           0x0062
+#define CMN_PLL0_VCOCAL_START           0x0081
+#define CMN_PLL0_VCOCAL_INIT_TMR        0x0084
+#define CMN_PLL0_VCOCAL_ITER_TMR        0x0085
+#define CMN_PLL0_INTDIV                 0x0094
+#define CMN_PLL0_FRACDIV                0x0095
+#define CMN_PLL0_HIGH_THR               0x0096
+#define CMN_PLL0_DSM_DIAG               0x0097
+#define CMN_PLL0_SS_CTRL1               0x0098
+#define CMN_PLL0_SS_CTRL2               0x0099
+#define CMN_ICAL_INIT_TMR               0x00C4
+#define CMN_ICAL_ITER_TMR               0x00C5
+#define CMN_RXCAL_INIT_TMR              0x00D4
+#define CMN_RXCAL_ITER_TMR              0x00D5
+#define CMN_TXPUCAL_CTRL                0x00E0
+#define CMN_TXPUCAL_INIT_TMR            0x00E4
+#define CMN_TXPUCAL_ITER_TMR            0x00E5
+#define CMN_TXPDCAL_CTRL                0x00F0
+#define CMN_TXPDCAL_INIT_TMR            0x00F4
+#define CMN_TXPDCAL_ITER_TMR            0x00F5
+#define CMN_ICAL_ADJ_INIT_TMR           0x0102
+#define CMN_ICAL_ADJ_ITER_TMR           0x0103
+#define CMN_RX_ADJ_INIT_TMR             0x0106
+#define CMN_RX_ADJ_ITER_TMR             0x0107
+#define CMN_TXPU_ADJ_CTRL               0x0108
+#define CMN_TXPU_ADJ_INIT_TMR           0x010A
+#define CMN_TXPU_ADJ_ITER_TMR           0x010B
+#define CMN_TXPD_ADJ_CTRL               0x010c
+#define CMN_TXPD_ADJ_INIT_TMR           0x010E
+#define CMN_TXPD_ADJ_ITER_TMR           0x010F
+#define CMN_DIAG_PLL0_FBH_OVRD          0x01C0
+#define CMN_DIAG_PLL0_FBL_OVRD          0x01C1
+#define CMN_DIAG_PLL0_OVRD              0x01C2
+#define CMN_DIAG_PLL0_TEST_MODE         0x01C4
+#define CMN_DIAG_PLL0_V2I_TUNE          0x01C5
+#define CMN_DIAG_PLL0_CP_TUNE           0x01C6
+#define CMN_DIAG_PLL0_LF_PROG           0x01C7
+#define CMN_DIAG_PLL0_PTATIS_TUNE1      0x01C8
+#define CMN_DIAG_PLL0_PTATIS_TUNE2      0x01C9
+#define CMN_DIAG_PLL0_INCLK_CTRL        0x01CA
+#define CMN_DIAG_PLL0_PXL_DIVH          0x01CB
+#define CMN_DIAG_PLL0_PXL_DIVL          0x01CC
+#define CMN_DIAG_HSCLK_SEL              0x01E0
+#define CMN_DIAG_PER_CAL_ADJ            0x01EC
+#define CMN_DIAG_CAL_CTRL               0x01ED
+#define CMN_DIAG_ACYA                   0x01FF
+#define XCVR_PSM_RCTRL                  0x4001
+#define XCVR_PSM_CAL_TMR                0x4002
+#define XCVR_PSM_A0IN_TMR               0x4003
+#define TX_TXCC_CAL_SCLR_MULT_0         0x4047
+#define TX_TXCC_CPOST_MULT_00_0         0x404C
+#define TX_TXCC_MGNFS_MULT_000_0        0x4050
+#define XCVR_DIAG_PLLDRC_CTRL           0x40E0
+#define XCVR_DIAG_PLLDRC_CTRL           0x40E0
+#define XCVR_DIAG_HSCLK_SEL             0x40E1
+#define XCVR_DIAG_BIDI_CTRL             0x40E8
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR   0x40F2
+#define XCVR_DIAG_LANE_FCM_EN_MGN       0x40F2
+#define TX_PSC_A0                       0x4100
+#define TX_PSC_A1                       0x4101
+#define TX_PSC_A2                       0x4102
+#define TX_PSC_A3                       0x4103
+#define TX_RCVDET_CTRL                  0x4120
+#define TX_RCVDET_EN_TMR                0x4122
+#define TX_RCVDET_EN_TMR                0x4122
+#define TX_RCVDET_ST_TMR                0x4123
+#define TX_RCVDET_ST_TMR                0x4123
+#define TX_BIST_CTRL                    0x4140
+#define TX_BIST_UDDWR                   0x4141
+#define TX_DIAG_TX_CTRL                 0x41E0
+#define TX_DIAG_TX_DRV                  0x41E1
+#define TX_DIAG_BGREF_PREDRV_DELAY      0x41E7
+#define TX_DIAG_BGREF_PREDRV_DELAY      0x41E7
+#define XCVR_PSM_RCTRL_1                0x4201
+#define TX_TXCC_CAL_SCLR_MULT_1         0x4247
+#define TX_TXCC_CPOST_MULT_00_1         0x424C
+#define TX_TXCC_MGNFS_MULT_000_1        0x4250
+#define XCVR_DIAG_PLLDRC_CTRL_1         0x42E0
+#define XCVR_DIAG_HSCLK_SEL_1           0x42E1
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR_1 0x42F2
+#define TX_RCVDET_EN_TMR_1              0x4322
+#define TX_RCVDET_ST_TMR_1              0x4323
+#define TX_DIAG_ACYA_0                  0x41FF
+#define TX_DIAG_ACYA_1                  0x43FF
+#define TX_DIAG_ACYA_2                  0x45FF
+#define TX_DIAG_ACYA_3                  0x47FF
+#define TX_ANA_CTRL_REG_1               0x5020
+#define TX_ANA_CTRL_REG_2               0x5021
+#define TXDA_COEFF_CALC                 0x5022
+#define TX_DIG_CTRL_REG_1               0x5023
+#define TX_DIG_CTRL_REG_2               0x5024
+#define TXDA_CYA_AUXDA_CYA              0x5025
+#define TX_ANA_CTRL_REG_3               0x5026
+#define TX_ANA_CTRL_REG_4               0x5027
+#define TX_ANA_CTRL_REG_5               0x5029
+#define RX_PSC_A0                       0x8000
+#define RX_PSC_CAL                      0x8006
+#define PMA_LANE_CFG                    0xC000
+#define PIPE_CMN_CTRL1                  0xC001
+#define PIPE_CMN_CTRL2                  0xC002
+#define PIPE_COM_LOCK_CFG1              0xC003
+#define PIPE_COM_LOCK_CFG2              0xC004
+#define PIPE_RCV_DET_INH                0xC005
+#define PHY_HDP_MODE_CTRL               0xC008
+#define PHY_HDP_CLK_CTL                 0xC009
+#define STS                             0xC00F
+#define PHY_ISO_CMN_CTRL                0xC010
+#define PHY_ISO_CMN_CTRL                0xC010
+#define PHY_HDP_TX_CTL_L0               0xC408
+#define PHY_DP_TX_CTL                   0xC408
+#define PHY_HDP_TX_CTL_L1               0xC448
+#define PHY_HDP_TX_CTL_L2               0xC488
+#define PHY_HDP_TX_CTL_L3               0xC4C8
+#define PHY_PMA_CMN_CTRL1               0xC800
+#define PMA_CMN_CTRL1                   0xC800
+#define PHY_PMA_ISO_CMN_CTRL            0xC810
+#define PHY_PMA_ISO_PLL_CTRL1           0xC812
+#define PHY_PMA_ISOLATION_CTRL          0xC81F
+#define PHY_ISOLATION_CTRL              0xC81F
+#define PHY_PMA_ISO_XCVR_CTRL           0xCC11

Quoted 8 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 152

Quoted 6 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +6 -0

+#define PHY_PMA_ISO_LINK_MODE           0xCC12
+#define PHY_PMA_ISO_PWRST_CTRL          0xCC13
+#define PHY_PMA_ISO_TX_DATA_LO          0xCC14
+#define PHY_PMA_ISO_TX_DATA_HI          0xCC15
+#define PHY_PMA_ISO_RX_DATA_LO          0xCC16
+#define PHY_PMA_ISO_RX_DATA_HI          0xCC17

do you use all these?

I will remove unused later.

Quoted 670 lines

Quoted 15 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +14 -0

+
+#define MAX_NUM_LANES                4
+#define DEFAULT_MAX_BIT_RATE 5400 /* in Mbps */
+
+#define REF_CLK_27MHZ                27000000
+
+enum dp_link_rate {
+     RATE_1_6 = 162000,
+     RATE_2_1 = 216000,
+     RATE_2_4 = 243000,
+     RATE_2_7 = 270000,
+     RATE_3_2 = 324000,
+     RATE_4_3 = 432000,
+     RATE_5_4 = 540000,

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     RATE_8_1 = 810000,
+};
+
+struct phy_pll_reg {
+     u16 val[7];
+     u32 addr;
+};
+
+static const struct phy_pll_reg phy_pll_27m_cfg[] = {
+     /*  1.62    2.16    2.43    2.7     3.24    4.32    5.4

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 177

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E },

CMN_PLL0_VCOCAL_INIT_TMR },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 178

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B },

CMN_PLL0_VCOCAL_ITER_TMR },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 179

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x30B9, 0x3087, 0x3096, 0x30B4, 0x30B9, 0x3087, 0x30B4 },

CMN_PLL0_VCOCAL_START },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 180

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0077, 0x009F, 0x00B3, 0x00C7, 0x0077, 0x009F, 0x00C7 },

CMN_PLL0_INTDIV },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 181

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0xF9DA, 0xF7CD, 0xF6C7, 0xF5C1, 0xF9DA, 0xF7CD, 0xF5C1 },

CMN_PLL0_FRACDIV },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 182

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x001E, 0x0028, 0x002D, 0x0032, 0x001E, 0x0028, 0x0032 },

CMN_PLL0_HIGH_THR },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 183

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 },

CMN_PLL0_DSM_DIAG },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 184

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 },

CMN_PLLSM0_USER_DEF_CTRL },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 185

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },

CMN_DIAG_PLL0_OVRD },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 186

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },

CMN_DIAG_PLL0_FBH_OVRD },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 187

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },

CMN_DIAG_PLL0_FBL_OVRD },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 188

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0006, 0x0007, 0x0007, 0x0007, 0x0006, 0x0007, 0x0007 },

CMN_DIAG_PLL0_V2I_TUNE },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 189

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0043, 0x0043, 0x0043, 0x0042, 0x0043, 0x0043, 0x0042 },

CMN_DIAG_PLL0_CP_TUNE },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 190

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 },

CMN_DIAG_PLL0_LF_PROG },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 191

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0100, 0x0001, 0x0001, 0x0001, 0x0100, 0x0001, 0x0001 },

CMN_DIAG_PLL0_PTATIS_TUNE1 },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 192

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0007, 0x0001, 0x0001, 0x0001, 0x0007, 0x0001, 0x0001 },

CMN_DIAG_PLL0_PTATIS_TUNE2 },

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 193

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 },

CMN_DIAG_PLL0_TEST_MODE},

Quoted 9 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +9 -0

+     {{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 },
+CMN_PSM_CLK_CTRL } };
+
+struct cdns_hdptx_dp_phy {
+     void __iomem *regs;     /* DPTX registers base */
+     struct device *dev;
+     struct phy *phy;
+     struct mutex mbox_mutex; /* mutex to protect mailbox */
+     struct clk *ref_clk;

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     u32 ref_clk_rate;
+     u32 num_lanes;
+     u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
+     u32 link_rate;
+     bool power_up;
+};
+
+static int cdns_phy_reg_write(struct cdns_hdptx_dp_phy *cdns_phy, u32
+addr, u32 val) {
+     return cdns_mhdp_reg_write(cdns_phy, ADDR_PHY_AFE + (addr <<

2),

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 219

Quoted 7 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +7 -0

+val); }
+
+static u32 cdns_phy_reg_read(struct cdns_hdptx_dp_phy *cdns_phy, u32
+addr) {
+     u32 reg32;
+
+     cdns_mhdp_reg_read(cdns_phy, ADDR_PHY_AFE + (addr << 2),

&reg32);

Quoted 42 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +42 -0

+     return reg32;
+}
+
+static int link_rate_index(u32 rate)
+{
+     switch (rate) {
+     case RATE_1_6:
+             return 0;
+     case RATE_2_1:
+             return 1;
+     case RATE_2_4:
+             return 2;
+     case RATE_2_7:
+             return 3;
+     case RATE_3_2:
+             return 4;
+     case RATE_4_3:
+             return 5;
+     case RATE_5_4:
+             return 6;
+     default:
+             return -1;
+     }
+}
+
+static int hdptx_dp_ref_clk(struct cdns_hdptx_dp_phy *cdns_phy) {
+     struct device *dev = cdns_phy->dev;
+     u32 ref_clk_rate;
+     int ret;
+
+     cdns_phy->ref_clk = devm_clk_get(dev, "refclk");
+     if (IS_ERR(cdns_phy->ref_clk)) {
+             dev_err(dev, "phy ref clock not found\n");
+             return PTR_ERR(cdns_phy->ref_clk);
+     }
+
+     ret = clk_prepare_enable(cdns_phy->ref_clk);
+     if (ret) {
+             dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
+             return ret;
+     }
+

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     ref_clk_rate = clk_get_rate(cdns_phy->ref_clk);
+     if (!ref_clk_rate) {
+             dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
+             goto err_ref_clk;
+     }
+
+     if (ref_clk_rate == REF_CLK_27MHZ)
+             cdns_phy->ref_clk_rate = ref_clk_rate;
+     else {
+             dev_err(cdns_phy->dev, "Not support Ref Clock

Rate(%dHz)\n", ref_clk_rate);

Quoted 36 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +36 -0

+             goto err_ref_clk;
+     }
+
+     return 0;
+
+err_ref_clk:
+     clk_disable_unprepare(cdns_phy->ref_clk);
+     return -EINVAL;
+}
+
+static void hdptx_dp_aux_cfg(struct cdns_hdptx_dp_phy *cdns_phy) {
+     /* Power up Aux */
+     cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 1);
+
+     cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_1, 0x3);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, 36);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA018);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030C);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0000);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x1001);
+     ndelay(150);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA098);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA198);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
+     ndelay(150);
+     cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f); }
+
+/* PMA common configuration for 27MHz */ static void
+hdptx_dp_phy_pma_cmn_cfg_27mhz(struct cdns_hdptx_dp_phy

*cdns_phy) {

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 12 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +12 -0

+     u32 num_lanes = cdns_phy->num_lanes;
+     u16 val;
+     int k;
+
+     val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+     val &= 0xFFF7;
+     val |= 0x0008;
+     cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
+
+     /* Startup state machine registers */
+     cdns_phy_reg_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0087);
+     cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLEN_TMR,

0x001B);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 330

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR,

0x0036);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 331

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLVREF_TMR,

0x001B);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 332

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR,

0x006C);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 5 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +5 -0

+
+     /* Current calibration registers */
+     cdns_phy_reg_write(cdns_phy, CMN_ICAL_INIT_TMR, 0x0044);
+     cdns_phy_reg_write(cdns_phy, CMN_ICAL_ITER_TMR, 0x0006);
+     cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_INIT_TMR,

0x0022);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 338

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_ITER_TMR,

0x0006);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 4 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +4 -0

+
+     /* Resistor calibration registers */
+     cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0022);
+     cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_ITER_TMR,

0x0006);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 343

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_INIT_TMR,

0x0022);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 344

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_ITER_TMR,

0x0006);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 346

Quoted 2 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +2 -0

+     cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0022);
+     cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_ITER_TMR,

0x0006);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 347

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_INIT_TMR,

0x0022);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 348

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+     cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_ITER_TMR,

0x0006);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 8 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +8 -0

+     cdns_phy_reg_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0022);
+     cdns_phy_reg_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
+     cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_INIT_TMR, 0x0022);
+     cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_ITER_TMR, 0x0006);
+
+     for (k = 0; k < num_lanes; k = k + 1) {
+             /* Power state machine registers */
+             cdns_phy_reg_write(cdns_phy, XCVR_PSM_CAL_TMR  |

(k << 9), 0x016D);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 357

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             cdns_phy_reg_write(cdns_phy, XCVR_PSM_A0IN_TMR |

(k << 9), 0x016D);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 359

Quoted 2 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +2 -0

+             /* Transceiver control and diagnostic registers */
+             cdns_phy_reg_write(cdns_phy,

XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x00A2);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 360

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             cdns_phy_reg_write(cdns_phy,

TX_DIAG_BGREF_PREDRV_DELAY | (k << 9), 0x0097);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 362

Quoted 2 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +2 -0

+             /* Transmitter receiver detect registers */
+             cdns_phy_reg_write(cdns_phy, TX_RCVDET_EN_TMR | (k

<< 9), 0x0A8C);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 363

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             cdns_phy_reg_write(cdns_phy, TX_RCVDET_ST_TMR | (k

<< 9), 0x0036);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 8 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +8 -0

+     }
+
+     cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
+     cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
+     cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
+     cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1); }
+
+static void hdptx_dp_phy_pma_cmn_pll0_27mhz(struct

cdns_hdptx_dp_phy

Quoted 14 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +14 -0

+*cdns_phy) {
+     u32 num_lanes = cdns_phy->num_lanes;
+     u32 link_rate = cdns_phy->link_rate;
+     u16 val;
+     int index, i, k;
+
+     /* DP PLL data rate 0/1 clock divider value */
+     val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+     val &= 0x00FF;
+     if (link_rate <= RATE_2_7)
+             val |= 0x2400;
+     else
+             val |= 0x1200;
+     cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+
+     /* High speed clock 0/1 div */
+     val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
+     val &= 0xFFCC;
+     if (link_rate <= RATE_2_7)
+             val |= 0x0011;
+     cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
+
+     for (k = 0; k < num_lanes; k++) {
+             val = cdns_phy_reg_read(cdns_phy,

(XCVR_DIAG_HSCLK_SEL | (k << 9)));

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 4 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +4 -0

+             val = val & 0xCFFF;
+             if (link_rate <= RATE_2_7)
+                     val |= 0x1000;
+             cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL |

(k << 9)), val);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 11 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +11 -0

+     }
+
+     /* DP PHY PLL 27MHz configuration */
+     index = link_rate_index(link_rate);
+     for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
+             cdns_phy_reg_write(cdns_phy, phy_pll_27m_cfg[i].addr,
+                             phy_pll_27m_cfg[i].val[index]);
+
+     /* Transceiver control and diagnostic registers */
+     for (k = 0; k < num_lanes; k++) {
+             val = cdns_phy_reg_read(cdns_phy,

(XCVR_DIAG_PLLDRC_CTRL | (k << 9)));

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 6 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +6 -0

+             val = val & 0x8FFF;
+             if (link_rate <= RATE_2_7)
+                     val |= 0x2000;
+             else
+                     val |= 0x1000;
+             cdns_phy_reg_write(cdns_phy,

(XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 5 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +5 -0

+     }
+
+     for (k = 0; k < num_lanes; k = k + 1) {
+             /* Power state machine registers */
+             cdns_phy_reg_write(cdns_phy, (XCVR_PSM_RCTRL | (k <<

9)), 0xBEFC);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 422

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             cdns_phy_reg_write(cdns_phy, (TX_PSC_A0 | (k << 9)),

0x6799);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 423

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             cdns_phy_reg_write(cdns_phy, (TX_PSC_A1 | (k << 9)),

0x6798);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 424

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             cdns_phy_reg_write(cdns_phy, (TX_PSC_A2 | (k << 9)),

0x0098);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 425

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             cdns_phy_reg_write(cdns_phy, (TX_PSC_A3 | (k << 9)),

0x0098);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 427

Quoted 2 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +2 -0

+             /* Receiver calibration power state definition register */
+             val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k <<

9));

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 429

Quoted 2 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +2 -0
+             val &= 0xFFBB;
+             cdns_phy_reg_write(cdns_phy, (RX_PSC_CAL | (k << 9)),

val);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 430

Quoted 1 line

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +1 -0
+             val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0  | (k <<

9));

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 432

Quoted 2 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +2 -0
+             val &= 0xFFBB;
+             cdns_phy_reg_write(cdns_phy, (RX_PSC_A0  | (k << 9)),

val);

Quoted 43 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +43 -0

+     }
+}
+
+static void hdptx_dp_phy_ref_clock_type(struct cdns_hdptx_dp_phy
+*cdns_phy) {
+     u32 val;
+
+     val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+     val &= 0xFF8F;
+     /*
+      * single ended reference clock (val |= 0x0030);
+      * differential clock  (val |= 0x0000);
+      *
+      * for differential clock on the refclk_p and
+      * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
+      * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
+      */
+     val |= 0x0030;
+     cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val); }
+
+static int hdptx_dp_phy_power_up(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+     u32 val, i;
+
+     /* Enable HDP PLL’s for high speed clocks */
+     val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+     val |= (1 << 0);
+     cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+     /* Wait for PLL ready ACK */
+     for (i = 0; i < 10; i++) {
+             val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+             if (val & (1 << 1))
+                     break;
+             msleep(20);
+     }
+     if (i == 10) {
+             dev_err(cdns_phy->dev, "Wait PLL Ack failed\n");
+             return -1;
+     }
+
+     /* Enable HDP PLL’s data rate and full rate clocks out of PMA. */
+     val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+     val |= (1 << 2);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+     /* Wait for PLL clock enable ACK */
+     for (i = 0; i < 10; i++) {
+             val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+             if (val & (1 << 3))
+                     break;
+             msleep(20);
+     }
+     if (i == 10) {
+             dev_err(cdns_phy->dev, "Wait PLL clock enable ACk

failed\n");

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 8 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +8 -0

+             return -1;
+     }
+
+     /* Configure PHY in A2 Mode */
+     cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x0004);
+     /* Wait for Power State A2 Ack */
+     for (i = 0; i < 10; i++) {
+             val = cdns_phy_reg_read(cdns_phy,

PHY_HDP_MODE_CTRL);

Quoted 7 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +7 -0

+             if (val & (1 << 6))
+                     break;
+             msleep(20);
+     }
+     if (i == 10) {
+             dev_err(cdns_phy->dev, "Wait A2 Ack failed\n");
+             return -1;

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     }
+
+     /* Configure PHY in A0 mode (PHY must be in the A0 power
+      * state in order to transmit data)
+      */
+     cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x0101);
+
+     /* Wait for Power State A0 Ack */
+     for (i = 0; i < 10; i++) {
+             val = cdns_phy_reg_read(cdns_phy,

PHY_HDP_MODE_CTRL);

Quoted 17 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +17 -0

+             if (val & (1 << 4))
+                     break;
+             msleep(20);
+     }
+     if (i == 10) {
+             dev_err(cdns_phy->dev, "Wait A0 Ack failed\n");
+             return -1;
+     }
+
+     cdns_phy->power_up = true;
+
+     return 0;
+}
+
+static void hdptx_dp_phy_power_down(struct cdns_hdptx_dp_phy
+*cdns_phy) {
+     u16 val;

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     int i;
+
+     if (!cdns_phy->power_up)
+             return;
+
+     /* Place the PHY lanes in the A3 power state. */
+     cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x8);
+     /* Wait for Power State A3 Ack */
+     for (i = 0; i < 10; i++) {
+             val = cdns_phy_reg_read(cdns_phy,

PHY_HDP_MODE_CTRL);

Quoted 12 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +12 -0

+             if (val & (1 << 7))
+                     break;
+             msleep(20);
+     }
+     if (i == 10) {
+             dev_err(cdns_phy->dev, "Wait A3 Ack failed\n");
+             return;
+     }
+
+     /* Disable HDP PLL’s data rate and full rate clocks out of PMA. */
+     val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+     val &= ~(1 << 2);

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+     /* Wait for PLL clock gate ACK */
+     for (i = 0; i < 10; i++) {
+             val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+             if (!(val & (1 << 3)))
+                     break;
+             msleep(20);
+     }
+     if (i == 10) {
+             dev_err(cdns_phy->dev, "Wait PLL clock gate Ack

failed\n");

Quoted 41 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +41 -0

+             return;
+     }
+
+     /* Disable HDP PLL’s for high speed clocks */
+     val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+     val &= ~(1 << 0);
+     cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+     /* Wait for PLL disable ACK */
+     for (i = 0; i < 10; i++) {
+             val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+             if (!(val & (1 << 1)))
+                     break;
+             msleep(20);
+     }
+     if (i == 10) {
+             dev_err(cdns_phy->dev, "Wait PLL disable Ack failed\n");
+             return;
+     }
+}
+
+static int cdns_hdptx_dp_phy_on(struct phy *phy) {
+     struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+
+     return hdptx_dp_phy_power_up(cdns_phy); }
+
+static int cdns_hdptx_dp_phy_off(struct phy *phy) {
+     struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+
+     hdptx_dp_phy_power_down(cdns_phy);
+
+     return 0;
+}
+
+static int cdns_hdptx_dp_phy_init(struct phy *phy) {
+     struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+     int ret;
+
+     hdptx_dp_phy_ref_clock_type(cdns_phy);
+
+     /* PHY power up */
+     ret = hdptx_dp_phy_power_up(cdns_phy);

drivers/phy/cadence/phy-cadence-hdptx-dp.c line 620

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     if (ret < 0)
+             return ret;
+
+     hdptx_dp_aux_cfg(cdns_phy);
+
+     return ret;
+}
+
+static int cdns_hdptx_dp_configure(struct phy *phy,
+                                  union phy_configure_opts *opts)

{

Quoted 39 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +39 -0

+     struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+     int ret;
+
+     cdns_phy->link_rate = opts->dp.link_rate;
+
+     /* Disable phy clock if PHY in power up state */
+     hdptx_dp_phy_power_down(cdns_phy);
+
+     if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) {
+             hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy);
+             hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy);
+     } else
+             dev_err(cdns_phy->dev, "Not support ref clock rate\n");
+
+     /* PHY power up */
+     ret = hdptx_dp_phy_power_up(cdns_phy);
+
+     return ret;
+}
+
+static const struct phy_ops cdns_hdptx_dp_phy_ops = {
+     .init           = cdns_hdptx_dp_phy_init,
+     .configure      = cdns_hdptx_dp_configure,
+     .power_on       = cdns_hdptx_dp_phy_on,
+     .power_off      = cdns_hdptx_dp_phy_off,
+     .owner          = THIS_MODULE,
+};
+
+static int cdns_hdptx_dp_phy_probe(struct platform_device *pdev) {
+     struct cdns_hdptx_dp_phy *cdns_phy;
+     struct device *dev = &pdev->dev;
+     struct device_node *node = dev->of_node;
+     struct phy_provider *phy_provider;
+     struct resource *res;
+     struct phy *phy;
+     int ret;
+
+     cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
+     if (!cdns_phy)

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+             return -ENOMEM;
+
+     dev_set_drvdata(dev, cdns_phy);
+     cdns_phy->dev = dev;
+     mutex_init(&cdns_phy->mbox_mutex);
+
+     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+     if (!res)
+             return -ENODEV;
+     cdns_phy->regs = devm_ioremap(dev, res->start,

resource_size(res));

Quoted 48 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +48 -0

+     if (IS_ERR(cdns_phy->regs))
+             return PTR_ERR(cdns_phy->regs);
+
+     if (of_property_read_u32(node, "cdns,num-lanes",
+                              &cdns_phy->num_lanes)) {
+             dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
+                     node->full_name);
+             return -EINVAL;
+     }
+
+     phy = devm_phy_create(dev, node, &cdns_hdptx_dp_phy_ops);
+     if (IS_ERR(phy))
+             return PTR_ERR(phy);
+
+     cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
+     of_property_read_u32(node, "cdns,max-bit-rate",
+                          &cdns_phy->max_bit_rate);
+
+     switch (cdns_phy->max_bit_rate) {
+     /* valid bit rate */
+     case 1620:
+     case 2160:
+     case 2430:
+     case 2700:
+     case 3240:
+     case 4320:
+     case 5400:
+             break;
+     case 8100:
+     default:
+             dev_err(dev, "unsupported max bit rate: %dMbps\n",
+                             cdns_phy->max_bit_rate);
+             return -EINVAL;
+     }
+
+     dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
+             cdns_phy->max_bit_rate / 1000,
+             cdns_phy->max_bit_rate % 1000);
+
+     phy->attrs.bus_width = cdns_phy->num_lanes;
+     phy->attrs.max_link_rate = cdns_phy->max_bit_rate;
+     phy->attrs.mode = PHY_MODE_DP;
+
+     cdns_phy->phy = phy;
+     phy_set_drvdata(phy, cdns_phy);
+
+     if (cdns_phy->num_lanes > MAX_NUM_LANES) {
+             dev_err(dev, "Invalid lane configuration\n");

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+             return -EINVAL;
+     }
+
+     ret = hdptx_dp_ref_clk(cdns_phy);
+     if (ret) {
+             dev_err(dev, "Init clk fail\n");
+             return -EINVAL;
+     }
+
+     phy_provider = devm_of_phy_provider_register(dev,

of_phy_simple_xlate);

Quoted 7 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +7 -0

+     if (IS_ERR(phy_provider)) {
+             ret =  PTR_ERR(phy_provider);
+             goto clk_disable;
+     }
+
+     dev_dbg(dev, "link: (%d lanes)", cdns_phy->num_lanes);
+

drivers/phy/cadence/phy-cadence-hdptx-dp.c

Quoted 10 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +10 -0

+     return 0;
+
+clk_disable:
+     clk_disable_unprepare(cdns_phy->ref_clk);
+
+     return -EINVAL;
+}
+
+static int cdns_hdptx_dp_phy_remove(struct platform_device *pdev) {
+     struct cdns_hdptx_dp_phy *cdns_phy =

platform_get_drvdata(pdev);

Quoted 24 lines

drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +24 -0

+
+     clk_disable_unprepare(cdns_phy->ref_clk);
+
+     return 0;
+}
+
+static const struct of_device_id cdns_hdptx_dp_phy_of_match[] = {
+     {
+             .compatible = "cdns,hdptx-dp-phy",
+     },
+     {}
+};
+MODULE_DEVICE_TABLE(of, cdns_hdptx_dp_phy_of_match);
+
+static struct platform_driver cdns_hdptx_dp_phy_driver = {
+     .probe  = cdns_hdptx_dp_phy_probe,
+     .remove = cdns_hdptx_dp_phy_remove,
+     .driver = {
+             .name   = "cdns-hdptx-dp-phy",
+             .of_match_table = cdns_hdptx_dp_phy_of_match,
+     }
+};
+module_platform_driver(cdns_hdptx_dp_phy_driver);
+

Quoted 8 lines

Quoted 5 lines
drivers/phy/cadence/phy-cadence-hdptx-dp.c new file +3 -1
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_DESCRIPTION("Cadence HDP-TX DisplayPort PHY driver");
+MODULE_LICENSE("GPL");
--
2.34.1
--
~Vinod

B.R
Sandor

Sandor Yu

author

2022-11-08 13:02 UTC #18 lore raw

PATCH v3 9/10 dt-bindings: phy: Add Cadence HDP-TX HDMI PHY

In reply to Sandor Yu

Add bindings for Cadence HDP-TX HDMI PHY.

Signed-off-by Sandor Yu <[email protected]>

---
 .../bindings/phy/cdns,hdptx-hdmi-phy.yaml     | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml

Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml new file +50 -0

new file mode 100644
index 000000000000..c2ed17ffe6ef
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,hdptx-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX(HDMI/DisplayPort) PHY for HDMI protocol
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - cdns,hdptx-hdmi-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      description:
+        PHY reference clock.
+
+  clock-names:
+    items:
+      - const: refclk
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/phy/phy.h>
+    hdmi_phy: phy@32c00000 {
+      compatible = "cdns,hdptx-hdmi-phy";
+      reg = <0x32c00000 0x100000>;
+      #phy-cells = <0>;
+      clocks = <&hdmi_phy_27m>;
+      clock-names = "refclk";
+    };

Signature · 1 line

2.34.1

Krzysztof Kozlowski

2022-11-15 13:27 UTC #19 lore raw

Re: [PATCH v3 09/10] dt-bindings: phy: Add Cadence HDP-TX HDMI PHY

Quoted 26 lines · Sandor Yu

Add bindings for Cadence HDP-TX HDMI PHY.

Signed-off-by Sandor Yu <[email protected]>

---
 .../bindings/phy/cdns,hdptx-hdmi-phy.yaml     | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml

Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml new file +12 -0

new file mode 100644
index 000000000000..c2ed17ffe6ef
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,hdptx-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX(HDMI/DisplayPort) PHY for HDMI protocol
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+properties:

Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml line 22

Quoted 10 lines

Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml new file +10 -0
+  compatible:
+    enum:
+      - cdns,hdptx-hdmi-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      description:

Same problem.

Best regards,
Krzysztof

Sandor Yu

author

2022-11-08 13:02 UTC #20 lore raw

PATCH v3 10/10 phy: cadence: Add driver for HDP-TX HDMI PHY

In reply to Sandor Yu

Add Cadence HDP-TX HDMI PHY driver.

Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. HDMI PHY mode is configurated in the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/phy/cadence/Kconfig                  |   8 +
 drivers/phy/cadence/Makefile                 |   1 +
 drivers/phy/cadence/phy-cadence-hdptx-hdmi.c | 948 +++++++++++++++++++
 3 files changed, 957 insertions(+)
 create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-hdmi.c

drivers/phy/cadence/Kconfig +8 -0

index 1e1914d3afdc..b6eae2d4a52c 100644
@@ -54,3 +54,11 @@ config PHY_CADENCE_HDPTX_DP
 	select GENERIC_PHY
 	help
 	  Enable this to support the Cadence HDPTX DP PHY driver
+
+config PHY_CADENCE_HDPTX_HDMI
+	tristate "Cadence HDPTX HDMI PHY Driver"
+	depends on OF && HAS_IOMEM
+	depends on COMMON_CLK
+	select GENERIC_PHY
+	help
+	  Enable this to support the Cadence HDPTX HDMI PHY driver.

drivers/phy/cadence/Makefile +1 -0

index fbdb0bc5ff11..b5a676c1c54c 100644
@@ -5,3 +5,4 @@ obj-$(CONFIG_PHY_CADENCE_DPHY_RX)	+= cdns-dphy-rx.o
 obj-$(CONFIG_PHY_CADENCE_SIERRA)	+= phy-cadence-sierra.o
 obj-$(CONFIG_PHY_CADENCE_SALVO)	+= phy-cadence-salvo.o
 obj-$(CONFIG_PHY_CADENCE_HDPTX_DP)	+= phy-cadence-hdptx-dp.o
+obj-$(CONFIG_PHY_CADENCE_HDPTX_HDMI) += phy-cadence-hdptx-hdmi.o

drivers/phy/cadence/phy-cadence-hdptx-hdmi.c new file +948 -0

948 lines not on this page · raw message

Signature · 1 line

2.34.1

Jani Nikula

2022-11-08 13:15 UTC #21 lore raw

In reply to Sandor Yu

Quoted 2 lines · Sandor Yu

The patch set initial support for Cadence MHDP(HDMI/DP) DRM bridge drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for iMX8MQ.

Has some get_maintainer.pl guidance changed recently or something, or why am I increasingly being Cc'd on patches that are largely irrelevant to me?

BR,
Jani.

Signature · 1 line

Jani Nikula, Intel Open Source Graphics Center

Sandor Yu

author

2022-11-08 13:50 UTC #22 lore raw

Run get_maintainer.pl for patch 1,
Your email address is list as follow,
Jani Nikula <[email protected]> (commit_signer:2/8=25%)

And I add the email address that comment as "commit_signer" into Cc list.

B.R
Sandor

Quoted 32 lines

-----Original Message-----
From: Jani Nikula <[email protected]>
Sent: 2022年11月8日 21:16
To: Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; [email protected]; [email protected]; Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v3 00/10] Initial support for Cadence MHDP(HDMI/DP) for i.MX8MQ
Caution: EXT Email
Quoted 2 lines · Sandor Yu
The patch set initial support for Cadence MHDP(HDMI/DP) DRM bridge drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for iMX8MQ.
Has some get_maintainer.pl guidance changed recently or something, or why am I increasingly being Cc'd on patches that are largely irrelevant to me?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center

Jani Nikula

2022-11-08 16:27 UTC #23 lore raw

Quoted 5 lines · Sandor Yu

Run get_maintainer.pl for patch 1,
Your email address is list as follow,
Jani Nikula <[email protected]> (commit_signer:2/8=25%)
And I add the email address that comment as "commit_signer" into Cc list.

Please don't do that.

get_maintainer.pl gives you no less than *eight* people as designated maintainers or reviewers.

I've acked two commits with one-line collateral changes to the files in question.

BR,
Jani.

Signature · 1 line

Jani Nikula, Intel Open Source Graphics Center

Krzysztof Kozlowski

2022-11-15 13:29 UTC #24 lore raw

In reply to Sandor Yu

Quoted 5 lines · Sandor Yu

Run get_maintainer.pl for patch 1,
Your email address is list as follow,
Jani Nikula <[email protected]> (commit_signer:2/8=25%)
And I add the email address that comment as "commit_signer" into Cc list.

That's not a maintainer entry, but contributor. No need to Cc occasional contributors, except people interested in the driver.

Best regards,
Krzysztof