Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ

MHDP8546 mailbox access functions will be share to other mhdp driver and Cadence HDP-TX HDMI/DP PHY drivers.
Create a new mhdp helper driver and move all those functions into.

cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(), because it use the DPTX command ID DPTX_WRITE_REGISTER.

New cdns_mhdp_reg_write() is created with the general command ID GENERAL_REGISTER_WRITE.

rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver, use cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write() same as the other mailbox access functions.

Signed-off-by Sandor Yu <[email protected]>

---
v10->v11:
- rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver, use cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write() same as the other mailbox access functions.
- use static for cdns_mhdp_mailbox_write() and cdns_mhdp_mailbox_read() and remove them from EXPORT_SYMBOL_GPL().

v9->v10:
*use mhdp helper driver to replace macro functions, move maibox access function and mhdp hdmi/dp common API functions into the driver.

 drivers/gpu/drm/bridge/cadence/Kconfig        |   4 +
 drivers/gpu/drm/bridge/cadence/Makefile       |   1 +
 .../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 304 +++++++++++++
 .../drm/bridge/cadence/cdns-mhdp8546-core.c   | 403 +++---------------
 .../drm/bridge/cadence/cdns-mhdp8546-core.h   |  44 +-
 include/drm/bridge/cdns-mhdp-helper.h         |  94 ++++
 6 files changed, 476 insertions(+), 374 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
 create mode 100644 include/drm/bridge/cdns-mhdp-helper.h

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Kconfig index ec35215a20034..0b7b4626a7af0 100644

drivers/gpu/drm/bridge/cadence/Kconfig +4 -0

@@ -20,6 +20,9 @@ config DRM_CDNS_DSI_J721E
 	  the routing of the DSS DPI signal to the Cadence DSI.
 endif
 
+config CDNS_MHDP_HELPER
+	tristate
+
 config DRM_CDNS_MHDP8546
 	tristate "Cadence DPI/DP bridge"
 	select DRM_DISPLAY_DP_HELPER

@@ -27,6 +30,7 @@ config DRM_CDNS_MHDP8546
 	select DRM_DISPLAY_HELPER
 	select DRM_KMS_HELPER
 	select DRM_PANEL_BRIDGE
+	select CDNS_MHDP_HELPER
 	depends on OF
 	help
 	  Support Cadence DPI to DP bridge. This is an internal

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Makefile index
c95fd5b81d137..087dc074820d7 100644

drivers/gpu/drm/bridge/cadence/Makefile +1 -0

@@ -2,6 +2,7 @@
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
 cdns-dsi-y := cdns-dsi-core.o
 cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
+obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o
 obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
 cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
 cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file mode 100644 index 0000000000000..8cabd79ad9663

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +5 -0

@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 NXP Semiconductor, Inc.
+ *
+ */

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +4 -0

+	ret = readx_poll_timeout(readl, base->regs + CDNS_MAILBOX_EMPTY,
+				 empty, !empty, MAILBOX_RETRY_US,
+				 MAILBOX_TIMEOUT_US);
+	if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +13 -0

+int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_base *base,
+				  u8 module_id, u8 opcode,
+				  u16 req_size)
+{
+	u32 mbox_size, i;
+	u8 header[4];
+	int ret;
+
+	/* read the header of the message */
+	for (i = 0; i < sizeof(header); i++) {
+		ret = cdns_mhdp_mailbox_read(base);
+		if (ret < 0)
+			return ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +125 -0

+		 * clear the mailbox by reading its contents.
+		 */
+		for (i = 0; i < mbox_size; i++)
+			if (cdns_mhdp_mailbox_read(base) < 0)
+				break;
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_recv_header);
+
+int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_base *base,
+				u8 *buff, u16 buff_size)
+{
+	u32 i;
+	int ret;
+
+	for (i = 0; i < buff_size; i++) {
+		ret = cdns_mhdp_mailbox_read(base);
+		if (ret < 0)
+			return ret;
+
+		buff[i] = ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_recv_data);
+
+int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, u8 module_id,
+			   u8 opcode, u16 size, u8 *message)
+{
+	u8 header[4];
+	int ret, i;
+
+	header[0] = opcode;
+	header[1] = module_id;
+	put_unaligned_be16(size, header + 2);
+
+	for (i = 0; i < sizeof(header); i++) {
+		ret = cdns_mhdp_mailbox_write(base, header[i]);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < size; i++) {
+		ret = cdns_mhdp_mailbox_write(base, message[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send);
+
+/* General helper functions */
+int cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32 *value)
+{
+	u8 msg[4], resp[8];
+	int ret;
+
+	put_unaligned_be32(addr, msg);
+
+	mutex_lock(base->mbox_mutex);
+
+	ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_GENERAL,
+				     GENERAL_REGISTER_READ,
+				     sizeof(msg), msg);
+	if (ret)
+		goto out;
+
+	ret = cdns_mhdp_mailbox_recv_header(base, MB_MODULE_ID_GENERAL,
+					    GENERAL_REGISTER_READ,
+					    sizeof(resp));
+	if (ret)
+		goto out;
+
+	ret = cdns_mhdp_mailbox_recv_data(base, resp, sizeof(resp));
+	if (ret)
+		goto out;
+
+	/* Returned address value should be the same as requested */
+	if (memcmp(msg, resp, sizeof(msg))) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	*value = get_unaligned_be32(resp + 4);
+
+out:
+	mutex_unlock(base->mbox_mutex);
+	if (ret) {
+		dev_err(base->dev, "Failed to read register\n");
+		*value = 0;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_read);
+
+int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32 val)
+{
+	u8 msg[8];
+	int ret;
+
+	put_unaligned_be32(addr, msg);
+	put_unaligned_be32(val, msg + 4);
+
+	mutex_lock(base->mbox_mutex);
+
+	ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_GENERAL,
+				     GENERAL_REGISTER_WRITE,
+				     sizeof(msg), msg);
+
+	mutex_unlock(base->mbox_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_write);
+
+/* DPTX helper functions */
+int cdns_mhdp_dp_reg_write(struct cdns_mhdp_base *base, u16 addr, u32 val)
+{

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +12 -0

+
+	mutex_unlock(base->mbox_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write);
+
+int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr,
+			       u8 start_bit, u8 bits_no, u32 val)
+{
+	u8 field[8];
+	int ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+
+	mutex_unlock(base->mbox_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write_bit);
+
+int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base,
+			u32 addr, u8 *data, u16 len)
+{

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +25 -0

+	if (ret)
+		goto out;
+
+	ret = cdns_mhdp_mailbox_recv_header(base, MB_MODULE_ID_DP_TX,
+					    DPTX_READ_DPCD,
+					    sizeof(reg) + len);
+	if (ret)
+		goto out;
+
+	ret = cdns_mhdp_mailbox_recv_data(base, reg, sizeof(reg));
+	if (ret)
+		goto out;
+
+	ret = cdns_mhdp_mailbox_recv_data(base, data, len);
+
+out:
+	mutex_unlock(base->mbox_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_read);
+
+int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8 value)
+{
+	u8 msg[6], reg[5];

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +12 -0

+out:
+	mutex_unlock(base->mbox_mutex);
+
+	if (ret)
+		dev_err(base->dev, "dpcd write failed: %d\n", ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_write);
+
+MODULE_DESCRIPTION("Cadence MHDP Helper driver");
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_LICENSE("GPL");

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index 6af565ac307ae..9d9dbb976868c 100644

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -45

@@ -73,298 +73,28 @@ static void cdns_mhdp_bridge_hpd_disable(struct
 drm_bridge *bridge) mhdp->regs + CDNS_APB_INT_MASK);
 }
 
-static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
-{
-	int ret, empty;
-
-	WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
-	ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
-				 empty, !empty, MAILBOX_RETRY_US,
-				 MAILBOX_TIMEOUT_US);
-	if (ret < 0)
-		return ret;
-
-	return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
-}
-
-static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
-{
-	int ret, full;
-
-	WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
-	ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
-				 full, !full, MAILBOX_RETRY_US,
-				 MAILBOX_TIMEOUT_US);
-	if (ret < 0)
-		return ret;
-
-	writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
-
-	return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_device *mhdp,
-					 u8 module_id, u8 opcode,
-					 u16 req_size)
-{
-	u32 mbox_size, i;
-	u8 header[4];
-	int ret;
-
-	/* read the header of the message */
-	for (i = 0; i < sizeof(header); i++) {
-		ret = cdns_mhdp_mailbox_read(mhdp);
-		if (ret < 0)
-			return ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -30

-		 * clear the mailbox by reading its contents.
-		 */
-		for (i = 0; i < mbox_size; i++)
-			if (cdns_mhdp_mailbox_read(mhdp) < 0)
-				break;
-
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_device *mhdp,
-				       u8 *buff, u16 buff_size)
-{
-	u32 i;
-	int ret;
-
-	for (i = 0; i < buff_size; i++) {
-		ret = cdns_mhdp_mailbox_read(mhdp);
-		if (ret < 0)
-			return ret;
-
-		buff[i] = ret;
-	}
-
-	return 0;
-}
-
-static int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8

module_id, - u8 opcode, u16 size, u8

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -70

-{
-	u8 header[4];
-	int ret, i;
-
-	header[0] = opcode;
-	header[1] = module_id;
-	put_unaligned_be16(size, header + 2);
-
-	for (i = 0; i < sizeof(header); i++) {
-		ret = cdns_mhdp_mailbox_write(mhdp, header[i]);
-		if (ret)
-			return ret;
-	}
-
-	for (i = 0; i < size; i++) {
-		ret = cdns_mhdp_mailbox_write(mhdp, message[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-static
-int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr, u32 *value)
-{
-	u8 msg[4], resp[8];
-	int ret;
-
-	put_unaligned_be32(addr, msg);
-
-	mutex_lock(&mhdp->mbox_mutex);
-
-	ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL,
-				     GENERAL_REGISTER_READ,
-				     sizeof(msg), msg);
-	if (ret)
-		goto out;
-
-	ret = cdns_mhdp_mailbox_recv_header(mhdp, MB_MODULE_ID_GENERAL,
-					    GENERAL_REGISTER_READ,
-					    sizeof(resp));
-	if (ret)
-		goto out;
-
-	ret = cdns_mhdp_mailbox_recv_data(mhdp, resp, sizeof(resp));
-	if (ret)
-		goto out;
-
-	/* Returned address value should be the same as requested */
-	if (memcmp(msg, resp, sizeof(msg))) {
-		ret = -EINVAL;
-		goto out;
-	}
-
-	*value = get_unaligned_be32(resp + 4);
-
-out:
-	mutex_unlock(&mhdp->mbox_mutex);
-	if (ret) {
-		dev_err(mhdp->dev, "Failed to read register\n");
-		*value = 0;
-	}
-
-	return ret;
-}
-
-static
-int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u16 addr, u32 val)
-{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -11

-
-	mutex_unlock(&mhdp->mbox_mutex);
-
-	return ret;
-}
-
 static
-int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr,
-			    u8 start_bit, u8 bits_no, u32 val)
-{
-	u8 field[8];
-	int ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-
-	mutex_unlock(&mhdp->mbox_mutex);
-
-	return ret;
-}
-
-static
-int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
-			u32 addr, u8 *data, u16 len)
-{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -23

-	if (ret)
-		goto out;
-
-	ret = cdns_mhdp_mailbox_recv_header(mhdp, MB_MODULE_ID_DP_TX,
-					    DPTX_READ_DPCD,
-					    sizeof(reg) + len);
-	if (ret)
-		goto out;
-
-	ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
-	if (ret)
-		goto out;
-
-	ret = cdns_mhdp_mailbox_recv_data(mhdp, data, len);
-
-out:
-	mutex_unlock(&mhdp->mbox_mutex);
-
-	return ret;
-}
-
-static
-int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value)
+int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool

enable) {

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-	u8 msg[6], reg[5];
+	u8 status;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -13

 	if (ret)
 		goto out;
 
-	if (addr != get_unaligned_be24(reg + 2))
-		ret = -EINVAL;
-
-out:
-	mutex_unlock(&mhdp->mbox_mutex);
-
-	if (ret)
-		dev_err(mhdp->dev, "dpcd write failed: %d\n", ret);
-	return ret;
-}
-
-static
-int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool

enable) -{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-	u8 msg[5];
-	int ret, i;
-
-	msg[0] = GENERAL_MAIN_CONTROL;
-	msg[1] = MB_MODULE_ID_GENERAL;
-	msg[2] = 0;
-	msg[3] = 1;
-	msg[4] = enable ? FW_ACTIVE : FW_STANDBY;
-
-	mutex_lock(&mhdp->mbox_mutex);

out:

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 	mutex_unlock(&mhdp->mbox_mutex);

@@ -382,18 +112,18 @@ int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device
 *mhdp)
 
 	mutex_lock(&mhdp->mbox_mutex);
 
-	ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
+	ret = cdns_mhdp_mailbox_send(&mhdp->base, MB_MODULE_ID_DP_TX,
 				     DPTX_HPD_STATE, 0, NULL);
 	if (ret)
 		goto err_get_hpd;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

 		if (ret)
 			continue;
 

@@ -464,17 +194,17 @@ int cdns_mhdp_read_hpd_event(struct cdns_mhdp_device
 *mhdp)
 
 	mutex_lock(&mhdp->mbox_mutex);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 out:
 	mutex_unlock(&mhdp->mbox_mutex);

@@ -512,20 +242,20 @@ int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp,
 unsigned int nlanes,
 
 	mutex_lock(&mhdp->mbox_mutex);
 
-	ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
+	ret = cdns_mhdp_mailbox_send(&mhdp->base, MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -2

 	if (ret)
 		goto out;
 
-	ret = cdns_mhdp_mailbox_recv_data(mhdp, hdr, sizeof(hdr));
+	ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, hdr, sizeof(hdr));
 	if (ret)
 		goto out;

@@ -533,7 +263,7 @@ int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp,
 unsigned int nlanes, if (addr != DP_LANE0_1_STATUS)
 		goto out;
 
-	ret = cdns_mhdp_mailbox_recv_data(mhdp, link_status,
+	ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, link_status,
 					  DP_LINK_STATUS_SIZE);
 
 out:

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +4 -4

 			if (!ret)
 				continue;

@@ -859,7 +589,7 @@ static ssize_t cdns_mhdp_transfer(struct drm_dp_aux
 *aux, return ret;
 		}
 	} else {
-		ret = cdns_mhdp_dpcd_read(mhdp, msg->address,
+		ret = cdns_mhdp_dpcd_read(&mhdp->base, msg->address,
 					  msg->buffer, msg->size);
 		if (ret) {
 			dev_err(mhdp->dev,

@@ -887,12 +617,12 @@ static int cdns_mhdp_link_training_init(struct
 cdns_mhdp_device *mhdp) if (!mhdp->host.scrambler)
 		reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG, reg32);
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_ENHNCD,
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_ENHNCD,
 			    mhdp->sink.enhanced & mhdp->host.enhanced);
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_LANE_EN,
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_LANE_EN,
 			    CDNS_DP_LANE_EN_LANES(mhdp-
 link.num_lanes));
 

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 	cdns_mhdp_link_configure(&mhdp->aux, &mhdp->link);

@@ -913,7 +643,7 @@ static int cdns_mhdp_link_training_init(struct
 cdns_mhdp_device *mhdp) return ret;
 	}
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG,
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,
 			    CDNS_PHY_COMMON_CONFIG |
 			    CDNS_PHY_TRAINING_EN |
 			    CDNS_PHY_TRAINING_TYPE(1) |

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 	/* Reset PHY config */
 	reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_TYPE(1);
 	if (!mhdp->host.scrambler)
 		reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;
-	cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG, reg32);
 
 	return 0;
 err:

@@ -1347,7 +1077,7 @@ static int cdns_mhdp_link_training(struct

cdns_mhdp_device *mhdp, reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_TYPE(1);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 	if (!mhdp->host.scrambler)
 		reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;
-	cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG, reg32);
 
 	drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,
 			   DP_TRAINING_PATTERN_DISABLE);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 	/* Spread AMP if required, enable 8b/10b coding */
 	amp[0] = cdns_mhdp_get_ssc_supported(mhdp) ? DP_SPREAD_AMP_0_5 : 0;

@@ -1837,7 +1567,7 @@ static void cdns_mhdp_configure_video(struct
 cdns_mhdp_device *mhdp, if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		bnd_hsync2vsync |= CDNS_IP_DET_INTERLACE_FORMAT;
 
-	cdns_mhdp_reg_write(mhdp, CDNS_BND_HSYNC2VSYNC(stream_id),
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_BND_HSYNC2VSYNC(stream_id),
 			    bnd_hsync2vsync);
 
 	hsync2vsync_pol_ctrl = 0;

@@ -1845,10 +1575,10 @@ static void cdns_mhdp_configure_video(struct

cdns_mhdp_device *mhdp, hsync2vsync_pol_ctrl |=
CDNS_H2V_HSYNC_POL_ACTIVE_LOW;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +5 -5

 			    msa_horizontal_1);
 
 	msa_v0 = mode->crtc_vtotal - mode->crtc_vsync_start;
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_MSA_VERTICAL_0(stream_id),
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_MSA_VERTICAL_0(stream_id),
 			    CDNS_DP_MSAV0_V_TOTAL(mode->crtc_vtotal) |
 			    CDNS_DP_MSAV0_VSYNC_START(msa_v0));
 

@@ -1890,7 +1620,7 @@ static void cdns_mhdp_configure_video(struct
 cdns_mhdp_device *mhdp, CDNS_DP_MSAV1_VDISP_WIDTH(mode->crtc_vdisplay);
 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 		msa_vertical_1 |= CDNS_DP_MSAV1_VSYNC_POL_LOW;
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_MSA_VERTICAL_1(stream_id),
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_MSA_VERTICAL_1(stream_id),
 			    msa_vertical_1);
 
 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&

@@ -1902,14 +1632,14 @@ static void cdns_mhdp_configure_video(struct
 cdns_mhdp_device *mhdp, if (pxlfmt == DRM_COLOR_FORMAT_YCBCR420)
 		misc1 = CDNS_DP_TEST_VSC_SDP;
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_MSA_MISC(stream_id),
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_MSA_MISC(stream_id),
 			    misc0 | (misc1 << 8));
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_HORIZONTAL(stream_id),
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_HORIZONTAL(stream_id),
 			    CDNS_DP_H_HSYNC_WIDTH(hsync) |
 			    CDNS_DP_H_H_TOTAL(mode->crtc_hdisplay));
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_VERTICAL_0(stream_id),
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_VERTICAL_0(stream_id),
 			    CDNS_DP_V0_VHEIGHT(mode->crtc_vdisplay) |
 			    CDNS_DP_V0_VSTART(msa_v0));
 

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+	ret = cdns_mhdp_reg_read(&mhdp->base, CDNS_DP_FRAMER_GLOBAL_CONFIG,
 &framer); if (ret < 0) {
 		dev_err(mhdp->dev,

"Failed to read CDNS_DP_FRAMER_GLOBAL_CONFIG

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 }
 
 static void cdns_mhdp_sst_enable(struct cdns_mhdp_device *mhdp,

@@ -1966,15 +1696,15 @@ static void cdns_mhdp_sst_enable(struct
 cdns_mhdp_device *mhdp,
 
 	mhdp->stream_id = 0;
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_TU,
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_FRAMER_TU,
 			    CDNS_DP_FRAMER_TU_VS(vs) |
 			    CDNS_DP_FRAMER_TU_SIZE(tu_size) |

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 		goto out;
 	}
 
-	cdns_mhdp_reg_write(mhdp, CDNS_DPTX_CAR,
+	cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_CAR,
 			    resp | CDNS_VIF_CLK_EN | CDNS_VIF_CLK_RSTN);
 
 	connector = drm_atomic_get_new_connector_for_encoder(state,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +5 -0

 	if (mhdp->info && mhdp->info->ops && mhdp->info->ops->disable)

@@ -2502,6 +2232,11 @@ static int cdns_mhdp_probe(struct platform_device
 *pdev)
 
 	platform_set_drvdata(pdev, mhdp);
 
+	/* init base struct for access mailbox  */
+	mhdp->base.dev = mhdp->dev;
+	mhdp->base.regs = mhdp->regs;
+	mhdp->base.mbox_mutex = &mhdp->mbox_mutex;
+
 	mhdp->info = of_device_get_match_data(dev);
 

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

 	clk_prepare_enable(clk);

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h index bad2fc0c73066..f08db38c82bbd 100644

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +1 -4

@@ -15,6 +15,7 @@
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 
+#include <drm/bridge/cdns-mhdp-helper.h>
 #include <drm/display/drm_dp_helper.h>
 #include <drm/drm_bridge.h>
 #include <drm/drm_connector.h>

@@ -27,10 +28,6 @@ struct phy;
 #define CDNS_APB_CTRL				0x00000
 #define CDNS_CPU_STALL				BIT(3)
 
-#define CDNS_MAILBOX_FULL			0x00008
-#define CDNS_MAILBOX_EMPTY			0x0000c
-#define CDNS_MAILBOX_TX_DATA			0x00010
-#define CDNS_MAILBOX_RX_DATA			0x00014
 #define CDNS_KEEP_ALIVE				0x00018
 #define CDNS_KEEP_ALIVE_MASK			GENMASK(7, 0)
 

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +0 -9

 #define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT	16
 
-/* mailbox */
-#define MAILBOX_RETRY_US			1000
-#define MAILBOX_TIMEOUT_US			2000000
-
-#define MB_OPCODE_ID				0
-#define MB_MODULE_ID				1
-#define MB_SIZE_MSB_ID				2
-#define MB_SIZE_LSB_ID				3
-#define MB_DATA_ID				4

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +2 -19

 #define CDNS_MHDP_IMEM				0x10000
 
-#define GENERAL_MAIN_CONTROL			0x01
-#define GENERAL_TEST_ECHO			0x02
-#define GENERAL_BUS_SETTINGS			0x03
-#define GENERAL_TEST_ACCESS			0x04
-#define GENERAL_REGISTER_READ			0x07
-
-#define DPTX_SET_POWER_MNG			0x00
-#define DPTX_GET_EDID				0x02
-#define DPTX_READ_DPCD				0x03
-#define DPTX_WRITE_DPCD				0x04
-#define DPTX_ENABLE_EVENT			0x05
-#define DPTX_WRITE_REGISTER			0x06
-#define DPTX_READ_REGISTER			0x07
-#define DPTX_WRITE_FIELD			0x08
-#define DPTX_READ_EVENT				0x0a
-#define DPTX_GET_LAST_AUX_STAUS			0x0e
-#define DPTX_HPD_STATE				0x11
-#define DPTX_ADJUST_LT				0x12
-
 #define FW_STANDBY				0
 #define FW_ACTIVE				1
 

@@ -352,6 +314,8 @@ struct cdns_mhdp_hdcp {
 };
 
 struct cdns_mhdp_device {
+	struct cdns_mhdp_base base;
+
 	void __iomem *regs;
 	void __iomem *sapb_regs;
 	void __iomem *j721e_regs;

(quoted diff) +0 -0

b/include/drm/bridge/cdns-mhdp-helper.h new file mode 100644 index 0000000000000..477e67601ee5f

include/drm/bridge/cdns-mhdp-helper.h new file +66 -0

@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 NXP Semiconductor, Inc.
+ */
+#ifndef __CDNS_MHDP_HELPER_H__
+#define __CDNS_MHDP_HELPER_H__
+
+#include <asm/unaligned.h>
+#include <linux/iopoll.h>
+
+/* mailbox regs offset */
+#define CDNS_MAILBOX_FULL			0x00008
+#define CDNS_MAILBOX_EMPTY			0x0000c
+#define CDNS_MAILBOX_TX_DATA			0x00010
+#define CDNS_MAILBOX_RX_DATA			0x00014
+
+#define MAILBOX_RETRY_US			1000
+#define MAILBOX_TIMEOUT_US			2000000
+
+/* Module ID Code */
+#define MB_MODULE_ID_DP_TX			0x01
+#define MB_MODULE_ID_HDMI_TX			0x03
+#define MB_MODULE_ID_HDCP_TX			0x07
+#define MB_MODULE_ID_HDCP_RX			0x08
+#define MB_MODULE_ID_HDCP_GENERAL		0x09
+#define MB_MODULE_ID_GENERAL			0x0A
+
+/* General Commands */
+#define GENERAL_MAIN_CONTROL			0x01
+#define GENERAL_TEST_ECHO			0x02
+#define GENERAL_BUS_SETTINGS			0x03
+#define GENERAL_TEST_ACCESS			0x04
+#define GENERAL_REGISTER_WRITE			0x05
+#define GENERAL_WRITE_FIELD			0x06
+#define GENERAL_REGISTER_READ			0x07
+#define GENERAL_GET_HPD_STATE			0x11
+
+/* DPTX Commands */
+#define DPTX_SET_POWER_MNG			0x00
+#define DPTX_SET_HOST_CAPABILITIES		0x01
+#define DPTX_GET_EDID				0x02
+#define DPTX_READ_DPCD				0x03
+#define DPTX_WRITE_DPCD				0x04
+#define DPTX_ENABLE_EVENT			0x05
+#define DPTX_WRITE_REGISTER			0x06
+#define DPTX_READ_REGISTER			0x07
+#define DPTX_WRITE_FIELD			0x08
+#define DPTX_TRAINING_CONTROL			0x09
+#define DPTX_READ_EVENT				0x0a
+#define DPTX_READ_LINK_STAT			0x0b
+#define DPTX_SET_VIDEO				0x0c
+#define DPTX_SET_AUDIO				0x0d
+#define DPTX_GET_LAST_AUX_STAUS			0x0e
+#define DPTX_SET_LINK_BREAK_POINT		0x0f
+#define DPTX_FORCE_LANES			0x10
+#define DPTX_HPD_STATE				0x11
+#define DPTX_ADJUST_LT				0x12
+
+/* HDMI TX Commands */
+#define HDMI_TX_READ				0x00
+#define HDMI_TX_WRITE				0x01
+#define HDMI_TX_UPDATE_READ			0x02
+#define HDMI_TX_EDID				0x03
+#define HDMI_TX_EVENTS				0x04
+#define HDMI_TX_HPD_STATUS			0x05
+

include/drm/bridge/cdns-mhdp-helper.h new file +12 -0

+/* General commands helper functions */
+int cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32 *value);
+int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32 val);
+
+/* DPTX commands helper functions */
+int cdns_mhdp_dp_reg_write(struct cdns_mhdp_base *base, u16 addr, u32 val);
+int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr, +	
 
      u8 start_bit, u8 bits_no, u32 val);
+int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base,
+			u32 addr, u8 *data, u16 len);
+int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8 value);
+
+#endif /* __CDNS_MHDP_HELPER_H__ */

Hi Sandor,

thanks for the update.

One small typo in the commit message: 'Creat' -> 'Create'

Am Dienstag, 17. Oktober 2023, 09:03:57 CEST schrieb Sandor Yu:

Quoted 4 lines

MHDP8546 mailbox access functions will be share to other mhdp driver and Cadence HDP-TX HDMI/DP PHY drivers.
Create a new mhdp helper driver and move all those functions into.

Quoted 8 lines

cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(), because it use the DPTX command ID DPTX_WRITE_REGISTER.

New cdns_mhdp_reg_write() is created with the general command ID GENERAL_REGISTER_WRITE.

rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver, use cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write() same

as

Quoted 7 lines

the other mailbox access functions.

Signed-off-by Sandor Yu <[email protected]>

---
v10->v11:
- rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver, use cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write() same

as

Quoted 3 lines

the other mailbox access functions.
- use static for cdns_mhdp_mailbox_write() and
cdns_mhdp_mailbox_read() and remove them from

EXPORT_SYMBOL_GPL().

Quoted 47 lines

v9->v10:
*use mhdp helper driver to replace macro functions, move maibox
access function and mhdp hdmi/dp common API functions into the driver.

 drivers/gpu/drm/bridge/cadence/Kconfig        |   4 +
 drivers/gpu/drm/bridge/cadence/Makefile       |   1 +
 .../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 304 +++++++++++++
 .../drm/bridge/cadence/cdns-mhdp8546-core.c   | 403 +++---------------
 .../drm/bridge/cadence/cdns-mhdp8546-core.h   |  44 +-
 include/drm/bridge/cdns-mhdp-helper.h         |  94 ++++
 6 files changed, 476 insertions(+), 374 deletions(-)  create mode
100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
 create mode 100644 include/drm/bridge/cdns-mhdp-helper.h

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Kconfig index
ec35215a20034..0b7b4626a7af0
100644

drivers/gpu/drm/bridge/cadence/Kconfig +4 -1

@@ -20,6 +20,9 @@ config DRM_CDNS_DSI_J721E
        the routing of the DSS DPI signal to the Cadence DSI.
 endif
 
+config CDNS_MHDP_HELPER
+     tristate
+
 config DRM_CDNS_MHDP8546
      tristate "Cadence DPI/DP bridge"
      select DRM_DISPLAY_DP_HELPER

@@ -27,6 +30,7 @@ config DRM_CDNS_MHDP8546
      select DRM_DISPLAY_HELPER
      select DRM_KMS_HELPER
      select DRM_PANEL_BRIDGE
+     select CDNS_MHDP_HELPER
      depends on OF
      help
        Support Cadence DPI to DP bridge. This is an internal diff
--git a/drivers/gpu/drm/bridge/cadence/Makefile

b/drivers/gpu/drm/bridge/cadence/Makefile index
c95fd5b81d137..087dc074820d7 100644

drivers/gpu/drm/bridge/cadence/Makefile +0 -0

@@ -2,6 +2,7 @@
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o  cdns-dsi-y :=

Quoted 4 lines

cdns-dsi-core.o
cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
+obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o

cdns-mhdp8546-y

Quoted 17 lines

:= cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) +=
cdns-mhdp8546-j721e.o diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file mode 100644 index 0000000000000..8cabd79ad9663

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +8 -0

@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 NXP Semiconductor, Inc.
+ *
+ */
+#include <drm/bridge/cdns-mhdp-helper.h> #include
+<linux/dev_printk.h> #include <linux/module.h>
+

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 15

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +5 -0

+/* Mailbox helper functions */
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_base *base) {
+     int ret, empty;
+
+     WARN_ON(!mutex_is_locked(base->mbox_mutex));

Actually this should be moved to cdns_mhdp_mailbox_recv_header() and cdns_mhdp_mailbox_recv_data().

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 14

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+     ret = readx_poll_timeout(readl, base->regs +

CDNS_MAILBOX_EMPTY,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 30

Quoted 12 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +12 -0

+                              empty, !empty, MAILBOX_RETRY_US,
+                              MAILBOX_TIMEOUT_US);
+     if (ret < 0)
+             return ret;
+
+     return readl(base->regs + CDNS_MAILBOX_RX_DATA) & 0xff; }
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_base *base, u8
+val) {
+     int ret, full;
+
+     WARN_ON(!mutex_is_locked(base->mbox_mutex));

I think this should be moved to cdns_mhdp_mailbox_send() as well.

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 41

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+     ret = readx_poll_timeout(readl, base->regs + CDNS_MAILBOX_FULL,
+                              full, !full, MAILBOX_RETRY_US,
+                              MAILBOX_TIMEOUT_US);
+     if (ret < 0)
+             return ret;
+
+     writel(val, base->regs + CDNS_MAILBOX_TX_DATA);
+
+     return 0;
+}

Nice, much better having these as static now.

Quoted 14 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +13 -0

+int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_base *base,
+                               u8 module_id, u8 opcode,
+                               u16 req_size) {
+     u32 mbox_size, i;
+     u8 header[4];
+     int ret;
+
+     /* read the header of the message */
+     for (i = 0; i < sizeof(header); i++) {
+             ret = cdns_mhdp_mailbox_read(base);
+             if (ret < 0)
+                     return ret;
+

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+             header[i] = ret;
+     }
+
+     mbox_size = get_unaligned_be16(header + 2);
+
+     if (opcode != header[0] || module_id != header[1] ||
+         req_size != mbox_size) {
+             /*
+              * If the message in mailbox is not what we want, we
+ need

to

Quoted 21 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +21 -0

+              * clear the mailbox by reading its contents.
+              */
+             for (i = 0; i < mbox_size; i++)
+                     if (cdns_mhdp_mailbox_read(base) < 0)
+                             break;
+
+             return -EINVAL;
+     }
+
+     return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_recv_header);
+
+int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_base *base,
+                             u8 *buff, u16 buff_size) {
+     u32 i;
+     int ret;
+
+     for (i = 0; i < buff_size; i++) {
+             ret = cdns_mhdp_mailbox_read(base);
+             if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+                     return ret;
+
+             buff[i] = ret;
+     }
+
+     return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_recv_data);
+
+int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, u8

module_id,

Quoted 31 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +31 -0

+                        u8 opcode, u16 size, u8 *message) {
+     u8 header[4];
+     int ret, i;
+
+     header[0] = opcode;
+     header[1] = module_id;
+     put_unaligned_be16(size, header + 2);
+
+     for (i = 0; i < sizeof(header); i++) {
+             ret = cdns_mhdp_mailbox_write(base, header[i]);
+             if (ret)
+                     return ret;
+     }
+
+     for (i = 0; i < size; i++) {
+             ret = cdns_mhdp_mailbox_write(base, message[i]);
+             if (ret)
+                     return ret;
+     }
+
+     return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send);
+
+/* General helper functions */
+int cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32
+*value) {
+     u8 msg[4], resp[8];
+     int ret;
+
+     put_unaligned_be32(addr, msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+
+     mutex_lock(base->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_GENERAL,
+                                  GENERAL_REGISTER_READ,
+                                  sizeof(msg), msg);
+     if (ret)
+             goto out;
+
+     ret = cdns_mhdp_mailbox_recv_header(base,

MB_MODULE_ID_GENERAL,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 132

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+

GENERAL_REGISTER_READ,

Quoted 39 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +39 -0

+                                         sizeof(resp));
+     if (ret)
+             goto out;
+
+     ret = cdns_mhdp_mailbox_recv_data(base, resp, sizeof(resp));
+     if (ret)
+             goto out;
+
+     /* Returned address value should be the same as requested */
+     if (memcmp(msg, resp, sizeof(msg))) {
+             ret = -EINVAL;
+             goto out;
+     }
+
+     *value = get_unaligned_be32(resp + 4);
+
+out:
+     mutex_unlock(base->mbox_mutex);
+     if (ret) {
+             dev_err(base->dev, "Failed to read register\n");
+             *value = 0;
+     }
+
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_read);
+
+int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32
+val) {
+     u8 msg[8];
+     int ret;
+
+     put_unaligned_be32(addr, msg);
+     put_unaligned_be32(val, msg + 4);
+
+     mutex_lock(base->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_GENERAL,
+                                  GENERAL_REGISTER_WRITE,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+                                  sizeof(msg), msg);
+
+     mutex_unlock(base->mbox_mutex);
+
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_write);
+
+/* DPTX helper functions */
+int cdns_mhdp_dp_reg_write(struct cdns_mhdp_base *base, u16 addr,

u32

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +11 -0

+val) {
+     u8 msg[6];
+     int ret;
+
+     put_unaligned_be16(addr, msg);
+     put_unaligned_be32(val, msg + 2);
+
+     mutex_lock(base->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
+                                  DPTX_WRITE_REGISTER,

sizeof(msg),
msg);

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +11 -0

+
+     mutex_unlock(base->mbox_mutex);
+
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write);
+
+int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr,
+                            u8 start_bit, u8 bits_no, u32 val) {
+     u8 field[8];
+     int ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+
+     put_unaligned_be16(addr, field);
+     field[2] = start_bit;
+     field[3] = bits_no;
+     put_unaligned_be32(val, field + 4);
+
+     mutex_lock(base->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
+                                  DPTX_WRITE_FIELD,

sizeof(field),
field);

Quoted 9 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +9 -0

+
+     mutex_unlock(base->mbox_mutex);
+
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write_bit);
+
+int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base,
+                     u32 addr, u8 *data, u16 len) {

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+     u8 msg[5], reg[5];
+     int ret;
+
+     put_unaligned_be16(len, msg);
+     put_unaligned_be24(addr, msg + 2);
+
+     mutex_lock(base->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
+                                  DPTX_READ_DPCD, sizeof(msg),

msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +4 -0

+     if (ret)
+             goto out;
+
+     ret = cdns_mhdp_mailbox_recv_header(base,

MB_MODULE_ID_DP_TX,

Quoted 21 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +21 -0

+                                         DPTX_READ_DPCD,
+                                         sizeof(reg) + len);
+     if (ret)
+             goto out;
+
+     ret = cdns_mhdp_mailbox_recv_data(base, reg, sizeof(reg));
+     if (ret)
+             goto out;
+
+     ret = cdns_mhdp_mailbox_recv_data(base, data, len);
+
+out:
+     mutex_unlock(base->mbox_mutex);
+
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_read);
+
+int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8
+value) {
+     u8 msg[6], reg[5];

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+     int ret;
+
+     put_unaligned_be16(1, msg);
+     put_unaligned_be24(addr, msg + 2);
+     msg[5] = value;
+
+     mutex_lock(base->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
+                                  DPTX_WRITE_DPCD,

sizeof(msg),
msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +4 -0

+     if (ret)
+             goto out;
+
+     ret = cdns_mhdp_mailbox_recv_header(base,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 272

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+                                         DPTX_WRITE_DPCD,

sizeof(reg));

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 291

Quoted 9 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +9 -0

+     if (ret)
+             goto out;
+
+     ret = cdns_mhdp_mailbox_recv_data(base, reg, sizeof(reg));
+     if (ret)
+             goto out;
+
+     if (addr != get_unaligned_be24(reg + 2))
+             ret = -EINVAL;

No need to have the mutex locked while doing this check. This should be moved below 'out' label.

Quoted 19 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +12 -0

+out:
+     mutex_unlock(base->mbox_mutex);
+
+     if (ret)
+             dev_err(base->dev, "dpcd write failed: %d\n", ret);
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_write);
+
+MODULE_DESCRIPTION("Cadence MHDP Helper driver");
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_LICENSE("GPL");

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index 6af565ac307ae..9d9dbb976868c 100644

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct · line 80

Quoted 8 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -6

@@ -73,298 +73,28 @@ static void cdns_mhdp_bridge_hpd_disable(struct
 drm_bridge *bridge) mhdp->regs + CDNS_APB_INT_MASK);  }
 
-static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) -{
-     int ret, empty;
-
-     WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
-     ret = readx_poll_timeout(readl, mhdp->regs +

CDNS_MAILBOX_EMPTY,

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -5

-                              empty, !empty, MAILBOX_RETRY_US,
-                              MAILBOX_TIMEOUT_US);
-     if (ret < 0)
-             return ret;
-

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -9

-     return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
-}
-
-static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8
 val) -{
-     int ret, full;
-
-     WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
-     ret = readx_poll_timeout(readl, mhdp->regs +

CDNS_MAILBOX_FULL,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -11

-                              full, !full, MAILBOX_RETRY_US,
-                              MAILBOX_TIMEOUT_US);
-     if (ret < 0)
-             return ret;
-
-     writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
-
-     return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_device

*mhdp,

Quoted 12 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -12

-                                      u8 module_id, u8 opcode,
-                                      u16 req_size)
-{
-     u32 mbox_size, i;
-     u8 header[4];
-     int ret;
-
-     /* read the header of the message */
-     for (i = 0; i < sizeof(header); i++) {
-             ret = cdns_mhdp_mailbox_read(mhdp);
-             if (ret < 0)
-                     return ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-
-             header[i] = ret;
-     }
-
-     mbox_size = get_unaligned_be16(header + 2);
-
-     if (opcode != header[0] || module_id != header[1] ||
-         req_size != mbox_size) {
-             /*
-              * If the message in mailbox is not what we want, we need

to

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 13 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -13

-              * clear the mailbox by reading its contents.
-              */
-             for (i = 0; i < mbox_size; i++)
-                     if (cdns_mhdp_mailbox_read(mhdp) < 0)
-                             break;
-
-             return -EINVAL;
-     }
-
-     return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_device

*mhdp,

Quoted 17 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -17

-                                    u8 *buff, u16 buff_size)
-{
-     u32 i;
-     int ret;
-
-     for (i = 0; i < buff_size; i++) {
-             ret = cdns_mhdp_mailbox_read(mhdp);
-             if (ret < 0)
-                     return ret;
-
-             buff[i] = ret;
-     }
-
-     return 0;
-}
-
-static int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8

Quoted 1 line

module_id, - u8 opcode, u16 size, u8

*message)

Quoted 30 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -25

-{
-     u8 header[4];
-     int ret, i;
-
-     header[0] = opcode;
-     header[1] = module_id;
-     put_unaligned_be16(size, header + 2);
-
-     for (i = 0; i < sizeof(header); i++) {
-             ret = cdns_mhdp_mailbox_write(mhdp, header[i]);
-             if (ret)
-                     return ret;
-     }
-
-     for (i = 0; i < size; i++) {
-             ret = cdns_mhdp_mailbox_write(mhdp, message[i]);
-             if (ret)
-                     return ret;
-     }
-
-     return 0;
-}
-
-static
-int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr, u32

*value) -{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -4

-     u8 msg[4], resp[8];
-     int ret;
-
-     put_unaligned_be32(addr, msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-
-     mutex_lock(&mhdp->mbox_mutex);
-
-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL,
-                                  GENERAL_REGISTER_READ,
-                                  sizeof(msg), msg);
-     if (ret)
-             goto out;
-
-     ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_GENERAL,

Quoted 1 line

-

GENERAL_REGISTER_READ,

Quoted 29 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -28

-                                         sizeof(resp));
-     if (ret)
-             goto out;
-
-     ret = cdns_mhdp_mailbox_recv_data(mhdp, resp, sizeof(resp));
-     if (ret)
-             goto out;
-
-     /* Returned address value should be the same as requested */
-     if (memcmp(msg, resp, sizeof(msg))) {
-             ret = -EINVAL;
-             goto out;
-     }
-
-     *value = get_unaligned_be32(resp + 4);
-
-out:
-     mutex_unlock(&mhdp->mbox_mutex);
-     if (ret) {
-             dev_err(mhdp->dev, "Failed to read register\n");
-             *value = 0;
-     }
-
-     return ret;
-}
-
-static
-int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u16 addr, u32

val) -{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-     u8 msg[6];
-     int ret;
-
-     put_unaligned_be16(addr, msg);
-     put_unaligned_be32(val, msg + 2);
-
-     mutex_lock(&mhdp->mbox_mutex);
-
-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
-                                  DPTX_WRITE_REGISTER,

sizeof(msg),
msg);

Quoted 12 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -11

-
-     mutex_unlock(&mhdp->mbox_mutex);
-
-     return ret;
-}
-
 static
-int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr,
-                         u8 start_bit, u8 bits_no, u32 val)
-{
-     u8 field[8];
-     int ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-
-     put_unaligned_be16(addr, field);
-     field[2] = start_bit;
-     field[3] = bits_no;
-     put_unaligned_be32(val, field + 4);
-
-     mutex_lock(&mhdp->mbox_mutex);
-
-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
-                                  DPTX_WRITE_FIELD,

sizeof(field),
field);

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-
-     mutex_unlock(&mhdp->mbox_mutex);
-
-     return ret;
-}
-
-static
-int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
-                     u32 addr, u8 *data, u16 len)
-{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-     u8 msg[5], reg[5];
-     int ret;
-
-     put_unaligned_be16(len, msg);
-     put_unaligned_be24(addr, msg + 2);
-
-     mutex_lock(&mhdp->mbox_mutex);
-
-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
-                                  DPTX_READ_DPCD, sizeof(msg),

msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -4

-     if (ret)
-             goto out;
-
-     ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_DP_TX,

Quoted 19 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -19

-                                         DPTX_READ_DPCD,
-                                         sizeof(reg) + len);
-     if (ret)
-             goto out;
-
-     ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
-     if (ret)
-             goto out;
-
-     ret = cdns_mhdp_mailbox_recv_data(mhdp, data, len);
-
-out:
-     mutex_unlock(&mhdp->mbox_mutex);
-
-     return ret;
-}
-
-static
-int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8

Quoted 2 lines

value)
+int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp,

bool

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 13 lines

enable) {

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -7

-     u8 msg[6], reg[5];
+     u8 status;
      int ret;
 
-     put_unaligned_be16(1, msg);
-     put_unaligned_be24(addr, msg + 2);
-     msg[5] = value;
-
      mutex_lock(&mhdp->mbox_mutex);
 
-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
-                                  DPTX_WRITE_DPCD,

sizeof(msg),
msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -4

-     if (ret)
-             goto out;
-
-     ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_DP_TX,

Quoted 1 line

- DPTX_WRITE_DPCD,

sizeof(reg));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge) · line 84

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -2

-     if (ret)
-             goto out;
+     status = enable ? FW_ACTIVE : FW_STANDBY;

Initialising status can be done outside of the locked mutex.

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+     ret = cdns_mhdp_mailbox_send(&mhdp->base,

MB_MODULE_ID_GENERAL,

Quoted 1 line

+ GENERAL_MAIN_CONTROL,

sizeof(status), &status);

Quoted 6 lines

      if (ret)
              goto out;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -3

-     if (addr != get_unaligned_be24(reg + 2))
-             ret = -EINVAL;
-

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-out:
-     mutex_unlock(&mhdp->mbox_mutex);
-
-     if (ret)
-             dev_err(mhdp->dev, "dpcd write failed: %d\n", ret);
-     return ret;
-}
-
-static
-int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp,

bool

Quoted 11 lines

enable) -{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -10

-     u8 msg[5];
-     int ret, i;
-
-     msg[0] = GENERAL_MAIN_CONTROL;
-     msg[1] = MB_MODULE_ID_GENERAL;
-     msg[2] = 0;
-     msg[3] = 1;
-     msg[4] = enable ? FW_ACTIVE : FW_STANDBY;
-
-     mutex_lock(&mhdp->mbox_mutex);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -9

-
-     for (i = 0; i < sizeof(msg); i++) {
-             ret = cdns_mhdp_mailbox_write(mhdp, msg[i]);
-             if (ret)
-                     goto out;
-     }
-
-     /* read the firmware state */
-     ret = cdns_mhdp_mailbox_recv_data(mhdp, msg, sizeof(msg));
+     ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,

MB_MODULE_ID_GENERAL,

Quoted 1 line

+

GENERAL_MAIN_CONTROL,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -1

+                                         sizeof(status));
      if (ret)
              goto out;
 
-     ret = 0;
+     ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, &status,

sizeof(status));

Quoted 3 lines

out:

      mutex_unlock(&mhdp->mbox_mutex); @@ -382,18 +112,18 @@

int

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 7 lines

cdns_mhdp_get_hpd_status(struct cdns_mhdp_device
*mhdp)

      mutex_lock(&mhdp->mbox_mutex);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
+     ret = cdns_mhdp_mailbox_send(&mhdp->base,

MB_MODULE_ID_DP_TX,

Quoted 5 lines

                                   DPTX_HPD_STATE, 0, NULL);
      if (ret)
              goto err_get_hpd;

- ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_get_hpd_status(struct cdns_mhdp_device *mhdp)

Quoted 9 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +3 -1

+     ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
+ MB_MODULE_ID_DP_TX,
                                          DPTX_HPD_STATE,
                                          sizeof(status));
      if (ret)
              goto err_get_hpd;
 
-     ret = cdns_mhdp_mailbox_recv_data(mhdp, &status, sizeof(status));
+     ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, &status,

sizeof(status));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_get_edid_block(void *data, u8

Quoted 4 lines

      if (ret)
              goto err_get_hpd;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -424,22 +154,22 @@ int cdns_mhdp_get_edid_block(void *data, u8

*edid,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_get_edid_block(void *data, u8 *edid,

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

              msg[0] = block / 2;
              msg[1] = block % 2;
 
-             ret = cdns_mhdp_mailbox_send(mhdp,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_get_edid_block(void *data, u8 · line 157

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+             ret = cdns_mhdp_mailbox_send(&mhdp->base,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_get_edid_block(void *data, u8 *edid, · line 163

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

                                           DPTX_GET_EDID,

sizeof(msg), msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_get_edid_block(void *data, u8 *edid,

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

              if (ret)
                      continue;
 
-             ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_get_edid_block(void *data, u8 · line 162

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+             ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,

MB_MODULE_ID_DP_TX,

Quoted 1 line

DPTX_GET_EDID,

Quoted 1 line

sizeof(reg) +

length);

Quoted 4 lines

              if (ret)
                      continue;

- ret = cdns_mhdp_mailbox_recv_data(mhdp, reg,

sizeof(reg));

Quoted 1 line

+ ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, reg,

sizeof(reg));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 5 lines

              if (ret)
                      continue;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-             ret = cdns_mhdp_mailbox_recv_data(mhdp, edid, length);
+             ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, edid,

length);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 11 lines

              if (ret)
                      continue;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -464,17 +194,17 @@ int cdns_mhdp_read_hpd_event(struct

cdns_mhdp_device
*mhdp)

      mutex_lock(&mhdp->mbox_mutex);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
+     ret = cdns_mhdp_mailbox_send(&mhdp->base,

MB_MODULE_ID_DP_TX,

Quoted 5 lines

                                   DPTX_READ_EVENT, 0, NULL);
      if (ret)
              goto out;

- ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_DP_TX,

Quoted 3 lines

+ ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
+ MB_MODULE_ID_DP_TX,
DPTX_READ_EVENT,

sizeof(event));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 5 lines

      if (ret < 0)
              goto out;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     ret = cdns_mhdp_mailbox_recv_data(mhdp, &event, sizeof(event));
+     ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, &event,

sizeof(event));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_adjust_lt(struct

Quoted 4 lines

out:

      mutex_unlock(&mhdp->mbox_mutex);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -512,20 +242,20 @@ int cdns_mhdp_adjust_lt(struct

cdns_mhdp_device

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge)

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

 *mhdp, unsigned int nlanes,
 
      mutex_lock(&mhdp->mbox_mutex);
 
-     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
+     ret = cdns_mhdp_mailbox_send(&mhdp->base,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_adjust_lt(struct cdns_mhdp_device *mhdp, unsigned int nlanes,

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

                                   DPTX_ADJUST_LT,
                                   sizeof(payload), payload);
      if (ret)
              goto out;
 
      /* Yes, read the DPCD read command response */
-     ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c int cdns_mhdp_adjust_lt(struct · line 256

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -0

+     ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
+ MB_MODULE_ID_DP_TX,
                                          DPTX_READ_DPCD,
                                          sizeof(hdr) +

DP_LINK_STATUS_SIZE);

Quoted 19 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +3 -2

      if (ret)
              goto out;
 
-     ret = cdns_mhdp_mailbox_recv_data(mhdp, hdr, sizeof(hdr));
+     ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, hdr,
+ sizeof(hdr));
      if (ret)
              goto out;

@@ -533,7 +263,7 @@ int cdns_mhdp_adjust_lt(struct cdns_mhdp_device
 *mhdp, unsigned int nlanes, if (addr != DP_LANE0_1_STATUS)
              goto out;
 
-     ret = cdns_mhdp_mailbox_recv_data(mhdp, link_status,
+     ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, link_status,
                                        DP_LINK_STATUS_SIZE);
 
 out:

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static ssize_t cdns_mhdp_transfer(struct · line 581

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

@@ -847,7 +577,7 @@ static ssize_t cdns_mhdp_transfer(struct
 drm_dp_aux *aux, unsigned int i;
 
              for (i = 0; i < msg->size; ++i) {
-                     ret = cdns_mhdp_dpcd_write(mhdp,
+                     ret = cdns_mhdp_dpcd_write(&mhdp->base,
                                                 msg->address

+
i, buf[i]);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static ssize_t cdns_mhdp_transfer(struct · line 583

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

                      if (!ret)
                              continue; @@ -859,7 +589,7 @@

static

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 5 lines

ssize_t cdns_mhdp_transfer(struct drm_dp_aux *aux, return ret;
              }
      } else {

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-             ret = cdns_mhdp_dpcd_read(mhdp, msg->address,
+             ret = cdns_mhdp_dpcd_read(&mhdp->base,

msg->address,

Quoted 3 lines

                                        msg->buffer, msg->size);
              if (ret) {
                      dev_err(mhdp->dev, @@ -887,12 +617,12 @@

static

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 6 lines

int cdns_mhdp_link_training_init(struct cdns_mhdp_device *mhdp) if (!mhdp->host.scrambler)

              reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,

reg32);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static int cdns_mhdp_link_training_init(struct cdns_mhdp_device *mhdp)

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DP_ENHNCD,
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_ENHNCD,
                          mhdp->sink.enhanced &

mhdp->host.enhanced);

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DP_LANE_EN,
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_LANE_EN,
                          CDNS_DP_LANE_EN_LANES(mhdp-

link.num_lanes));

      cdns_mhdp_link_configure(&mhdp->aux, &mhdp->link); @@ -913,7
+643,7 @@ static int cdns_mhdp_link_training_init(struct
cdns_mhdp_device *mhdp) return ret;
      }

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static int cdns_mhdp_link_training_init(struct cdns_mhdp_device *mhdp)

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG,
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,
                          CDNS_PHY_COMMON_CONFIG |
                          CDNS_PHY_TRAINING_EN |
                          CDNS_PHY_TRAINING_TYPE(1) | @@

-1058,7

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 6 lines

+788,7 @@ static bool cdns_mhdp_link_training_channel_eq(struct

cdns_mhdp_device *mhdp, CDNS_PHY_TRAINING_TYPE(eq_tps);
      if (eq_tps != 4)
              reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,

reg32);

Quoted 3 lines

      drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,
                         (eq_tps != 4) ? eq_tps |

DP_LINK_SCRAMBLING_DISABLE :

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -1322,7 +1052,7 @@ static int cdns_mhdp_link_training(struct

cdns_mhdp_device *mhdp, mhdp->host.scrambler ? 0 :

                         DP_LINK_SCRAMBLING_DISABLE);

- ret = cdns_mhdp_reg_read(mhdp,

CDNS_DP_FRAMER_GLOBAL_CONFIG,
&reg32);

Quoted 5 lines

+ ret = cdns_mhdp_reg_read(&mhdp->base,
+ CDNS_DP_FRAMER_GLOBAL_CONFIG,
&reg32); if (ret < 0) {
dev_err(mhdp->dev,
"Failed to read

CDNS_DP_FRAMER_GLOBAL_CONFIG
%d\n",

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -1333,13 +1063,13 @@ static int cdns_mhdp_link_training(struct

cdns_mhdp_device *mhdp, reg32 |=

CDNS_DP_NUM_LANES(mhdp->link.num_lanes);

Quoted 3 lines

      reg32 |= CDNS_DP_WR_FAILING_EDGE_VSYNC;
      reg32 |= CDNS_DP_FRAMER_EN;

- cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,

reg32);

Quoted 1 line

+ cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_FRAMER_GLOBAL_CONFIG,
reg32);

Quoted 3 lines

/* Reset PHY config */
reg32 = CDNS_PHY_COMMON_CONFIG |

CDNS_PHY_TRAINING_TYPE(1);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 4 lines

      if (!mhdp->host.scrambler)
              reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,

reg32);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 10 lines

      return 0;

err:

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -1347,7 +1077,7 @@ static int cdns_mhdp_link_training(struct

cdns_mhdp_device *mhdp, reg32 = CDNS_PHY_COMMON_CONFIG |

CDNS_PHY_TRAINING_TYPE(1);
      if (!mhdp->host.scrambler)
              reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,

reg32);

Quoted 3 lines

      drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,
                         DP_TRAINING_PATTERN_DISABLE); @@

-1461,7

Quoted 5 lines

+1191,7 @@ static int cdns_mhdp_link_up(struct cdns_mhdp_device *mhdp) mhdp->link.num_lanes = cdns_mhdp_max_num_lanes(mhdp);

      /* Disable framer for link training */

- err = cdns_mhdp_reg_read(mhdp,

CDNS_DP_FRAMER_GLOBAL_CONFIG, &resp);

Quoted 5 lines

+ err = cdns_mhdp_reg_read(&mhdp->base,
+ CDNS_DP_FRAMER_GLOBAL_CONFIG,
&resp); if (err < 0) {
dev_err(mhdp->dev,
"Failed to read

CDNS_DP_FRAMER_GLOBAL_CONFIG
%d\n",

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -1470,7 +1200,7 @@ static int cdns_mhdp_link_up(struct

cdns_mhdp_device
*mhdp) }

      resp &= ~CDNS_DP_FRAMER_EN;

- cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,

resp);

Quoted 1 line

+ cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_FRAMER_GLOBAL_CONFIG,
resp);

Quoted 3 lines

/* Spread AMP if required, enable 8b/10b coding */ amp[0] = cdns_mhdp_get_ssc_supported(mhdp) ?

DP_SPREAD_AMP_0_5 :

Quoted 2 lines

0; @@ -1837,7 +1567,7 @@ static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp, if (mode->flags &

DRM_MODE_FLAG_INTERLACE)

Quoted 1 line

              bnd_hsync2vsync |=

CDNS_IP_DET_INTERLACE_FORMAT;

Quoted 2 lines

- cdns_mhdp_reg_write(mhdp,

CDNS_BND_HSYNC2VSYNC(stream_id),

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -0

+     cdns_mhdp_reg_write(&mhdp->base,
+ CDNS_BND_HSYNC2VSYNC(stream_id),
                          bnd_hsync2vsync);
 
      hsync2vsync_pol_ctrl = 0;

@@ -1845,10 +1575,10 @@ static void cdns_mhdp_configure_video(struct

cdns_mhdp_device *mhdp, hsync2vsync_pol_ctrl |=

CDNS_H2V_HSYNC_POL_ACTIVE_LOW;
      if (mode->flags & DRM_MODE_FLAG_NVSYNC)
              hsync2vsync_pol_ctrl |=

CDNS_H2V_VSYNC_POL_ACTIVE_LOW;

Quoted 1 line

- cdns_mhdp_reg_write(mhdp,

CDNS_HSYNC2VSYNC_POL_CTRL(stream_id),

Quoted 1 line

+ cdns_mhdp_reg_write(&mhdp->base,

CDNS_HSYNC2VSYNC_POL_CTRL(stream_id),

Quoted 3 lines

                          hsync2vsync_pol_ctrl);

- cdns_mhdp_reg_write(mhdp,

CDNS_DP_FRAMER_PXL_REPR(stream_id),
pxl_repr);

Quoted 6 lines

+ cdns_mhdp_reg_write(&mhdp->base,
+ CDNS_DP_FRAMER_PXL_REPR(stream_id),
pxl_repr);

      if (mode->flags & DRM_MODE_FLAG_INTERLACE)
              dp_framer_sp |= CDNS_DP_FRAMER_INTERLACE; @@

-1856,19

Quoted 2 lines

+1586,19 @@ static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp, dp_framer_sp |=

CDNS_DP_FRAMER_HSYNC_POL_LOW;

Quoted 3 lines

      if (mode->flags & DRM_MODE_FLAG_NVSYNC)
              dp_framer_sp |= CDNS_DP_FRAMER_VSYNC_POL_LOW;

- cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_SP(stream_id),

dp_framer_sp);

Quoted 1 line

+ cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_FRAMER_SP(stream_id),

Quoted 5 lines

dp_framer_sp);

      front_porch = mode->crtc_hsync_start - mode->crtc_hdisplay;
      back_porch = mode->crtc_htotal - mode->crtc_hsync_end;

- cdns_mhdp_reg_write(mhdp,

CDNS_DP_FRONT_BACK_PORCH(stream_id),

Quoted 1 line

+ cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_FRONT_BACK_PORCH(stream_id),

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 5 lines

                          CDNS_DP_FRONT_PORCH(front_porch) |
                          CDNS_DP_BACK_PORCH(back_porch));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DP_BYTE_COUNT(stream_id),
+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_BYTE_COUNT(stream_id),

Quoted 4 lines

                          mode->crtc_hdisplay * bpp / 8);

      msa_h0 = mode->crtc_htotal - mode->crtc_hsync_start;

- cdns_mhdp_reg_write(mhdp,

CDNS_DP_MSA_HORIZONTAL_0(stream_id),

Quoted 1 line

+ cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_MSA_HORIZONTAL_0(stream_id),

Quoted 1 line

CDNS_DP_MSAH0_H_TOTAL(mode->crtc_htotal) |

Quoted 1 line

CDNS_DP_MSAH0_HSYNC_START(msa_h0));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1607

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -1877,11 +1607,11 @@ static void cdns_mhdp_configure_video(struct
 cdns_mhdp_device *mhdp,

CDNS_DP_MSAH1_HDISP_WIDTH(mode->crtc_hdisplay);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1609

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

      if (mode->flags & DRM_MODE_FLAG_NHSYNC)
              msa_horizontal_1 |=

CDNS_DP_MSAH1_HSYNC_POL_LOW;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1880

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

-     cdns_mhdp_reg_write(mhdp,

CDNS_DP_MSA_HORIZONTAL_1(stream_id),

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1610

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_MSA_HORIZONTAL_1(stream_id),

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

                          msa_horizontal_1);
 
      msa_v0 = mode->crtc_vtotal - mode->crtc_vsync_start;
-     cdns_mhdp_reg_write(mhdp,

CDNS_DP_MSA_VERTICAL_0(stream_id),

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1616

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -0

+     cdns_mhdp_reg_write(&mhdp->base,
+ CDNS_DP_MSA_VERTICAL_0(stream_id),
 

CDNS_DP_MSAV0_V_TOTAL(mode->crtc_vtotal) |

Quoted 1 line

CDNS_DP_MSAV0_VSYNC_START(msa_v0));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1620

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

@@ -1890,7 +1620,7 @@ static void cdns_mhdp_configure_video(struct
 cdns_mhdp_device *mhdp,

CDNS_DP_MSAV1_VDISP_WIDTH(mode->crtc_vdisplay);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

      if (mode->flags & DRM_MODE_FLAG_NVSYNC)
              msa_vertical_1 |= CDNS_DP_MSAV1_VSYNC_POL_LOW;
-     cdns_mhdp_reg_write(mhdp,

CDNS_DP_MSA_VERTICAL_1(stream_id),

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -0

+     cdns_mhdp_reg_write(&mhdp->base,
+ CDNS_DP_MSA_VERTICAL_1(stream_id),
                          msa_vertical_1);
 
      if ((mode->flags & DRM_MODE_FLAG_INTERLACE) && @@

-1902,14

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 6 lines

+1632,14 @@ static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp, if (pxlfmt == DRM_COLOR_FORMAT_YCBCR420)

              misc1 = CDNS_DP_TEST_VSC_SDP;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DP_MSA_MISC(stream_id),
+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_MSA_MISC(stream_id),

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 4 lines

                          misc0 | (misc1 << 8));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DP_HORIZONTAL(stream_id),
+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_HORIZONTAL(stream_id),

Quoted 2 lines

CDNS_DP_H_HSYNC_WIDTH(hsync) |

CDNS_DP_H_H_TOTAL(mode->crtc_hdisplay));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DP_VERTICAL_0(stream_id),
+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_VERTICAL_0(stream_id),

Quoted 1 line

CDNS_DP_V0_VHEIGHT(mode->crtc_vdisplay) |

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1921

Quoted 7 lines

                          CDNS_DP_V0_VSTART(msa_v0));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

@@ -1918,13 +1648,13 @@ static void cdns_mhdp_configure_video(struct
 cdns_mhdp_device *mhdp, mode->crtc_vtotal % 2 == 0)
              dp_vertical_1 |= CDNS_DP_V1_VTOTAL_EVEN;
 
-     cdns_mhdp_reg_write(mhdp, CDNS_DP_VERTICAL_1(stream_id),

dp_vertical_1);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1651

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_VERTICAL_1(stream_id),

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -2

 dp_vertical_1);
 
-     cdns_mhdp_reg_write_bit(mhdp, CDNS_DP_VB_ID(stream_id), 2, 1,
-                             (mode->flags &

DRM_MODE_FLAG_INTERLACE) ?

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1655

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -1

-                             CDNS_DP_VB_ID_INTERLACED : 0);
+     cdns_mhdp_dp_reg_write_bit(&mhdp->base,
+ CDNS_DP_VB_ID(stream_id), 2,

1,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1656

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+                                (mode->flags &

DRM_MODE_FLAG_INTERLACE) ?

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1657

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+                                CDNS_DP_VB_ID_INTERLACED :

0);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1927

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

-     ret = cdns_mhdp_reg_read(mhdp,

CDNS_DP_FRAMER_GLOBAL_CONFIG,
&framer);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -0

+     ret = cdns_mhdp_reg_read(&mhdp->base,
+ CDNS_DP_FRAMER_GLOBAL_CONFIG,
 &framer); if (ret < 0) {
              dev_err(mhdp->dev,
                      "Failed to read

CDNS_DP_FRAMER_GLOBAL_CONFIG
%d\n",

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1936

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

@@ -1933,7 +1663,7 @@ static void cdns_mhdp_configure_video(struct
 cdns_mhdp_device *mhdp, }
      framer |= CDNS_DP_FRAMER_EN;
      framer &= ~CDNS_DP_NO_VIDEO_MODE;
-     cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,

framer);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_configure_video(struct · line 1666

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_FRAMER_GLOBAL_CONFIG,
framer);

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

 }
 
 static void cdns_mhdp_sst_enable(struct cdns_mhdp_device *mhdp, @@
-1966,15 +1696,15 @@ static void cdns_mhdp_sst_enable(struct

cdns_mhdp_device *mhdp,

      mhdp->stream_id = 0;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

-     cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_TU,
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_FRAMER_TU,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_sst_enable(struct cdns_mhdp_device *mhdp,

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -2

                          CDNS_DP_FRAMER_TU_VS(vs) |
                          CDNS_DP_FRAMER_TU_SIZE(tu_size) |
                          CDNS_DP_FRAMER_TU_CNT_RST_EN);
 
-     cdns_mhdp_reg_write(mhdp, CDNS_DP_LINE_THRESH(0),
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_LINE_THRESH(0),
                          line_thresh & GENMASK(5, 0));
 
-     cdns_mhdp_reg_write(mhdp, CDNS_DP_STREAM_CONFIG_2(0),
+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_STREAM_CONFIG_2(0),

Quoted 1 line

                          CDNS_DP_SC2_TU_VS_DIFF((tu_size - vs >

3) ?

Quoted 1 line

                                                 0 : tu_size -

vs));

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_enable(struct · line 1742

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

@@ -2009,13 +1739,13 @@ static void cdns_mhdp_atomic_enable(struct
 drm_bridge *bridge, mhdp->info->ops->enable(mhdp);
 
      /* Enable VIF clock for stream 0 */
-     ret = cdns_mhdp_reg_read(mhdp, CDNS_DPTX_CAR, &resp);
+     ret = cdns_mhdp_reg_read(&mhdp->base, CDNS_DPTX_CAR,

&resp);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_enable(struct · line 1744

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

      if (ret < 0) {
              dev_err(mhdp->dev, "Failed to read

CDNS_DPTX_CAR %d\n",
ret);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_enable(struct drm_bridge *bridge,

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -1

              goto out;
      }
 
-     cdns_mhdp_reg_write(mhdp, CDNS_DPTX_CAR,
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_CAR,
                          resp | CDNS_VIF_CLK_EN |

CDNS_VIF_CLK_RSTN);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_disable(struct · line 2086

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

      connector = drm_atomic_get_new_connector_for_encoder(state,

@@ -2083,16 +1813,16 @@ static void cdns_mhdp_atomic_disable(struct
 drm_bridge *bridge, cdns_mhdp_hdcp_disable(mhdp);
 
      mhdp->bridge_enabled = false;
-     cdns_mhdp_reg_read(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,

&resp);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_disable(struct · line 1816

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+     cdns_mhdp_reg_read(&mhdp->base,

CDNS_DP_FRAMER_GLOBAL_CONFIG,
&resp);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_disable(struct drm_bridge *bridge,

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -1

      resp &= ~CDNS_DP_FRAMER_EN;
      resp |= CDNS_DP_NO_VIDEO_MODE;
-     cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,

resp);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_disable(struct · line 1819

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +1 -0

+     cdns_mhdp_reg_write(&mhdp->base,

CDNS_DP_FRAMER_GLOBAL_CONFIG,
resp);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c static void cdns_mhdp_atomic_disable(struct drm_bridge *bridge,

Quoted 9 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +2 -2

      cdns_mhdp_link_down(mhdp);
 
      /* Disable VIF clock for stream 0 */
-     cdns_mhdp_reg_read(mhdp, CDNS_DPTX_CAR, &resp);
-     cdns_mhdp_reg_write(mhdp, CDNS_DPTX_CAR,
+     cdns_mhdp_reg_read(&mhdp->base, CDNS_DPTX_CAR, &resp);
+     cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_CAR,
                          resp & ~(CDNS_VIF_CLK_EN |

CDNS_VIF_CLK_RSTN));

Quoted 39 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +0 -0

      if (mhdp->info && mhdp->info->ops && mhdp->info->ops->disable)

@@ -2502,6 +2232,11 @@ static int cdns_mhdp_probe(struct

platform_device
*pdev)

      platform_set_drvdata(pdev, mhdp);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +5 -0

+     /* init base struct for access mailbox  */
+     mhdp->base.dev = mhdp->dev;
+     mhdp->base.regs = mhdp->regs;
+     mhdp->base.mbox_mutex = &mhdp->mbox_mutex;
+
      mhdp->info = of_device_get_match_data(dev);
 
      clk_prepare_enable(clk);

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h index bad2fc0c73066..f08db38c82bbd 100644

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +1 -0

@@ -15,6 +15,7 @@
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 
+#include <drm/bridge/cdns-mhdp-helper.h>
 #include <drm/display/drm_dp_helper.h>  #include <drm/drm_bridge.h>
 #include <drm/drm_connector.h> @@ -27,10 +28,6 @@ struct phy;
 #define CDNS_APB_CTRL                                0x00000

#define CDNS_CPU_STALL BIT(3)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +0 -4

-#define CDNS_MAILBOX_FULL                    0x00008
-#define CDNS_MAILBOX_EMPTY                   0x0000c
-#define CDNS_MAILBOX_TX_DATA                 0x00010
-#define CDNS_MAILBOX_RX_DATA                 0x00014
 #define CDNS_KEEP_ALIVE                              0x00018
 #define CDNS_KEEP_ALIVE_MASK                 GENMASK(7, 0)

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h struct phy; · line 195

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +0 -0

@@ -198,45 +195,10 @@ struct phy;
 #define CDNS_DP_BYTE_COUNT(s)

(CDNS_DPTX_STREAM(s) + 0x7c)

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +0 -9

 #define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT      16
 
-/* mailbox */
-#define MAILBOX_RETRY_US                     1000
-#define MAILBOX_TIMEOUT_US                   2000000
-
-#define MB_OPCODE_ID                         0
-#define MB_MODULE_ID                         1
-#define MB_SIZE_MSB_ID                               2
-#define MB_SIZE_LSB_ID                               3
-#define MB_DATA_ID                           4

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h struct phy;

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +1 -8

-
-#define MB_MODULE_ID_DP_TX                   0x01
-#define MB_MODULE_ID_HDCP_TX                 0x07
-#define MB_MODULE_ID_HDCP_RX                 0x08
-#define MB_MODULE_ID_HDCP_GENERAL            0x09
-#define MB_MODULE_ID_GENERAL                 0x0a
-
-/* firmware and opcodes */
+/* firmware */
 #define FW_NAME

"cadence/
mhdp8546.bin"

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h struct phy; · line 200

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +0 -0

 #define CDNS_MHDP_IMEM

0x10000

Quoted 102 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +2 -19

-#define GENERAL_MAIN_CONTROL                 0x01
-#define GENERAL_TEST_ECHO                    0x02
-#define GENERAL_BUS_SETTINGS                 0x03
-#define GENERAL_TEST_ACCESS                  0x04
-#define GENERAL_REGISTER_READ                        0x07
-
-#define DPTX_SET_POWER_MNG                   0x00
-#define DPTX_GET_EDID                                0x02
-#define DPTX_READ_DPCD                               0x03
-#define DPTX_WRITE_DPCD                              0x04
-#define DPTX_ENABLE_EVENT                    0x05
-#define DPTX_WRITE_REGISTER                  0x06
-#define DPTX_READ_REGISTER                   0x07
-#define DPTX_WRITE_FIELD                     0x08
-#define DPTX_READ_EVENT                              0x0a
-#define DPTX_GET_LAST_AUX_STAUS                      0x0e
-#define DPTX_HPD_STATE                               0x11
-#define DPTX_ADJUST_LT                               0x12
-
 #define FW_STANDBY                           0
 #define FW_ACTIVE                            1
 

@@ -352,6 +314,8 @@ struct cdns_mhdp_hdcp {  };
 
 struct cdns_mhdp_device {
+     struct cdns_mhdp_base base;
+
      void __iomem *regs;
      void __iomem *sapb_regs;
      void __iomem *j721e_regs;

(quoted diff) +0 -0

b/include/drm/bridge/cdns-mhdp-helper.h new file mode 100644 index 0000000000000..477e67601ee5f

include/drm/bridge/cdns-mhdp-helper.h new file +65 -0

@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023 NXP Semiconductor, Inc.
+ */
+#ifndef __CDNS_MHDP_HELPER_H__
+#define __CDNS_MHDP_HELPER_H__
+
+#include <asm/unaligned.h>
+#include <linux/iopoll.h>
+
+/* mailbox regs offset */
+#define CDNS_MAILBOX_FULL                    0x00008
+#define CDNS_MAILBOX_EMPTY                   0x0000c
+#define CDNS_MAILBOX_TX_DATA                 0x00010
+#define CDNS_MAILBOX_RX_DATA                 0x00014
+
+#define MAILBOX_RETRY_US                     1000
+#define MAILBOX_TIMEOUT_US                   2000000
+
+/* Module ID Code */
+#define MB_MODULE_ID_DP_TX                   0x01
+#define MB_MODULE_ID_HDMI_TX                 0x03
+#define MB_MODULE_ID_HDCP_TX                 0x07
+#define MB_MODULE_ID_HDCP_RX                 0x08
+#define MB_MODULE_ID_HDCP_GENERAL            0x09
+#define MB_MODULE_ID_GENERAL                 0x0A
+
+/* General Commands */
+#define GENERAL_MAIN_CONTROL                 0x01
+#define GENERAL_TEST_ECHO                    0x02
+#define GENERAL_BUS_SETTINGS                 0x03
+#define GENERAL_TEST_ACCESS                  0x04
+#define GENERAL_REGISTER_WRITE                       0x05
+#define GENERAL_WRITE_FIELD                  0x06
+#define GENERAL_REGISTER_READ                        0x07
+#define GENERAL_GET_HPD_STATE                        0x11
+
+/* DPTX Commands */
+#define DPTX_SET_POWER_MNG                   0x00
+#define DPTX_SET_HOST_CAPABILITIES           0x01
+#define DPTX_GET_EDID                                0x02
+#define DPTX_READ_DPCD                               0x03
+#define DPTX_WRITE_DPCD                              0x04
+#define DPTX_ENABLE_EVENT                    0x05
+#define DPTX_WRITE_REGISTER                  0x06
+#define DPTX_READ_REGISTER                   0x07
+#define DPTX_WRITE_FIELD                     0x08
+#define DPTX_TRAINING_CONTROL                        0x09
+#define DPTX_READ_EVENT                              0x0a
+#define DPTX_READ_LINK_STAT                  0x0b
+#define DPTX_SET_VIDEO                               0x0c
+#define DPTX_SET_AUDIO                               0x0d
+#define DPTX_GET_LAST_AUX_STAUS                      0x0e
+#define DPTX_SET_LINK_BREAK_POINT            0x0f
+#define DPTX_FORCE_LANES                     0x10
+#define DPTX_HPD_STATE                               0x11
+#define DPTX_ADJUST_LT                               0x12
+
+/* HDMI TX Commands */
+#define HDMI_TX_READ                         0x00
+#define HDMI_TX_WRITE                                0x01
+#define HDMI_TX_UPDATE_READ                  0x02
+#define HDMI_TX_EDID                         0x03
+#define HDMI_TX_EVENTS                               0x04
+#define HDMI_TX_HPD_STATUS                   0x05

include/drm/bridge/cdns-mhdp-helper.h line 75

Quoted 10 lines

include/drm/bridge/cdns-mhdp-helper.h new file +10 -0

+
+struct cdns_mhdp_base {
+     struct device *dev;
+     void __iomem *regs;
+     /* protect mailbox communications with the firmware */
+     struct mutex *mbox_mutex;
+};
+
+/* Mailbox helper functions */
+int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, u8

module_id,