Initial support for Cadence MHDP8501(HDMI/DP) for i.MX8MQ

Add bindings for Cadence MHDP8501 DisplayPort and HDMI driver.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp8501.yaml         | 105 ++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file mode 100644
index 000000000000..a54756815e6f

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +48 -0

@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8501.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP8501 Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP8501 Displayport/HDMI TX interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp8501-dp
+      - cdns,mhdp8501-hdmi
+      - fsl,imx8mq-mhdp8501-dp
+      - fsl,imx8mq-mhdp8501-hdmi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: MHDP8501 DP/HDMI APB clock.
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +47 -0

+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+  - phys
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mhdp_dp: dp-bridge@32c00000 {
+        compatible = "fsl,imx8mq-mhdp8501-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+        phys = <&dp_phy>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mhdp_in: endpoint {
+                    remote-endpoint = <&dcss_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                mhdp_out: endpoint {
+                    remote-endpoint = <&dp_con>;
+                };
+            };
+        };
+    };

-----Original Message-----
From: Alexander Stein <[email protected]>
Sent: 2023年6月16日 17:32
To: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Oliver Brown <[email protected]>; Sandor Yu <[email protected]>; dl-linux-imx <[email protected]>; [email protected]; Sandor Yu <[email protected]>
Subject: [EXT] Re: [PATCH v6 2/8] dt-bindings: display: bridge: Add Cadence MHDP8501 HDMI and DP

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Hi Sandor,

Am Donnerstag, 15. Juni 2023, 03:38:12 CEST schrieb Sandor Yu:

Quoted 5 lines

Add bindings for Cadence MHDP8501 DisplayPort and HDMI driver.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp8501.yaml         | 105

++++++++++++++++++

Quoted 10 lines

 1 file changed, 105 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file mode 100644 index 000000000000..a54756815e6f
--- /dev/null
+++

b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.y

Review line 4

Quoted 7 lines

+++ aml

(quoted diff) +4 -0

@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
+---
+$id:
+http://devi/

+cetree.org%2Fschemas%2Fdisplay%2Fbridge%2Fcdns%2Cmhdp8501.yaml% 23&dat

Quoted 1 line

+a=05%7C01%7CSandor.yu%40nxp.com%7C6ef2c732b3674cb2896c08db6e4 c827b%7C

Quoted 1 line

+686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63822504710561225 8%7CUnkno

Quoted 1 line

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Quoted 1 line

+LCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=DGYYt2LQ%2FhlNBVd2m0s aXTm9IoKKwn

Review

Quoted 4 lines

(quoted diff) +3 -0

+X7CTTplhbLxcI%3D&reserved=0
+$schema:
+http://devi/

+cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7CSandor. yu%40n

Quoted 1 line

+xp.com%7C6ef2c732b3674cb2896c08db6e4c827b%7C686ea1d3bc2b4c6fa9 2cd99c5

Quoted 1 line

+c301635%7C0%7C0%7C638225047105612258%7CUnknown%7CTWFpbGZs b3d8eyJWIjoi

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+7C%7C&sdata=SkTFYM7HHgJmFUkyo3Ftf%2B8FdGqlnty0Ch6ggwSPeLY%3D &reserved

Quoted 49 lines

+=0

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +48 -0

+
+title: Cadence MHDP8501 Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP8501 Displayport/HDMI TX interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp8501-dp
+      - cdns,mhdp8501-hdmi
+      - fsl,imx8mq-mhdp8501-dp
+      - fsl,imx8mq-mhdp8501-hdmi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: MHDP8501 DP/HDMI APB clock.
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Input port from display controller output.
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 58

Quoted 5 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +5 -0

+          Output port to DP/HDMI connector.
+
+    required:
+      - port@0
+      - port@1

You mark these ports as required, but apparently the drivers do not use them, AFAICT. E.g. missing port@1 is not resulting in an error, at lease for HDMI one.

Best regards,
Alexander

Quoted 37 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +37 -0

+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+  - phys
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mhdp_dp: dp-bridge@32c00000 {
+        compatible = "fsl,imx8mq-mhdp8501-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+        phys = <&dp_phy>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mhdp_in: endpoint {
+                    remote-endpoint = <&dcss_out>;
+                };
+            };

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 105

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +10 -0

+
+            port@1 {
+                reg = <1>;
+
+                mhdp_out: endpoint {
+                    remote-endpoint = <&dp_con>;
+                };
+            };
+        };
+    };

--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq/
-group.com%2F&data=05%7C01%7CSandor.yu%40nxp.com%7C6ef2c732b367 4cb2896c08db6e4c827b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C 0%7C638225047105612258%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C %7C%7C&sdata=xJdLi2HJ72ShBwT%2FfUdZ3uLx%2FIJEPmTQJHGVXe0JVik%3 D&reserved=0

Hi Sandor,

Am Donnerstag, 15. Juni 2023, 03:38:12 CEST schrieb Sandor Yu:

Quoted 71 lines

Add bindings for Cadence MHDP8501 DisplayPort and HDMI driver.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp8501.yaml         | 105 ++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file mode 100644
index 000000000000..a54756815e6f

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +54 -0

@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8501.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP8501 Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP8501 Displayport/HDMI TX interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp8501-dp
+      - cdns,mhdp8501-hdmi
+      - fsl,imx8mq-mhdp8501-dp
+      - fsl,imx8mq-mhdp8501-hdmi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: MHDP8501 DP/HDMI APB clock.
+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Input port from display controller output.
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port to DP/HDMI connector.

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 58

Quoted 4 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +4 -0

+
+    required:
+      - port@0
+      - port@1

You mark these ports as required, but apparently the drivers do not use them, AFAICT. E.g. missing port@1 is not resulting in an error, at lease for HDMI one.

Add bindings for Cadence MHDP8501 DisplayPort and HDMI driver.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp8501.yaml         | 105 ++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +11 -0

new file mode 100644
index 000000000000..a54756815e6f
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8501.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP8501 Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +77 -0

+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Input port from display controller output.
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port to DP/HDMI connector.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+  - phys
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mhdp_dp: dp-bridge@32c00000 {
+        compatible = "fsl,imx8mq-mhdp8501-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+        phys = <&dp_phy>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mhdp_in: endpoint {
+                    remote-endpoint = <&dcss_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                mhdp_out: endpoint {
+                    remote-endpoint = <&dp_con>;
+                };
+            };
+        };
+    };

Signature · 1 line

2.34.1

-----Original Message-----
From: Rob Herring <[email protected]>
Sent: 2023年6月20日 23:49
To: Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v6 2/8] dt-bindings: display: bridge: Add Cadence MHDP8501 HDMI and DP

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Quoted 1 line · Sandor Yu

Add bindings for Cadence MHDP8501 DisplayPort and HDMI driver.

Bindings are for h/w, not a driver.

Quoted 5 lines

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp8501.yaml         | 105

++++++++++++++++++

Quoted 11 lines

 1 file changed, 105 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file mode 100644
index 000000000000..a54756815e6f
--- /dev/null
+++

b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.y

Review line 4

Quoted 7 lines

+++ aml

(quoted diff) +4 -0

@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
+---
+$id:
+https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi

+cetree.org%2Fschemas%2Fdisplay%2Fbridge%2Fcdns%2Cmhdp8501.yaml% 23&dat

Quoted 1 line

+a=05%7C01%7CSandor.yu%40nxp.com%7C4d4e118d60d744b5dba708db71 a5de79%7C

Quoted 1 line

+686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63822872943965530 2%7CUnkno

Quoted 1 line

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Quoted 1 line

+LCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=UEsMdkZBmfD7tM1wzJ71 DHQoi4zVOkpT

Review

Quoted 4 lines

(quoted diff) +3 -0

+A9TNE7Rxn%2B8%3D&reserved=0
+$schema:
+https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi

+cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7CSandor. yu%40n

Quoted 1 line

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Quoted 1 line

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Quoted 1 line

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Quoted 1 line

+7C%7C&sdata=Zu3v0yG2BXWXvTWV5oLiGvdu3O3PhK%2FrYNJIS2zHwpI%3 D&reserved

Quoted 13 lines

+=0

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +12 -0

+
+title: Cadence MHDP8501 Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP8501 Displayport/HDMI TX interface.
+
+properties:
+  compatible:
+    enum:

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 21

Quoted 4 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +4 -0

+      - cdns,mhdp8501-dp
+      - cdns,mhdp8501-hdmi
+      - fsl,imx8mq-mhdp8501-dp
+      - fsl,imx8mq-mhdp8501-hdmi

Is DP vs. HDMI fixed for a particular SoC implementation or it's a board level decision. In the latter case, the type of connector should determine the mode, not compatible.

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 28

Quoted 8 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +7 -0

+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: MHDP8501 DP/HDMI APB clock.

Seems odd there's no clock tied to the pixel/serdes clock.

Quoted 81 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +77 -1

+
+  phys:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Input port from display controller output.
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port to DP/HDMI connector.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+  - phys
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mhdp_dp: dp-bridge@32c00000 {
+        compatible = "fsl,imx8mq-mhdp8501-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+        phys = <&dp_phy>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mhdp_in: endpoint {
+                    remote-endpoint = <&dcss_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                mhdp_out: endpoint {
+                    remote-endpoint = <&dp_con>;
+                };
+            };
+        };
+    };
--

2.34.1

Quoted 4 lines

Quoted 4 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +4 -0

+
+properties:
+  compatible:
+    enum:

Quoted 8 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 21

Quoted 4 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +4 -0

+      - cdns,mhdp8501-dp
+      - cdns,mhdp8501-hdmi
+      - fsl,imx8mq-mhdp8501-dp
+      - fsl,imx8mq-mhdp8501-hdmi

Is DP vs. HDMI fixed for a particular SoC implementation or it's a board level decision. In the latter case, the type of connector should determine the mode, not compatible.

DP or HDMI is bord level decision.

Because DP and HDMI have different initialize process and less functions could be reuse, so they have different drivers.

Please check it in patch
[PATCH v6 3/8] drm: bridge: Cadence: Add MHDP8501 DP driver [PATCH v6 5/8] drm: bridge: Cadence: Add MHDP8501 HDMI driver

If use the type of connector to determine the mode, hdmi and DP driver have to combine into one driver. So the compatible may the better choice.

Add a new DRM DisplayPort bridge driver for Candence MHDP8501 used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SOC, the DisplayPort FW was loaded and activated by SOC ROM code. Bootload binary included HDMI FW was required for the driver.

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file +22 -0

+static const struct drm_connector_funcs cdns_dp_connector_funcs = {
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.destroy = drm_connector_cleanup,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_connector_helper_funcs cdns_dp_connector_helper_funcs = {
+	.get_modes = cdns_dp_connector_get_modes,
+};
+
+static int cdns_dp_bridge_attach(struct drm_bridge *bridge,
+				 enum drm_bridge_attach_flags flags)
+{
+	struct cdns_mhdp_device *mhdp = bridge->driver_private;
+	struct drm_encoder *encoder = bridge->encoder;
+	struct drm_connector *connector = &mhdp->connector;
+	int ret;
+
+	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+		connector->interlace_allowed = 0;

-----Original Message-----
From: Sam Ravnborg <[email protected]>
Sent: 2023年6月16日 0:33
To: Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Oliver Brown <[email protected]>; dl-linux-imx <[email protected]>; [email protected]
Subject: [EXT] Re: [PATCH v6 3/8] drm: bridge: Cadence: Add MHDP8501 DP driver

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Hi Sandor,

Quoted 5 lines · Sandor Yu

Add a new DRM DisplayPort bridge driver for Candence MHDP8501 used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SOC, the DisplayPort FW was loaded and activated by SOC

ROM

Quoted 1 line

code. Bootload binary included HDMI FW was required for the driver.

The bridge driver supports creating a connector, but is this really necessary?

This part:

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file +5 -0

+static const struct drm_connector_funcs cdns_dp_connector_funcs = {
+     .fill_modes = drm_helper_probe_single_connector_modes,
+     .destroy = drm_connector_cleanup,
+     .reset = drm_atomic_helper_connector_reset,
+     .atomic_duplicate_state =

drm_atomic_helper_connector_duplicate_state,

Review

Quoted 5 lines

(quoted diff) +5 -0

+     .atomic_destroy_state =
+drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_connector_helper_funcs

cdns_dp_connector_helper_funcs = {

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c line 724

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file +4 -0

+     .get_modes = cdns_dp_connector_get_modes, };
+
+static int cdns_dp_bridge_attach(struct drm_bridge *bridge,
+                              enum drm_bridge_attach_flags flags)

{

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file +4 -0

+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+     struct drm_encoder *encoder = bridge->encoder;
+     struct drm_connector *connector = &mhdp->connector;
+     int ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file +10 -0

+
+     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+             connector->interlace_allowed = 0;
+
+             connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+             drm_connector_helper_add(connector,
+ &cdns_dp_connector_helper_funcs);
+
+             drm_connector_init(bridge->dev, connector,

&cdns_dp_connector_funcs,

Quoted 1 line

+

DRM_MODE_CONNECTOR_DisplayPort);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c line 742

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file +3 -0

+
+             drm_connector_attach_encoder(connector, encoder);
+     }

Unless you have a display driver that do not create their own connector then drop the above and error out if DRM_BRIDGE_ATTACH_NO_CONNECTOR is not set.
It is encouraged that display drivers create their own connector.

This was the only detail I looked for in the driver, I hope some else volunteer to review it.

Sam

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
 include/linux/phy/phy-hdmi.h | 38 ++++++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h      |  7 ++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/phy/phy-hdmi.h

include/linux/phy/phy-hdmi.h new file +8 -0

new file mode 100644
index 000000000000..5765aa5bc175
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+

include/linux/phy/phy-hdmi.h new file +20 -0

+	HDMI_PHY_COLORSPACE_RESERVED4,
+	HDMI_PHY_COLORSPACE_RESERVED5,
+	HDMI_PHY_COLORSPACE_RESERVED6,
+};
+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:	Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+	unsigned int pixel_clk_rate;
+	unsigned int bpc;
+	enum hdmi_phy_colorspace color_space;
+};
+
+#endif /* __PHY_HDMI_H_ */

include/linux/phy/phy.h +6 -1

index 3a570bc59fc7..93d77d45b1d4 100644
@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-hdmi.h>
 #include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>
 

@@ -42,7 +43,8 @@ enum phy_mode {
 	PHY_MODE_MIPI_DPHY,
 	PHY_MODE_SATA,
 	PHY_MODE_LVDS,
-	PHY_MODE_DP
+	PHY_MODE_DP,
+	PHY_MODE_HDMI,
 };
 
 enum phy_media {

@@ -60,11 +62,14 @@ enum phy_media {
  *		the DisplayPort protocol.
  * @lvds:	Configuration set applicable for phys supporting
  *		the LVDS phy mode.
+ * @hdmi:	Configuration set applicable for phys supporting
+ *		the HDMI phy mode.
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
 	struct phy_configure_opts_dp		dp;
 	struct phy_configure_opts_lvds		lvds;
+	struct phy_configure_opts_hdmi		hdmi;
 };
 
 /**

Signature · 1 line

2.34.1

-----Original Message-----
From: Vinod Koul <[email protected]>
Sent: 2023年6月21日 19:22
To: Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
 include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 22 lines

 include/linux/phy/phy.h      |  7 ++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)  create mode 100644

include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +12 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification
+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5
+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum

include/linux/phy/phy-hdmi.h line 18

Quoted 5 lines

include/linux/phy/phy-hdmi.h new file +5 -0

+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */

Better add this comments and above one as expected by kernel-doc for enum..

Quoted 56 lines

include/linux/phy/phy-hdmi.h new file +19 -0

+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6,
+};
+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

include/linux/phy/phy.h index renamed from include/linux/phy/phy.h +0 -0

3a570bc59fc7..93d77d45b1d4 100644

include/linux/phy/phy.h +6 -1

@@ -17,6 +17,7 @@
 #include <linux/regulator/consumer.h>
 
 #include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-hdmi.h>
 #include <linux/phy/phy-lvds.h>
 #include <linux/phy/phy-mipi-dphy.h>
 

@@ -42,7 +43,8 @@ enum phy_mode {
      PHY_MODE_MIPI_DPHY,
      PHY_MODE_SATA,
      PHY_MODE_LVDS,
-     PHY_MODE_DP
+     PHY_MODE_DP,
+     PHY_MODE_HDMI,
 };
 
 enum phy_media {

@@ -60,11 +62,14 @@ enum phy_media {
  *           the DisplayPort protocol.
  * @lvds:    Configuration set applicable for phys supporting
  *           the LVDS phy mode.
+ * @hdmi:    Configuration set applicable for phys supporting
+ *           the HDMI phy mode.
  */
 union phy_configure_opts {
      struct phy_configure_opts_mipi_dphy     mipi_dphy;
      struct phy_configure_opts_dp            dp;
      struct phy_configure_opts_lvds          lvds;
+     struct phy_configure_opts_hdmi          hdmi;
 };
 

Quoted 3 lines

include/linux/phy/phy.h +0 -1

 /**
--

2.34.1

--
~Vinod

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
  include/linux/phy/phy-hdmi.h | 38 ++++++++++++++++++++++++++++++++++++
  include/linux/phy/phy.h      |  7 ++++++-
  2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

include/linux/phy/phy-hdmi.h new file +12 -0

new file mode 100644
index 000000000000..5765aa5bc175
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification
+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5
+ * YUV420: HDMI Specification 2.a Section 7.1

include/linux/phy/phy-hdmi.h new file +6 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:	Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.

-----Original Message-----
From: Dmitry Baryshkov <[email protected]>
Sent: 2023年6月25日 2:02
To: Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
  include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 21 lines

  include/linux/phy/phy.h      |  7 ++++++-
  2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +11 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification
+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5

include/linux/phy/phy-hdmi.h line 21

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum
+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6,
+};

This enum duplicates enum hdmi_colorspace from <linux/hdmi.h> HDMI 2.0 defines '7' to be IDO-defined.

Would it be better to use that enum instead?

Quoted 6 lines

include/linux/phy/phy-hdmi.h new file +5 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.

include/linux/phy/phy-hdmi.h line 38

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

[skipped the rest]

--
With best wishes
Dmitry

Hi Dmitry,

Thanks for your comments,

Quoted 15 lines

-----Original Message-----
From: Dmitry Baryshkov <[email protected]>
Sent: 2023年6月25日 2:02
To: Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Quoted 53 lines

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
  include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 21 lines

  include/linux/phy/phy.h      |  7 ++++++-
  2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +11 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification
+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5

include/linux/phy/phy-hdmi.h line 21

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum
+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6,
+};

This enum duplicates enum hdmi_colorspace from <linux/hdmi.h> HDMI 2.0 defines '7' to be IDO-defined.

Quoted 1 line

Would it be better to use that enum instead?

Accept. I will create head file hdmi_colorspace.h to reuse enum hdmi_colorspace in <linux/hdmi.h>.

B.R
Sandor

Quoted 22 lines

Quoted 6 lines

include/linux/phy/phy-hdmi.h new file +5 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.

include/linux/phy/phy-hdmi.h line 38

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

[skipped the rest]

--
With best wishes
Dmitry

-----Original Message-----
From: Dmitry Baryshkov <[email protected]>
Sent: 2023年7月10日 15:30
To: Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: Re: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Quoted 21 lines · Sandor Yu

Hi Dmitry,

Thanks for your comments,

Quoted 16 lines

-----Original Message-----
From: Dmitry Baryshkov <[email protected]>
Sent: 2023年6月25日 2:02
To: Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Is this part necessary?

Quoted 53 lines

Quoted 53 lines

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
  include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 20 lines

  include/linux/phy/phy.h      |  7 ++++++-
  2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +10 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification

include/linux/phy/phy-hdmi.h line 20

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5
+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum
+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6, };

This enum duplicates enum hdmi_colorspace from <linux/hdmi.h> HDMI 2.0 defines '7' to be IDO-defined.

Quoted 2 lines

Quoted 1 line

Would it be better to use that enum instead?

Accept. I will create head file hdmi_colorspace.h to reuse enum

hdmi_colorspace in <linux/hdmi.h>.

Hmm, you need another header file to reuse this enum.

Quoted 4 lines

B.R
Sandor

Quoted 1 line

Quoted 8 lines

Quoted 8 lines

include/linux/phy/phy-hdmi.h

Quoted 8 lines

include/linux/phy/phy-hdmi.h new file +8 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI

phy.

Quoted 10 lines

Quoted 10 lines

include/linux/phy/phy-hdmi.h line 38

Quoted 7 lines

include/linux/phy/phy-hdmi.h new file +7 -0

+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

[skipped the rest]

Quoted 4 lines

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--
With best wishes
Dmitry

--
With best wishes
Dmitry

Hi Dmitry,

Thanks for your comments,

Quoted 48 lines

From: Dmitry Baryshkov <[email protected]>

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
   include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 21 lines

   include/linux/phy/phy.h      |  7 ++++++-
   2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +11 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification
+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5

include/linux/phy/phy-hdmi.h line 21

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum
+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6,
+};

This enum duplicates enum hdmi_colorspace from <linux/hdmi.h> HDMI 2.0 defines '7' to be IDO-defined.

Quoted 1 line

Would it be better to use that enum instead?

Accept. I will create head file hdmi_colorspace.h to reuse enum hdmi_colorspace in <linux/hdmi.h>.

B.R
Sandor

Quoted 22 lines

Quoted 6 lines

include/linux/phy/phy-hdmi.h new file +5 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.

include/linux/phy/phy-hdmi.h line 38

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

[skipped the rest]

--
With best wishes
Dmitry

-----Original Message-----
From: Dmitry Baryshkov <[email protected]>
Sent: 2023年7月10日 15:44
To: Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: Re: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Quoted 51 lines · Sandor Yu

Hi Dmitry,

Thanks for your comments,

Quoted 47 lines

From: Dmitry Baryshkov <[email protected]> On 15/06/2023

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
   include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 20 lines

   include/linux/phy/phy.h      |  7 ++++++-
   2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +10 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification

include/linux/phy/phy-hdmi.h line 20

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5
+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum
+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6, };

This enum duplicates enum hdmi_colorspace from <linux/hdmi.h> HDMI 2.0 defines '7' to be IDO-defined.

Quoted 2 lines

Quoted 1 line

Would it be better to use that enum instead?

Accept. I will create head file hdmi_colorspace.h to reuse enum

hdmi_colorspace in <linux/hdmi.h>.

Excuse me, it was supposed to be a question.

Do you need another header file to reuse this enum?

Quoted 5 lines

B.R
Sandor

Quoted 1 line

Quoted 8 lines

Quoted 8 lines

include/linux/phy/phy-hdmi.h

Quoted 8 lines

include/linux/phy/phy-hdmi.h new file +8 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI

phy.

Quoted 10 lines

Quoted 10 lines

include/linux/phy/phy-hdmi.h line 38

Quoted 7 lines

include/linux/phy/phy-hdmi.h new file +7 -0

+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

[skipped the rest]

Quoted 4 lines

Quoted 3 lines

--
With best wishes
Dmitry

--
With best wishes
Dmitry

Quoted 74 lines

-----Original Message-----
From: Dmitry Baryshkov <[email protected]>
Sent: 2023年7月10日 15:44
To: Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: Re: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Quoted 53 lines · Sandor Yu

Hi Dmitry,

Thanks for your comments,

Quoted 47 lines

From: Dmitry Baryshkov <[email protected]> On 15/06/2023

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
   include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 20 lines

   include/linux/phy/phy.h      |  7 ++++++-
   2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +10 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification

include/linux/phy/phy-hdmi.h line 20

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5
+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum
+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6, };

This enum duplicates enum hdmi_colorspace from <linux/hdmi.h> HDMI 2.0 defines '7' to be IDO-defined.

Quoted 1 line

Would it be better to use that enum instead?

Accept. I will create head file hdmi_colorspace.h to reuse enum

Quoted 5 lines

hdmi_colorspace in <linux/hdmi.h>.

Excuse me, it was supposed to be a question.

Do you need another header file to reuse this enum?

I'm not sure community whether would accept the patch that simply include <linux/hdmi.h> in phy-hdmi.h because there are lots of other definition in <linux/hdmi.h> that not need by phy-hdmi.h. If the answer is yes, I happy to follow.

Quoted 25 lines

Quoted 6 lines

B.R
Sandor

Quoted 1 line

Quoted 8 lines

Quoted 8 lines

include/linux/phy/phy-hdmi.h

Quoted 8 lines

include/linux/phy/phy-hdmi.h new file +8 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI

phy.

Quoted 10 lines

Quoted 10 lines

include/linux/phy/phy-hdmi.h line 38

Quoted 7 lines

include/linux/phy/phy-hdmi.h new file +7 -0

+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

[skipped the rest]

Quoted 8 lines

Quoted 4 lines

Quoted 3 lines

--
With best wishes
Dmitry

--
With best wishes
Dmitry

B.R
Sandor

Quoted 80 lines

Quoted 80 lines

-----Original Message-----
From: Dmitry Baryshkov <[email protected]>
Sent: 2023年7月10日 15:44
To: Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; dl-linux-imx <[email protected]>; Oliver Brown <[email protected]>
Subject: Re: [EXT] Re: [PATCH v6 4/8] phy: Add HDMI configuration options

Quoted 52 lines · Sandor Yu

Hi Dmitry,

Thanks for your comments,

Quoted 48 lines

From: Dmitry Baryshkov <[email protected]> On

Quoted 10 lines · Sandor Yu

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Signed-off-by Sandor Yu <[email protected]>

---
   include/linux/phy/phy-hdmi.h | 38

++++++++++++++++++++++++++++++++++++

Quoted 20 lines

   include/linux/phy/phy.h      |  7 ++++++-
   2 files changed, 44 insertions(+), 1 deletion(-)

create mode 100644 include/linux/phy/phy-hdmi.h

(quoted diff) +0 -0

b/include/linux/phy/phy-hdmi.h new file mode 100644 index 000000000000..5765aa5bc175

include/linux/phy/phy-hdmi.h new file +10 -0

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification

include/linux/phy/phy-hdmi.h line 20

Quoted 10 lines

include/linux/phy/phy-hdmi.h new file +10 -0

+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5
+ * YUV420: HDMI Specification 2.a Section 7.1  */ enum
+hdmi_phy_colorspace {
+     HDMI_PHY_COLORSPACE_RGB,        /* RGB 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV422,     /* YCbCr 4:2:2 */
+     HDMI_PHY_COLORSPACE_YUV444,     /* YCbCr 4:4:4 */
+     HDMI_PHY_COLORSPACE_YUV420,     /* YCbCr 4:2:0 */
+     HDMI_PHY_COLORSPACE_RESERVED4,
+     HDMI_PHY_COLORSPACE_RESERVED5,
+     HDMI_PHY_COLORSPACE_RESERVED6, };

This enum duplicates enum hdmi_colorspace from <linux/hdmi.h> HDMI
2.0 defines '7' to be IDO-defined.

Quoted 2 lines

Quoted 1 line

Would it be better to use that enum instead?

Accept. I will create head file hdmi_colorspace.h to reuse enum

hdmi_colorspace in <linux/hdmi.h>.

Excuse me, it was supposed to be a question.

Quoted 3 lines

Quoted 1 line

Do you need another header file to reuse this enum?

I'm not sure community whether would accept the patch that simply include <linux/hdmi.h> in phy-hdmi.h because there are lots of other

definition in <linux/hdmi.h> that not need by phy-hdmi.h.

Quoted 1 line

If the answer is yes, I happy to follow.

In my opinion it's a better alternative to creating yet another header.

Quoted 32 lines

Quoted 32 lines

Quoted 7 lines

B.R
Sandor

Quoted 1 line

Quoted 9 lines

Quoted 9 lines

include/linux/phy/phy-hdmi.h

Quoted 9 lines

include/linux/phy/phy-hdmi.h new file +9 -0

+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:  Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state
+of a HDMI

phy.

Quoted 14 lines

Quoted 13 lines

include/linux/phy/phy-hdmi.h line 38

Quoted 7 lines

include/linux/phy/phy-hdmi.h new file +7 -0

+ */
+struct phy_configure_opts_hdmi {
+     unsigned int pixel_clk_rate;
+     unsigned int bpc;
+     enum hdmi_phy_colorspace color_space; };
+
+#endif /* __PHY_HDMI_H_ */

[skipped the rest]

--
With best wishes
Dmitry

Quoted 7 lines

Quoted 3 lines

--
With best wishes
Dmitry

B.R
Sandor

--
With best wishes
Dmitry

Add a new DRM HDMI bridge driver for Cadence MHDP8501 that used in Freescale i.MX8MQ SoC.
MHDP8501 could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SoC, the HDMI FW was loaded and activated by SOC ROM code. Bootload binary included HDMI FW was required for the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/gpu/drm/bridge/cadence/Kconfig        |   12 +
 drivers/gpu/drm/bridge/cadence/Makefile       |    1 +
 .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c   | 1024 +++++++++++++++++
 3 files changed, 1037 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Kconfig index 5b7ec4e49aa1..bee05e834055 100644

drivers/gpu/drm/bridge/cadence/Kconfig +12 -0

@@ -59,3 +59,15 @@ config DRM_CDNS_MHDP8501_DP
 	  Support Cadence MHDP8501 DisplayPort driver.
 	  Cadence MHDP8501 Controller support one or more protocols,
 	  DisplayPort firmware is required for this driver.
+
+config DRM_CDNS_MHDP8501_HDMI
+	tristate "Cadence MHDP8501 HDMI DRM driver"
+	select DRM_KMS_HELPER
+	select DRM_PANEL_BRIDGE
+	select DRM_DISPLAY_HELPER
+	select DRM_CDNS_AUDIO
+	depends on OF
+	help
+	  Support Cadence MHDP8501 HDMI driver.
+	  Cadence MHDP8501 Controller support one or more protocols,
+	  HDMI firmware is required for this driver.

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Makefile index 5842e4540c62..8a129c14ac14 100644

drivers/gpu/drm/bridge/cadence/Makefile +0 -0

@@ -7,3 +7,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o

cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o

obj-$(CONFIG_DRM_CDNS_MHDP8501_DP) += cdns-mhdp8501-dp.o

drivers/gpu/drm/bridge/cadence/Makefile +1 -0

+obj-$(CONFIG_DRM_CDNS_MHDP8501_HDMI) += cdns-mhdp8501-hdmi.o

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file mode 100644 index 000000000000..43673f1b50f6

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +0 -0

-----Original Message-----
From: Alexander Stein <[email protected]>
Sent: 2023年6月16日 17:30
To: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Oliver Brown <[email protected]>; Sandor Yu <[email protected]>; dl-linux-imx <[email protected]>; [email protected]; Sandor Yu <[email protected]>
Subject: [EXT] Re: [PATCH v6 5/8] drm: bridge: Cadence: Add MHDP8501 HDMI driver

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Hi Sandor,

thanks for sending a new version.

Am Donnerstag, 15. Juni 2023, 03:38:15 CEST schrieb Sandor Yu:

Quoted 6 lines

Add a new DRM HDMI bridge driver for Cadence MHDP8501 that used in Freescale i.MX8MQ SoC.
MHDP8501 could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SoC, the HDMI FW was loaded and activated by SOC ROM

code.

Quoted 7 lines

Bootload binary included HDMI FW was required for the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/gpu/drm/bridge/cadence/Kconfig        |   12 +
 drivers/gpu/drm/bridge/cadence/Makefile       |    1 +
 .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c   | 1024

+++++++++++++++++

Quoted 44 lines

 3 files changed, 1037 insertions(+)
 create mode 100644

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Kconfig index
5b7ec4e49aa1..bee05e834055
100644

drivers/gpu/drm/bridge/cadence/Kconfig +12 -0

@@ -59,3 +59,15 @@ config DRM_CDNS_MHDP8501_DP
        Support Cadence MHDP8501 DisplayPort driver.
        Cadence MHDP8501 Controller support one or more protocols,
        DisplayPort firmware is required for this driver.
+
+config DRM_CDNS_MHDP8501_HDMI
+     tristate "Cadence MHDP8501 HDMI DRM driver"
+     select DRM_KMS_HELPER
+     select DRM_PANEL_BRIDGE
+     select DRM_DISPLAY_HELPER
+     select DRM_CDNS_AUDIO
+     depends on OF
+     help
+       Support Cadence MHDP8501 HDMI driver.
+       Cadence MHDP8501 Controller support one or more protocols,
+       HDMI firmware is required for this driver.

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Makefile index
5842e4540c62..8a129c14ac14
100644

drivers/gpu/drm/bridge/cadence/Makefile +0 -0

@@ -7,3 +7,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o

cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o

obj-$(CONFIG_DRM_CDNS_MHDP8501_DP) += cdns-mhdp8501-dp.o

drivers/gpu/drm/bridge/cadence/Makefile +1 -0

+obj-$(CONFIG_DRM_CDNS_MHDP8501_HDMI) += cdns-mhdp8501-hdmi.o

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file mode 100644 index 000000000000..43673f1b50f6

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +0 -0

[...]

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c line 678

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +2 -0

+static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge,
+                              enum drm_bridge_attach_flags flags)

{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +10 -0

+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+     struct drm_mode_config *config = &bridge->dev->mode_config;
+     struct drm_encoder *encoder = bridge->encoder;
+     struct drm_connector *connector = &mhdp->connector;
+
+     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+             connector->interlace_allowed = 0;
+             connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+             drm_connector_helper_add(connector,

&cdns_hdmi_connector_helper_funcs);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +2 -0

+
+             drm_connector_init(bridge->dev, connector,

&cdns_hdmi_connector_funcs,

Quoted 1 line

+

DRM_MODE_CONNECTOR_HDMIA);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +3 -0

+
+             drm_object_attach_property(&connector->base,
+                                        config-

hdr_output_metadata_property, 0);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +3 -0

+
+             if
+ (!drm_mode_create_hdmi_colorspace_property(connector))

This is missing a 2nd parameter.

Quoted 2 lines

+

drm_object_attach_property(&connector->base,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c line 705

Quoted 8 lines

+ connector-
colorspace_property, 0);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +6 -0

+
+             drm_connector_attach_encoder(connector, encoder);
+     }
+
+     return 0;
+}

[...]

Best regards,
Alexander
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq/
-group.com%2F&data=05%7C01%7CSandor.yu%40nxp.com%7C77fbaace052c 4ccf338c08db6e4c40cb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C 0%7C638225046010817530%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C %7C%7C&sdata=JJjeV2InXzHyefL4uiK9%2BRtSVjoBYd%2FwIqSbIQhDH90%3D &reserved=0

Hi Alexander,

Thanks for your comments,

Quoted 21 lines

-----Original Message-----
From: Alexander Stein <[email protected]>
Sent: 2023年6月16日 17:30
To: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Oliver Brown <[email protected]>; Sandor Yu <[email protected]>; dl-linux-imx <[email protected]>; [email protected]; Sandor Yu <[email protected]>
Subject: [EXT] Re: [PATCH v6 5/8] drm: bridge: Cadence: Add MHDP8501 HDMI driver

Caution: This is an external email. Please take care when clicking links or

Quoted 127 lines

'Report this email' button

Hi Sandor,

thanks for sending a new version.

Am Donnerstag, 15. Juni 2023, 03:38:15 CEST schrieb Sandor Yu:

Quoted 8 lines

Add a new DRM HDMI bridge driver for Cadence MHDP8501 that used in Freescale i.MX8MQ SoC.
MHDP8501 could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SoC, the HDMI FW was loaded and activated by SOC ROM

code.

Quoted 10 lines

Bootload binary included HDMI FW was required for the driver.

Signed-off-by Sandor Yu <[email protected]>

---

 drivers/gpu/drm/bridge/cadence/Kconfig        |   12 +
 drivers/gpu/drm/bridge/cadence/Makefile       |    1 +
 .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c   | 1024

+++++++++++++++++

Quoted 52 lines

 3 files changed, 1037 insertions(+)
 create mode 100644

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Kconfig index
5b7ec4e49aa1..bee05e834055
100644

drivers/gpu/drm/bridge/cadence/Kconfig +12 -0

@@ -59,3 +59,15 @@ config DRM_CDNS_MHDP8501_DP
 
        Support Cadence MHDP8501 DisplayPort driver.
        Cadence MHDP8501 Controller support one or more protocols,
        DisplayPort firmware is required for this driver.
 
+
+config DRM_CDNS_MHDP8501_HDMI
+     tristate "Cadence MHDP8501 HDMI DRM driver"
+     select DRM_KMS_HELPER
+     select DRM_PANEL_BRIDGE
+     select DRM_DISPLAY_HELPER
+     select DRM_CDNS_AUDIO
+     depends on OF
+     help
+       Support Cadence MHDP8501 HDMI driver.
+       Cadence MHDP8501 Controller support one or more protocols,
+       HDMI firmware is required for this driver.

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Makefile index
5842e4540c62..8a129c14ac14
100644

drivers/gpu/drm/bridge/cadence/Makefile +0 -0

@@ -7,3 +7,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o

cdns-mhdp8546-hdcp.o cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o

obj-$(CONFIG_DRM_CDNS_MHDP8501_DP) += cdns-mhdp8501-dp.o

drivers/gpu/drm/bridge/cadence/Makefile +1 -0

+obj-$(CONFIG_DRM_CDNS_MHDP8501_HDMI) += cdns-mhdp8501-hdmi.o

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file mode 100644 index 000000000000..43673f1b50f6

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +0 -0

[...]

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c line 678

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +2 -0

+static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge,
+                              enum drm_bridge_attach_flags flags)

{

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +10 -0

+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+     struct drm_mode_config *config = &bridge->dev->mode_config;
+     struct drm_encoder *encoder = bridge->encoder;
+     struct drm_connector *connector = &mhdp->connector;
+
+     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+             connector->interlace_allowed = 0;
+             connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+             drm_connector_helper_add(connector,

&cdns_hdmi_connector_helper_funcs);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +2 -0

+
+             drm_connector_init(bridge->dev, connector,

&cdns_hdmi_connector_funcs,

Quoted 1 line

+

DRM_MODE_CONNECTOR_HDMIA);

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +3 -0

+
+             drm_object_attach_property(&connector->base,
+                                        config-

hdr_output_metadata_property, 0);

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +3 -0

+
+             if
+ (!drm_mode_create_hdmi_colorspace_property(connector))

This is missing a 2nd parameter.

I have not found function drm_mode_create_hdmi_colorspace_property need 2nd parameter in L6.1.

And those connector init functions will be remove in
the next version according Sam's comments, because they are not really needed.

B.R
Sandor

Quoted 36 lines

Quoted 3 lines

+

drm_object_attach_property(&connector->base,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c line 705

Quoted 10 lines

+ connector-

colorspace_property, 0);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file +6 -0

+
+             drm_connector_attach_encoder(connector, encoder);
+     }
+
+     return 0;
+}

[...]

Best regards,
Alexander
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq/
-group.com%2F&data=05%7C01%7CSandor.yu%40nxp.com%7C77fbaace052c 4ccf338c08db6e4c40cb%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C 0%7C638225046010817530%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C %7C%7C&sdata=JJjeV2InXzHyefL4uiK9%2BRtSVjoBYd%2FwIqSbIQhDH90%3D &reserved=0

Add bindings for Freescale iMX8MQ DP and HDMI PHY.

Signed-off-by Sandor Yu <[email protected]>

---
 .../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml  | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file mode 100644
index 000000000000..917f113503dc

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file +6 -0

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8mq-dp-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file +37 -0

+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: PHY reference clock.
+      - description: APB clock.
+
+  clock-names:
+    items:
+      - const: ref
+      - const: apb
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/phy/phy.h>
+    dp_phy: phy@32c00000 {
+        compatible = "fsl,imx8mq-dp-phy";
+        reg = <0x32c00000 0x100000>;
+        #phy-cells = <0>;
+        clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+        clock-names = "ref", "apb";
+    };

-----Original Message-----
From: Alexander Stein <[email protected]>
Sent: 2023年6月16日 17:35
To: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Cc: Oliver Brown <[email protected]>; Sandor Yu <[email protected]>; dl-linux-imx <[email protected]>; [email protected]; Sandor Yu <[email protected]>
Subject: [EXT] Re: [PATCH v6 6/8] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY

Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button

Hi Sandor,

Am Donnerstag, 15. Juni 2023, 03:38:16 CEST schrieb Sandor Yu:

Quoted 8 lines

Add bindings for Freescale iMX8MQ DP and HDMI PHY.

Signed-off-by Sandor Yu <[email protected]>

---
 .../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml  | 53
+++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644

Quoted 8 lines

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file mode 100644 index 000000000000..917f113503dc --- /dev/null
+++

b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yam

Review line 4

Quoted 7 lines

+++ l

(quoted diff) +4 -0

@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
+---
+$id:
+http://devi/

+cetree.org%2Fschemas%2Fphy%2Ffsl%2Cimx8mq-dp-hdmi-phy.yaml%23&d ata=05

Quoted 1 line

+%7C01%7CSandor.yu%40nxp.com%7Cf2d4e5ea99fa4f5776bf08db6e4ce7ba %7C686e

Quoted 1 line

+a1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638225048817792176%7C Unknown%7

Quoted 1 line

+CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW wiLCJX

Quoted 1 line

+VCI6Mn0%3D%7C3000%7C%7C%7C&sdata=ayYA0rayDR2w1LDgU53VtCitw MH9PnoblX2k

Review

Quoted 4 lines

(quoted diff) +3 -0

+Jhbu6Gs%3D&reserved=0
+$schema:
+http://devi/

+cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7CSandor. yu%40n

Quoted 1 line

+xp.com%7Cf2d4e5ea99fa4f5776bf08db6e4ce7ba%7C686ea1d3bc2b4c6fa92 cd99c5

Quoted 1 line

+c301635%7C0%7C0%7C638225048817792176%7CUnknown%7CTWFpbGZs b3d8eyJWIjoi

Quoted 1 line

+MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3 000%7C%

Quoted 1 line

+7C%7C&sdata=DagQtrIblGEk3T1mamSmI2010SRszqhIpJ4piXy3L4M%3D&re served=0

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml line 16

Quoted 11 lines

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file +11 -0

+
+title: Cadence HDP-TX DP/HDMI PHY for Freescale i.MX8MQ SoC
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mq-dp-phy
+      - fsl,imx8mq-hdmi-phy

How is it intended to select DP or HDMI? E.g. provide a single default dp-phy node in imx8mq.dtsi and change the compatible to HDMI on board-level?

Best regards,
Alexander

Quoted 25 lines

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file +25 -0

+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: PHY reference clock.
+      - description: APB clock.
+
+  clock-names:
+    items:
+      - const: ref
+      - const: apb
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+
+additionalProperties: false

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml

Quoted 10 lines

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file +10 -0

+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/phy/phy.h>
+    dp_phy: phy@32c00000 {
+        compatible = "fsl,imx8mq-dp-phy";
+        reg = <0x32c00000 0x100000>;
+        #phy-cells = <0>;
+        clocks = <&hdmi_phy_27m>, <&clk

IMX8MQ_CLK_DISP_APB_ROOT>;

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml line 53

Quoted 2 lines

Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml new file +2 -0

+        clock-names = "ref", "apb";
+    };

--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq/
-group.com%2F&data=05%7C01%7CSandor.yu%40nxp.com%7Cf2d4e5ea99fa 4f5776bf08db6e4ce7ba%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C 0%7C638225048817792176%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C %7C%7C&sdata=6uih84XByS6aX519z7l50amZl2XnPIMSggyfSD4xd4M%3D&re served=0

Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ

Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort PHY mode is configurated in the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/phy/freescale/Kconfig             |   9 +
 drivers/phy/freescale/Makefile            |   1 +
 drivers/phy/freescale/phy-fsl-imx8mq-dp.c | 697 ++++++++++++++++++++++
 3 files changed, 707 insertions(+)
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-dp.c

drivers/phy/freescale/Kconfig +9 -0

index 853958fb2c06..a99ee370eda6 100644
@@ -35,6 +35,15 @@ config PHY_FSL_IMX8M_PCIE
 	  Enable this to add support for the PCIE PHY as found on
 	  i.MX8M family of SOCs.
 
+config PHY_CADENCE_DP_PHY
+	tristate "Cadence HDPTX DP PHY support"
+	depends on OF && HAS_IOMEM
+	depends on COMMON_CLK
+	select GENERIC_PHY
+	help
+	  Enable this to support the Cadence HDPTX DP PHY driver
+	  on NXP's i.MX8MQ SOC.
+
 endif
 
 config PHY_FSL_LYNX_28G

drivers/phy/freescale/Makefile +1 -0

index cedb328bc4d2..c3bdf3fa2e72 100644
@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY)	+= phy-fsl-imx8qm-lvds-phy.o
 obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)	+= phy-fsl-imx8-mipi-dphy.o
 obj-$(CONFIG_PHY_FSL_IMX8M_PCIE)	+= phy-fsl-imx8m-pcie.o
 obj-$(CONFIG_PHY_FSL_LYNX_28G)		+= phy-fsl-lynx-28g.o
+obj-$(CONFIG_PHY_CADENCE_DP_PHY)	+= phy-fsl-imx8mq-dp.o

drivers/phy/freescale/phy-fsl-imx8mq-dp.c new file +7 -0

new file mode 100644
index 000000000000..2bd6772a5d3b
@@ -0,0 +1,697 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence HDP-TX Display Port Interface (DP) PHY driver
+ *
+ * Copyright (C) 2022 NXP Semiconductor, Inc.
+ */
+#include <asm/unaligned.h>

drivers/phy/freescale/phy-fsl-imx8mq-dp.c new file +70 -0

+
+/* PHY registers */
+#define CMN_SSM_BIAS_TMR                0x0022
+#define CMN_PLLSM0_PLLEN_TMR            0x0029
+#define CMN_PLLSM0_PLLPRE_TMR           0x002A
+#define CMN_PLLSM0_PLLVREF_TMR          0x002B
+#define CMN_PLLSM0_PLLLOCK_TMR          0x002C
+#define CMN_PLLSM0_USER_DEF_CTRL        0x002F
+#define CMN_PSM_CLK_CTRL                0x0061
+#define CMN_PLL0_VCOCAL_START           0x0081
+#define CMN_PLL0_VCOCAL_INIT_TMR        0x0084
+#define CMN_PLL0_VCOCAL_ITER_TMR        0x0085
+#define CMN_PLL0_INTDIV                 0x0094
+#define CMN_PLL0_FRACDIV                0x0095
+#define CMN_PLL0_HIGH_THR               0x0096
+#define CMN_PLL0_DSM_DIAG               0x0097
+#define CMN_PLL0_SS_CTRL2               0x0099
+#define CMN_ICAL_INIT_TMR               0x00C4
+#define CMN_ICAL_ITER_TMR               0x00C5
+#define CMN_RXCAL_INIT_TMR              0x00D4
+#define CMN_RXCAL_ITER_TMR              0x00D5
+#define CMN_TXPUCAL_INIT_TMR            0x00E4
+#define CMN_TXPUCAL_ITER_TMR            0x00E5
+#define CMN_TXPDCAL_INIT_TMR            0x00F4
+#define CMN_TXPDCAL_ITER_TMR            0x00F5
+#define CMN_ICAL_ADJ_INIT_TMR           0x0102
+#define CMN_ICAL_ADJ_ITER_TMR           0x0103
+#define CMN_RX_ADJ_INIT_TMR             0x0106
+#define CMN_RX_ADJ_ITER_TMR             0x0107
+#define CMN_TXPU_ADJ_INIT_TMR           0x010A
+#define CMN_TXPU_ADJ_ITER_TMR           0x010B
+#define CMN_TXPD_ADJ_INIT_TMR           0x010E
+#define CMN_TXPD_ADJ_ITER_TMR           0x010F
+#define CMN_DIAG_PLL0_FBH_OVRD          0x01C0
+#define CMN_DIAG_PLL0_FBL_OVRD          0x01C1
+#define CMN_DIAG_PLL0_OVRD              0x01C2
+#define CMN_DIAG_PLL0_TEST_MODE         0x01C4
+#define CMN_DIAG_PLL0_V2I_TUNE          0x01C5
+#define CMN_DIAG_PLL0_CP_TUNE           0x01C6
+#define CMN_DIAG_PLL0_LF_PROG           0x01C7
+#define CMN_DIAG_PLL0_PTATIS_TUNE1      0x01C8
+#define CMN_DIAG_PLL0_PTATIS_TUNE2      0x01C9
+#define CMN_DIAG_HSCLK_SEL              0x01E0
+#define CMN_DIAG_PER_CAL_ADJ            0x01EC
+#define CMN_DIAG_CAL_CTRL               0x01ED
+#define CMN_DIAG_ACYA                   0x01FF
+#define XCVR_PSM_RCTRL                  0x4001
+#define XCVR_PSM_CAL_TMR                0x4002
+#define XCVR_PSM_A0IN_TMR               0x4003
+#define TX_TXCC_CAL_SCLR_MULT_0         0x4047
+#define TX_TXCC_CPOST_MULT_00_0         0x404C
+#define XCVR_DIAG_PLLDRC_CTRL           0x40E0
+#define XCVR_DIAG_PLLDRC_CTRL           0x40E0
+#define XCVR_DIAG_HSCLK_SEL             0x40E1
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR   0x40F2
+#define TX_PSC_A0                       0x4100
+#define TX_PSC_A1                       0x4101
+#define TX_PSC_A2                       0x4102
+#define TX_PSC_A3                       0x4103
+#define TX_RCVDET_EN_TMR                0x4122
+#define TX_RCVDET_ST_TMR                0x4123
+#define TX_DIAG_BGREF_PREDRV_DELAY      0x41E7
+#define TX_DIAG_BGREF_PREDRV_DELAY      0x41E7
+#define TX_DIAG_ACYA_0                  0x41FF
+#define TX_DIAG_ACYA_1                  0x43FF
+#define TX_DIAG_ACYA_2                  0x45FF
+#define TX_DIAG_ACYA_3                  0x47FF
+#define TX_ANA_CTRL_REG_1               0x5020
+#define TX_ANA_CTRL_REG_2               0x5021
+#define TX_DIG_CTRL_REG_1               0x5023

drivers/phy/freescale/phy-fsl-imx8mq-dp.c new file +31 -0

+
+#define REF_CLK_27MHZ		27000000
+
+enum dp_link_rate {
+	RATE_1_6 = 162000,
+	RATE_2_1 = 216000,
+	RATE_2_4 = 243000,
+	RATE_2_7 = 270000,
+	RATE_3_2 = 324000,
+	RATE_4_3 = 432000,
+	RATE_5_4 = 540000,
+	RATE_8_1 = 810000,
+};
+
+#define MAX_LINK_RATE RATE_5_4
+
+struct phy_pll_reg {
+	u16 val[7];
+	u32 addr;
+};
+
+static const struct phy_pll_reg phy_pll_27m_cfg[] = {
+	/*  1.62    2.16    2.43    2.7     3.24    4.32    5.4      register address */
+	{{ 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E, 0x010E }, CMN_PLL0_VCOCAL_INIT_TMR },
+	{{ 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B, 0x001B }, CMN_PLL0_VCOCAL_ITER_TMR },
+	{{ 0x30B9, 0x3087, 0x3096, 0x30B4, 0x30B9, 0x3087, 0x30B4 }, CMN_PLL0_VCOCAL_START },
+	{{ 0x0077, 0x009F, 0x00B3, 0x00C7, 0x0077, 0x009F, 0x00C7 }, CMN_PLL0_INTDIV },
+	{{ 0xF9DA, 0xF7CD, 0xF6C7, 0xF5C1, 0xF9DA, 0xF7CD, 0xF5C1 }, CMN_PLL0_FRACDIV },
+	{{ 0x001E, 0x0028, 0x002D, 0x0032, 0x001E, 0x0028, 0x0032 }, CMN_PLL0_HIGH_THR },
+	{{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_PLL0_DSM_DIAG },
+	{{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL },

drivers/phy/freescale/phy-fsl-imx8mq-dp.c new file +559 -0

+};
+
+struct cdns_hdptx_dp_phy {
+	void __iomem *regs;	/* DPTX registers base */
+	struct device *dev;
+	struct phy *phy;
+	struct mutex mbox_mutex; /* mutex to protect mailbox */
+	struct clk *ref_clk, *apb_clk;
+	u32 ref_clk_rate;
+	u32 num_lanes;
+	u32 link_rate;
+	bool power_up;
+};
+
+static int cdns_phy_reg_write(struct cdns_hdptx_dp_phy *cdns_phy, u32 addr, u32 val)
+{
+	return cdns_mhdp_reg_write(cdns_phy, ADDR_PHY_AFE + (addr << 2), val);
+}
+
+static u32 cdns_phy_reg_read(struct cdns_hdptx_dp_phy *cdns_phy, u32 addr)
+{
+	u32 reg32;
+
+	cdns_mhdp_reg_read(cdns_phy, ADDR_PHY_AFE + (addr << 2), &reg32);
+	return reg32;
+}
+
+static int link_rate_index(u32 rate)
+{
+	switch (rate) {
+	case RATE_1_6:
+		return 0;
+	case RATE_2_1:
+		return 1;
+	case RATE_2_4:
+		return 2;
+	case RATE_2_7:
+		return 3;
+	case RATE_3_2:
+		return 4;
+	case RATE_4_3:
+		return 5;
+	case RATE_5_4:
+		return 6;
+	default:
+		return -1;
+	}
+}
+
+static int hdptx_dp_clk_enable(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	struct device *dev = cdns_phy->dev;
+	u32 ref_clk_rate;
+	int ret;
+
+	cdns_phy->ref_clk = devm_clk_get(dev, "ref");
+	if (IS_ERR(cdns_phy->ref_clk)) {
+		dev_err(dev, "phy ref clock not found\n");
+		return PTR_ERR(cdns_phy->ref_clk);
+	}
+
+	cdns_phy->apb_clk = devm_clk_get(dev, "apb");
+	if (IS_ERR(cdns_phy->apb_clk)) {
+		dev_err(dev, "phy apb clock not found\n");
+		return PTR_ERR(cdns_phy->apb_clk);
+	}
+
+	ret = clk_prepare_enable(cdns_phy->ref_clk);
+	if (ret) {
+		dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
+		return ret;
+	}
+
+	ref_clk_rate = clk_get_rate(cdns_phy->ref_clk);
+	if (!ref_clk_rate) {
+		dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
+		goto err_ref_clk;
+	}
+
+	if (ref_clk_rate == REF_CLK_27MHZ)
+		cdns_phy->ref_clk_rate = ref_clk_rate;
+	else {
+		dev_err(cdns_phy->dev, "Not support Ref Clock Rate(%dHz)\n", ref_clk_rate);
+		goto err_ref_clk;
+	}
+
+	ret = clk_prepare_enable(cdns_phy->apb_clk);
+	if (ret) {
+		dev_err(cdns_phy->dev, "Failed to prepare apb clock\n");
+		goto err_ref_clk;
+	}
+
+	return 0;
+
+err_ref_clk:
+	clk_disable_unprepare(cdns_phy->ref_clk);
+	return -EINVAL;
+}
+
+static void hdptx_dp_clk_disable(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	clk_disable_unprepare(cdns_phy->ref_clk);
+	clk_disable_unprepare(cdns_phy->apb_clk);
+}
+
+static void hdptx_dp_aux_cfg(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	/* Power up Aux */
+	cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 1);
+
+	cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_1, 0x3);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, 36);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA018);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030C);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0000);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x1001);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA098);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xA198);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f);
+}
+
+/* PMA common configuration for 27MHz */
+static void hdptx_dp_phy_pma_cmn_cfg_27mhz(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 num_lanes = cdns_phy->num_lanes;
+	u16 val;
+	int k;
+
+	val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+	val &= 0xFFF7;
+	val |= 0x0008;
+	cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
+
+	/* Startup state machine registers */
+	cdns_phy_reg_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0087);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLEN_TMR, 0x001B);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0036);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLVREF_TMR, 0x001B);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x006C);
+
+	/* Current calibration registers */
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_INIT_TMR, 0x0044);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_ITER_TMR, 0x0006);
+
+	/* Resistor calibration registers */
+	cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_ITER_TMR, 0x0006);
+
+	for (k = 0; k < num_lanes; k = k + 1) {
+		/* Power state machine registers */
+		cdns_phy_reg_write(cdns_phy, XCVR_PSM_CAL_TMR  | (k << 9), 0x016D);
+		cdns_phy_reg_write(cdns_phy, XCVR_PSM_A0IN_TMR | (k << 9), 0x016D);
+		/* Transceiver control and diagnostic registers */
+		cdns_phy_reg_write(cdns_phy, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x00A2);
+		cdns_phy_reg_write(cdns_phy, TX_DIAG_BGREF_PREDRV_DELAY    | (k << 9), 0x0097);
+		/* Transmitter receiver detect registers */
+		cdns_phy_reg_write(cdns_phy, TX_RCVDET_EN_TMR | (k << 9), 0x0A8C);
+		cdns_phy_reg_write(cdns_phy, TX_RCVDET_ST_TMR | (k << 9), 0x0036);
+	}
+
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
+}
+
+static void hdptx_dp_phy_pma_cmn_pll0_27mhz(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 num_lanes = cdns_phy->num_lanes;
+	u32 link_rate = cdns_phy->link_rate;
+	u16 val;
+	int index, i, k;
+
+	/* DP PLL data rate 0/1 clock divider value */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= 0x00FF;
+	if (link_rate <= RATE_2_7)
+		val |= 0x2400;
+	else
+		val |= 0x1200;
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+
+	/* High speed clock 0/1 div */
+	val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
+	val &= 0xFFCC;
+	if (link_rate <= RATE_2_7)
+		val |= 0x0011;
+	cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
+
+	for (k = 0; k < num_lanes; k++) {
+		val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
+		val = val & 0xCFFF;
+		if (link_rate <= RATE_2_7)
+			val |= 0x1000;
+		cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val);
+	}
+
+	/* DP PHY PLL 27MHz configuration */
+	index = link_rate_index(link_rate);
+	for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
+		cdns_phy_reg_write(cdns_phy, phy_pll_27m_cfg[i].addr,
+				phy_pll_27m_cfg[i].val[index]);
+
+	/* Transceiver control and diagnostic registers */
+	for (k = 0; k < num_lanes; k++) {
+		val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
+		val = val & 0x8FFF;
+		if (link_rate <= RATE_2_7)
+			val |= 0x2000;
+		else
+			val |= 0x1000;
+		cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);
+	}
+
+	for (k = 0; k < num_lanes; k = k + 1) {
+		/* Power state machine registers */
+		cdns_phy_reg_write(cdns_phy, (XCVR_PSM_RCTRL | (k << 9)),  0xBEFC);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A0 | (k << 9)), 0x6799);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A1 | (k << 9)), 0x6798);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A2 | (k << 9)), 0x0098);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A3 | (k << 9)), 0x0098);
+		/* Receiver calibration power state definition register */
+		val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
+		val &= 0xFFBB;
+		cdns_phy_reg_write(cdns_phy, (RX_PSC_CAL | (k << 9)), val);
+		val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0  | (k << 9));
+		val &= 0xFFBB;
+		cdns_phy_reg_write(cdns_phy, (RX_PSC_A0  | (k << 9)), val);
+	}
+}
+
+static void hdptx_dp_phy_ref_clock_type(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 val;
+
+	val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+	val &= 0xFF8F;
+	/*
+	 * single ended reference clock (val |= 0x0030);
+	 * differential clock  (val |= 0x0000);
+	 *
+	 * for differential clock on the refclk_p and
+	 * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
+	 * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
+	 */
+	val |= 0x0030;
+	cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
+}
+
+static int hdptx_dp_phy_power_up(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u32 val, i;
+
+	/* Enable HDP PLL’s for high speed clocks */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val |= (1 << 0);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL ready ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (val & (1 << 1))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL Ack failed\n");
+		return -1;
+	}
+
+	/* Enable HDP PLL’s data rate and full rate clocks out of PMA. */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val |= (1 << 2);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL clock enable ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (val & (1 << 3))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL clock enable ACk failed\n");
+		return -1;
+	}
+
+	/* Configure PHY in A2 Mode */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x0004);
+	/* Wait for Power State A2 Ack */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
+		if (val & (1 << 6))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait A2 Ack failed\n");
+		return -1;
+	}
+
+	/* Configure PHY in A0 mode (PHY must be in the A0 power
+	 * state in order to transmit data)
+	 */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x0101);
+
+	/* Wait for Power State A0 Ack */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
+		if (val & (1 << 4))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait A0 Ack failed\n");
+		return -1;
+	}
+
+	cdns_phy->power_up = true;
+
+	return 0;
+}
+
+static void hdptx_dp_phy_power_down(struct cdns_hdptx_dp_phy *cdns_phy)
+{
+	u16 val;
+	int i;
+
+	if (!cdns_phy->power_up)
+		return;
+
+	/* Place the PHY lanes in the A3 power state. */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, 0x8);
+	/* Wait for Power State A3 Ack */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
+		if (val & (1 << 7))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait A3 Ack failed\n");
+		return;
+	}
+
+	/* Disable HDP PLL’s data rate and full rate clocks out of PMA. */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= ~(1 << 2);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL clock gate ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (!(val & (1 << 3)))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL clock gate Ack failed\n");
+		return;
+	}
+
+	/* Disable HDP PLL’s for high speed clocks */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= ~(1 << 0);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	/* Wait for PLL disable ACK */
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+		if (!(val & (1 << 1)))
+			break;
+		msleep(20);
+	}
+	if (i == 10) {
+		dev_err(cdns_phy->dev, "Wait PLL disable Ack failed\n");
+		return;
+	}
+}
+
+static int cdns_hdptx_dp_phy_on(struct phy *phy)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+
+	return hdptx_dp_phy_power_up(cdns_phy);
+}
+
+static int cdns_hdptx_dp_phy_off(struct phy *phy)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+
+	hdptx_dp_phy_power_down(cdns_phy);
+
+	return 0;
+}
+
+static int cdns_hdptx_dp_phy_init(struct phy *phy)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+	int ret;
+
+	hdptx_dp_phy_ref_clock_type(cdns_phy);
+
+	/* PHY power up */
+	ret = hdptx_dp_phy_power_up(cdns_phy);
+	if (ret < 0)
+		return ret;
+
+	hdptx_dp_aux_cfg(cdns_phy);
+
+	return ret;
+}
+
+static int cdns_hdptx_dp_configure(struct phy *phy,
+				     union phy_configure_opts *opts)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
+	int ret;
+
+	cdns_phy->link_rate = opts->dp.link_rate;
+	cdns_phy->num_lanes = opts->dp.lanes;
+
+	if (cdns_phy->link_rate > MAX_LINK_RATE) {
+		dev_err(cdns_phy->dev, "Link Rate(%d) Not supported\n", cdns_phy->link_rate);
+		return false;
+	}
+
+	/* Disable phy clock if PHY in power up state */
+	hdptx_dp_phy_power_down(cdns_phy);
+
+	if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) {
+		hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy);
+		hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy);
+	} else
+		dev_err(cdns_phy->dev, "Not support ref clock rate\n");
+
+	/* PHY power up */
+	ret = hdptx_dp_phy_power_up(cdns_phy);
+
+	return ret;
+}
+
+static const struct phy_ops cdns_hdptx_dp_phy_ops = {
+	.init		= cdns_hdptx_dp_phy_init,
+	.configure	= cdns_hdptx_dp_configure,
+	.power_on	= cdns_hdptx_dp_phy_on,
+	.power_off	= cdns_hdptx_dp_phy_off,
+	.owner		= THIS_MODULE,
+};
+
+static int cdns_hdptx_dp_phy_probe(struct platform_device *pdev)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy;
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct phy_provider *phy_provider;
+	struct resource *res;
+	struct phy *phy;
+	int ret;
+
+	cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
+	if (!cdns_phy)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, cdns_phy);
+	cdns_phy->dev = dev;
+	mutex_init(&cdns_phy->mbox_mutex);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+	cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
+	if (IS_ERR(cdns_phy->regs))
+		return PTR_ERR(cdns_phy->regs);
+
+	phy = devm_phy_create(dev, node, &cdns_hdptx_dp_phy_ops);
+	if (IS_ERR(phy))
+		return PTR_ERR(phy);
+
+	phy->attrs.mode = PHY_MODE_DP;
+	cdns_phy->phy = phy;
+	phy_set_drvdata(phy, cdns_phy);
+
+	ret = hdptx_dp_clk_enable(cdns_phy);
+	if (ret) {
+		dev_err(dev, "Init clk fail\n");
+		return -EINVAL;
+	}
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+	if (IS_ERR(phy_provider)) {
+		ret =  PTR_ERR(phy_provider);
+		goto clk_disable;
+	}
+
+	return 0;
+
+clk_disable:
+	hdptx_dp_clk_disable(cdns_phy);
+
+	return -EINVAL;
+}
+
+static int cdns_hdptx_dp_phy_remove(struct platform_device *pdev)
+{
+	struct cdns_hdptx_dp_phy *cdns_phy = platform_get_drvdata(pdev);
+
+	hdptx_dp_clk_disable(cdns_phy);
+
+	return 0;
+}
+
+static const struct of_device_id cdns_hdptx_dp_phy_of_match[] = {
+	{.compatible = "fsl,imx8mq-dp-phy" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, cdns_hdptx_dp_phy_of_match);
+
+static struct platform_driver cdns_hdptx_dp_phy_driver = {
+	.probe	= cdns_hdptx_dp_phy_probe,
+	.remove = cdns_hdptx_dp_phy_remove,
+	.driver = {
+		.name	= "cdns-hdptx-dp-phy",
+		.of_match_table	= cdns_hdptx_dp_phy_of_match,
+	}
+};
+module_platform_driver(cdns_hdptx_dp_phy_driver);
+
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_DESCRIPTION("Cadence HDP-TX DisplayPort PHY driver");
+MODULE_LICENSE("GPL");

Signature · 1 line

2.34.1