Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ

Mailbox access functions in MHDP8546 will be share to other MHDP driver and Cadence HDP-TX HDMI/DP PHY drivers.

Create a new MHDP helper driver and move all mailbox access functions into. According the mailbox access sequence and type of security.
Six mailbox access API functions are introduced.
Three APIs for non-secure mailbox access:
- cdns_mhdp_mailbox_send()
- cdns_mhdp_mailbox_send_recv()
- cdns_mhdp_mailbox_send_recv_multi()
The other three APIs for secure mailbox access:
- cdns_mhdp_secure_mailbox_send()
- cdns_mhdp_secure_mailbox_send_recv()
- cdns_mhdp_secure_mailbox_send_recv_multi()

All MHDP commands that need to be passed through the mailbox have been rewritten using those new API functions.

The register read/write and DP DPCD read/write command functions are also included in this new helper driver.

Function cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(), because it use the DPTX command ID DPTX_WRITE_REGISTER.
New cdns_mhdp_reg_write() is added with the general command ID GENERAL_REGISTER_WRITE.

Signed-off-by Sandor Yu <[email protected]>

---
v17->v18:
- Create three ordinary mailbox access APIs cdns_mhdp_mailbox_send
cdns_mhdp_mailbox_send_recv cdns_mhdp_mailbox_send_recv_multi
- Create three secure mailbox access APIs cdns_mhdp_secure_mailbox_send cdns_mhdp_secure_mailbox_send_recv cdns_mhdp_secure_mailbox_send_recv_multi
- MHDP8546 DP and HDCP commands that need access mailbox are rewrited with above 6 API functions.

v16->v17:
- Replaces the local mutex mbox_mutex with a global mutex mhdp_mailbox_mutex

v12->v16:
*No change.

 drivers/gpu/drm/bridge/cadence/Kconfig        |   4 +
 drivers/gpu/drm/bridge/cadence/Makefile       |   1 +
 .../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 414 +++++++++++++++
 .../drm/bridge/cadence/cdns-mhdp8546-core.c   | 487 +++---------------
 .../drm/bridge/cadence/cdns-mhdp8546-core.h   |  47 +-
 .../drm/bridge/cadence/cdns-mhdp8546-hdcp.c   | 236 +--------
 .../drm/bridge/cadence/cdns-mhdp8546-hdcp.h   |  18 +-
 include/drm/bridge/cdns-mhdp-helper.h         | 130 +++++
 8 files changed, 658 insertions(+), 679 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
 create mode 100644 include/drm/bridge/cdns-mhdp-helper.h

drivers/gpu/drm/bridge/cadence/Kconfig +0 -0

index cced81633ddcd..e0973339e9e33 100644

drivers/gpu/drm/bridge/cadence/Kconfig +1 -0

 config DRM_CDNS_MHDP8546
 	tristate "Cadence DPI/DP bridge"
 	select DRM_DISPLAY_DP_HELPER

@@ -28,6 +31,7 @@ config DRM_CDNS_MHDP8546
 	select DRM_DISPLAY_HELPER
 	select DRM_KMS_HELPER
 	select DRM_PANEL_BRIDGE
+	select CDNS_MHDP_HELPER
 	depends on OF
 	help
 	  Support Cadence DPI to DP bridge. This is an internal

drivers/gpu/drm/bridge/cadence/Makefile +1 -0

index c95fd5b81d137..087dc074820d7 100644
@@ -2,6 +2,7 @@
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
 cdns-dsi-y := cdns-dsi-core.o
 cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
+obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o
 obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
 cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
 cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +56 -0

new file mode 100644
index 0000000000000..f39228a78c7cb
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, 2024 NXP Semiconductor, Inc.
+ *
+ */
+#include <drm/bridge/cdns-mhdp-helper.h>
+#include <linux/dev_printk.h>
+#include <linux/module.h>
+
+/* Protects mailbox communications with the firmware */
+static DEFINE_MUTEX(mhdp_mailbox_mutex);
+
+/* Mailbox helper functions */
+static int mhdp_mailbox_read(void __iomem *regs)
+{
+	int ret, empty;
+
+	WARN_ON(!mutex_is_locked(&mhdp_mailbox_mutex));
+
+	ret = readx_poll_timeout(readl, regs + CDNS_MAILBOX_EMPTY,
+				 empty, !empty, MAILBOX_RETRY_US,
+				 MAILBOX_TIMEOUT_US);
+	if (ret < 0)
+		return ret;
+
+	return readl(regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int mhdp_mailbox_write(void __iomem *regs, u8 val)
+{
+	int ret, full;
+
+	WARN_ON(!mutex_is_locked(&mhdp_mailbox_mutex));
+
+	ret = readx_poll_timeout(readl, regs + CDNS_MAILBOX_FULL,
+				 full, !full, MAILBOX_RETRY_US,
+				 MAILBOX_TIMEOUT_US);
+	if (ret < 0)
+		return ret;
+
+	writel(val, regs + CDNS_MAILBOX_TX_DATA);
+
+	return 0;
+}
+
+static int mhdp_mailbox_recv_header(void __iomem *regs,
+				    u8 module_id, u8 opcode,
+				    u16 req_size)
+{
+	u32 mbox_size, i;
+	u8 header[4];
+	int ret;
+
+	/* read the header of the message */
+	for (i = 0; i < sizeof(header); i++) {
+		ret = mhdp_mailbox_read(regs);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +46 -0

+		/*
+		 * If the message in mailbox is not what we want, we need to
+		 * clear the mailbox by reading its contents.
+		 */
+		for (i = 0; i < mbox_size; i++)
+			if (mhdp_mailbox_read(regs) < 0)
+				break;
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mhdp_mailbox_recv_data(void __iomem *regs,
+				  u8 *buff, u16 buff_size)
+{
+	u32 i;
+	int ret;
+
+	for (i = 0; i < buff_size; i++) {
+		ret = mhdp_mailbox_read(regs);
+		if (ret < 0)
+			return ret;
+
+		buff[i] = ret;
+	}
+
+	return 0;
+}
+
+static int mhdp_mailbox_send(void __iomem *regs, u8 module_id,
+			     u8 opcode, u16 size, u8 *message)
+{
+	u8 header[4];
+	int ret, i;
+
+	header[0] = opcode;
+	header[1] = module_id;
+	put_unaligned_be16(size, header + 2);
+
+	for (i = 0; i < sizeof(header); i++) {
+		ret = mhdp_mailbox_write(regs, header[i]);
+		if (ret)
+			return ret;
+	}

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +25 -0

+
+	ret = mhdp_mailbox_send(base->regs, module_id, opcode, size, message);
+
+	mutex_unlock(&mhdp_mailbox_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send);
+
+int cdns_mhdp_mailbox_send_recv(struct cdns_mhdp_base *base,
+				u8 module_id, u8 opcode,
+				u16 msg_size, u8 *msg,
+				u16 resp_size, u8 *resp)
+{
+	int ret;
+
+	mutex_lock(&mhdp_mailbox_mutex);
+
+	ret = mhdp_mailbox_send(base->regs, module_id,
+				opcode, msg_size, msg);
+	if (ret)
+		goto out;
+
+	ret = mhdp_mailbox_recv_header(base->regs, module_id,
+				       opcode, resp_size);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +104 -0

+int cdns_mhdp_mailbox_send_recv_multi(struct cdns_mhdp_base *base,
+				      u8 module_id, u8 opcode,
+				      u16 msg_size, u8 *msg,
+				      u8 opcode_resp,
+				      u16 resp1_size, u8 *resp1,
+				      u16 resp2_size, u8 *resp2)
+{
+	int ret;
+
+	mutex_lock(&mhdp_mailbox_mutex);
+
+	ret = mhdp_mailbox_send(base->regs, module_id,
+				opcode, msg_size, msg);
+	if (ret)
+		goto out;
+
+	ret = mhdp_mailbox_recv_header(base->regs, module_id, opcode_resp,
+				       resp1_size + resp2_size);
+	if (ret)
+		goto out;
+
+	ret = mhdp_mailbox_recv_data(base->regs, resp1, resp1_size);
+	if (ret)
+		goto out;
+
+	ret = mhdp_mailbox_recv_data(base->regs, resp2, resp2_size);
+out:
+	mutex_unlock(&mhdp_mailbox_mutex);
+
+	if (ret)
+		dev_err(base->dev, "ModuleID=%d, MSG_CMD=%d Resp_CMD=%d failed: %d\n",
+			module_id, opcode, opcode_resp, ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send_recv_multi);
+
+/*
+ * Secure mailbox access functions:
+ * These functions handle secure mailbox communication, which differs
+ * from non-secure mailbox access. They use the secure address.
+ */
+int cdns_mhdp_secure_mailbox_send(struct cdns_mhdp_base *base, u8 module_id,
+				  u8 opcode, u16 size, u8 *message)
+{
+	int ret;
+
+	mutex_lock(&mhdp_mailbox_mutex);
+
+	ret = mhdp_mailbox_send(base->sapb_regs, module_id, opcode, size, message);
+
+	mutex_unlock(&mhdp_mailbox_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_secure_mailbox_send);
+
+int cdns_mhdp_secure_mailbox_send_recv(struct cdns_mhdp_base *base,
+				       u8 module_id, u8 opcode,
+				       u16 msg_size, u8 *msg,
+				       u16 resp_size, u8 *resp)
+{
+	int ret;
+
+	mutex_lock(&mhdp_mailbox_mutex);
+
+	ret = mhdp_mailbox_send(base->sapb_regs, module_id,
+				opcode, msg_size, msg);
+	if (ret)
+		goto out;
+
+	ret = mhdp_mailbox_recv_header(base->sapb_regs, module_id,
+				       opcode, resp_size);
+	if (ret)
+		goto out;
+
+	ret = mhdp_mailbox_recv_data(base->sapb_regs, resp, resp_size);
+out:
+	mutex_unlock(&mhdp_mailbox_mutex);
+
+	if (ret)
+		dev_err(base->dev, "ModuleID=%d, CMD=%d failed: %d\n",
+			module_id, opcode, ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_secure_mailbox_send_recv);
+
+int cdns_mhdp_secure_mailbox_send_recv_multi(struct cdns_mhdp_base *base,
+					     u8 module_id, u8 opcode,
+					     u16 msg_size, u8 *msg,
+					     u8 opcode_resp,
+					     u16 resp1_size, u8 *resp1,
+					     u16 resp2_size, u8 *resp2)
+{
+	int ret;
+
+	mutex_lock(&mhdp_mailbox_mutex);
+
+	ret = mhdp_mailbox_send(base->sapb_regs, module_id,
+				opcode, msg_size, msg);
+	if (ret)
+		goto out;
+
+	ret = mhdp_mailbox_recv_header(base->sapb_regs, module_id,
+				       opcode_resp,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +59 -0

+		ret = mhdp_mailbox_recv_data(base->sapb_regs, resp2, 5 * resp1[0]);
+	else
+		ret = mhdp_mailbox_recv_data(base->sapb_regs, resp2, resp2_size);
+out:
+	mutex_unlock(&mhdp_mailbox_mutex);
+
+	if (ret)
+		dev_err(base->dev, "ModuleID=%d, CMD=%d failed: %d\n",
+			module_id, opcode, ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_secure_mailbox_send_recv_multi);
+
+/* General read/write helper functions */
+int cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32 *value)
+{
+	u8 msg[4], resp[8];
+	int ret;
+
+	put_unaligned_be32(addr, msg);
+
+	ret = cdns_mhdp_mailbox_send_recv(base, MB_MODULE_ID_GENERAL,
+					  GENERAL_REGISTER_READ,
+					  sizeof(msg), msg, sizeof(resp), resp);
+	if (ret)
+		goto out;
+
+	/* Returned address value should be the same as requested */
+	if (memcmp(msg, resp, sizeof(msg))) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	*value = get_unaligned_be32(resp + 4);
+out:
+	if (ret) {
+		dev_err(base->dev, "Failed to read register\n");
+		*value = 0;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_read);
+
+int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32 val)
+{
+	u8 msg[8];
+
+	put_unaligned_be32(addr, msg);
+	put_unaligned_be32(val, msg + 4);
+
+	return cdns_mhdp_mailbox_send(base, MB_MODULE_ID_GENERAL,
+				     GENERAL_REGISTER_WRITE,
+				     sizeof(msg), msg);
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_write);
+
+/* DPTX helper functions */
+int cdns_mhdp_dp_reg_write(struct cdns_mhdp_base *base, u16 addr, u32 val)

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +64 -0

+
+int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr,
+			       u8 start_bit, u8 bits_no, u32 val)
+{
+	u8 field[8];
+
+	put_unaligned_be16(addr, field);
+	field[2] = start_bit;
+	field[3] = bits_no;
+	put_unaligned_be32(val, field + 4);
+
+	return cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
+				      DPTX_WRITE_FIELD, sizeof(field), field);
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write_bit);
+
+int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base,
+			u32 addr, u8 *data, u16 len)
+{
+	u8 msg[5], reg[5];
+
+	put_unaligned_be16(len, msg);
+	put_unaligned_be24(addr, msg + 2);
+
+	return cdns_mhdp_mailbox_send_recv_multi(base,
+						 MB_MODULE_ID_DP_TX,
+						 DPTX_READ_DPCD,
+						 sizeof(msg), msg,
+						 DPTX_READ_DPCD,
+						 sizeof(reg), reg,
+						 len, data);
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_read);
+
+int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8 value)
+{
+	u8 msg[6], reg[5];
+	int ret;
+
+	put_unaligned_be16(1, msg);
+	put_unaligned_be24(addr, msg + 2);
+	msg[5] = value;
+
+	ret = cdns_mhdp_mailbox_send_recv(base, MB_MODULE_ID_DP_TX,
+					  DPTX_WRITE_DPCD,
+					  sizeof(msg), msg, sizeof(reg), reg);
+	if (ret) {
+		dev_err(base->dev, "dpcd write failed: %d\n", ret);
+		return ret;
+	}
+
+	if (addr != get_unaligned_be24(reg + 2)) {
+		dev_err(base->dev, "Invalid response: expected address 0x%06x, got 0x%06x\n",
+			addr, get_unaligned_be24(reg + 2));
+		return -EINVAL;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_write);
+
+MODULE_DESCRIPTION("Cadence MHDP Helper driver");
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_LICENSE("GPL");

Quoted 4 lines

Mailbox access functions in MHDP8546 will be share to other MHDP driver and Cadence HDP-TX HDMI/DP PHY drivers.

Create a new MHDP helper driver and move all mailbox access functions

into.

Quoted 23 lines

According the mailbox access sequence and type of security. Six mailbox access API functions are introduced. Three APIs for non-secure mailbox access:
- cdns_mhdp_mailbox_send()
- cdns_mhdp_mailbox_send_recv()
- cdns_mhdp_mailbox_send_recv_multi()
The other three APIs for secure mailbox access:
- cdns_mhdp_secure_mailbox_send()
- cdns_mhdp_secure_mailbox_send_recv()
- cdns_mhdp_secure_mailbox_send_recv_multi()

All MHDP commands that need to be passed through the mailbox have been rewritten using those new API functions.

The register read/write and DP DPCD read/write command functions are also included in this new helper driver.

Function cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(), because it use the DPTX command ID DPTX_WRITE_REGISTER.
New cdns_mhdp_reg_write() is added with the general command ID GENERAL_REGISTER_WRITE.

Signed-off-by Sandor Yu <[email protected]>

Quoted 11 lines

---
v17->v18:
- Create three ordinary mailbox access APIs cdns_mhdp_mailbox_send cdns_mhdp_mailbox_send_recv cdns_mhdp_mailbox_send_recv_multi
- Create three secure mailbox access APIs cdns_mhdp_secure_mailbox_send cdns_mhdp_secure_mailbox_send_recv cdns_mhdp_secure_mailbox_send_recv_multi
- MHDP8546 DP and HDCP commands that need access mailbox are

rewrited

Quoted 6 lines

with above 6 API functions.

v16->v17:
- Replaces the local mutex mbox_mutex with a global mutex mhdp_mailbox_mutex

Quoted 6 lines

v12->v16:
*No change.

 drivers/gpu/drm/bridge/cadence/Kconfig        |   4 +
 drivers/gpu/drm/bridge/cadence/Makefile       |   1 +
 .../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 414

+++++++++++++++

Quoted 18 lines

 .../drm/bridge/cadence/cdns-mhdp8546-core.c   | 487 +++---------------
 .../drm/bridge/cadence/cdns-mhdp8546-core.h   |  47 +-
 .../drm/bridge/cadence/cdns-mhdp8546-hdcp.c   | 236 +--------
 .../drm/bridge/cadence/cdns-mhdp8546-hdcp.h   |  18 +-
 include/drm/bridge/cdns-mhdp-helper.h         | 130 +++++
 8 files changed, 658 insertions(+), 679 deletions(-)  create mode
100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
 create mode 100644 include/drm/bridge/cdns-mhdp-helper.h

drivers/gpu/drm/bridge/cadence/Kconfig +0 -0

index cced81633ddcd..e0973339e9e33 100644
@@ -21,6 +21,9 @@ config DRM_CDNS_DSI_J721E
        the routing of the DSS DPI signal to the Cadence DSI.
 endif
 

drivers/gpu/drm/bridge/cadence/Kconfig config DRM_CDNS_DSI_J721E · line 26

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/Kconfig +3 -0

+config CDNS_MHDP_HELPER
+     tristate
+

I'm not sure if the placement for the helper is suitable. Especially if you want to reuse the helper by some other subsystem. As far as I don't like it, maybe drivers/soc is a better option.

Quoted 19 lines

drivers/gpu/drm/bridge/cadence/Kconfig +1 -1

 config DRM_CDNS_MHDP8546
      tristate "Cadence DPI/DP bridge"
      select DRM_DISPLAY_DP_HELPER

@@ -28,6 +31,7 @@ config DRM_CDNS_MHDP8546
      select DRM_DISPLAY_HELPER
      select DRM_KMS_HELPER
      select DRM_PANEL_BRIDGE
+     select CDNS_MHDP_HELPER
      depends on OF
      help
        Support Cadence DPI to DP bridge. This is an internal diff
--git a/drivers/gpu/drm/bridge/cadence/Makefile

b/drivers/gpu/drm/bridge/cadence/Makefile
index c95fd5b81d137..087dc074820d7 100644

drivers/gpu/drm/bridge/cadence/Makefile +0 -0

@@ -2,6 +2,7 @@
 obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o  cdns-dsi-y :=

Quoted 4 lines

cdns-dsi-core.o
cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
+obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o

cdns-mhdp8546-y

Quoted 66 lines

:= cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) +=
cdns-mhdp8546-j721e.o diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file mode 100644
index 0000000000000..f39228a78c7cb

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +56 -0

@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, 2024 NXP Semiconductor, Inc.
+ *
+ */
+#include <drm/bridge/cdns-mhdp-helper.h> #include
+<linux/dev_printk.h> #include <linux/module.h>
+
+/* Protects mailbox communications with the firmware */ static
+DEFINE_MUTEX(mhdp_mailbox_mutex);
+
+/* Mailbox helper functions */
+static int mhdp_mailbox_read(void __iomem *regs) {
+     int ret, empty;
+
+     WARN_ON(!mutex_is_locked(&mhdp_mailbox_mutex));
+
+     ret = readx_poll_timeout(readl, regs + CDNS_MAILBOX_EMPTY,
+                              empty, !empty, MAILBOX_RETRY_US,
+                              MAILBOX_TIMEOUT_US);
+     if (ret < 0)
+             return ret;
+
+     return readl(regs + CDNS_MAILBOX_RX_DATA) & 0xff; }
+
+static int mhdp_mailbox_write(void __iomem *regs, u8 val) {
+     int ret, full;
+
+     WARN_ON(!mutex_is_locked(&mhdp_mailbox_mutex));
+
+     ret = readx_poll_timeout(readl, regs + CDNS_MAILBOX_FULL,
+                              full, !full, MAILBOX_RETRY_US,
+                              MAILBOX_TIMEOUT_US);
+     if (ret < 0)
+             return ret;
+
+     writel(val, regs + CDNS_MAILBOX_TX_DATA);
+
+     return 0;
+}
+
+static int mhdp_mailbox_recv_header(void __iomem *regs,
+                                 u8 module_id, u8 opcode,
+                                 u16 req_size) {
+     u32 mbox_size, i;
+     u8 header[4];
+     int ret;
+
+     /* read the header of the message */
+     for (i = 0; i < sizeof(header); i++) {
+             ret = mhdp_mailbox_read(regs);
+             if (ret < 0)
+                     return ret;
+
+             header[i] = ret;
+     }

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +6 -0

+
+     mbox_size = get_unaligned_be16(header + 2);
+
+     if (opcode != header[0] || module_id != header[1] ||
+        (opcode != HDCP_TRAN_IS_REC_ID_VALID && req_size !=
+ mbox_size)) {

Could you please explain the second clause?

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 64

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +2 -0

+             /*
+              * If the message in mailbox is not what we want, we

need to

Quoted 47 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +47 -0

+              * clear the mailbox by reading its contents.
+              */
+             for (i = 0; i < mbox_size; i++)
+                     if (mhdp_mailbox_read(regs) < 0)
+                             break;
+
+             return -EINVAL;
+     }
+
+     return 0;
+}
+
+static int mhdp_mailbox_recv_data(void __iomem *regs,
+                               u8 *buff, u16 buff_size) {
+     u32 i;
+     int ret;
+
+     for (i = 0; i < buff_size; i++) {
+             ret = mhdp_mailbox_read(regs);
+             if (ret < 0)
+                     return ret;
+
+             buff[i] = ret;
+     }
+
+     return 0;
+}
+
+static int mhdp_mailbox_send(void __iomem *regs, u8 module_id,
+                          u8 opcode, u16 size, u8 *message) {
+     u8 header[4];
+     int ret, i;
+
+     header[0] = opcode;
+     header[1] = module_id;
+     put_unaligned_be16(size, header + 2);
+
+     for (i = 0; i < sizeof(header); i++) {
+             ret = mhdp_mailbox_write(regs, header[i]);
+             if (ret)
+                     return ret;
+     }
+
+     for (i = 0; i < size; i++) {
+             ret = mhdp_mailbox_write(regs, message[i]);
+             if (ret)
+                     return ret;

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 45

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +5 -0

+     }
+
+     return 0;
+}
+

Please add kerneldocs for all new API. It's obvious for the simple ones, but not for the more complex functions.

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 117

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, u8

module_id,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 128

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +4 -0

+                        u8 opcode, u16 size, u8 *message) {
+     int ret;
+
+     mutex_lock(&mhdp_mailbox_mutex);

guard(mutex)(&mhdp_mailbox_mutex);

return mhdp_mailbox_send(...);

Similar changes can be applied further on.

Quoted 25 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +24 -0

+
+     ret = mhdp_mailbox_send(base->regs, module_id, opcode, size,
+ message);
+
+     mutex_unlock(&mhdp_mailbox_mutex);
+
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send);
+
+int cdns_mhdp_mailbox_send_recv(struct cdns_mhdp_base *base,
+                             u8 module_id, u8 opcode,
+                             u16 msg_size, u8 *msg,
+                             u16 resp_size, u8 *resp) {
+     int ret;
+
+     mutex_lock(&mhdp_mailbox_mutex);
+
+     ret = mhdp_mailbox_send(base->regs, module_id,
+                             opcode, msg_size, msg);
+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_header(base->regs, module_id,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+                                    opcode, resp_size);
+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_data(base->regs, resp, resp_size);
+out:
+     mutex_unlock(&mhdp_mailbox_mutex);
+
+     if (ret)
+             dev_err(base->dev, "ModuleID=%d, CMD=%d

failed: %d\n",

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 156

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+                     module_id, opcode, ret);

Using guard() would allow you to use precise messages, e.g. failed to send, failed to received header, failed to receive data.

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 167

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +4 -0

+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send_recv);
+

Like what is _multi? Why do you need to fetch into two separate buffers? Can you fetch into one and then parse it accordingly? Please don't make the API more complicated than necessary.

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +6 -0

+int cdns_mhdp_mailbox_send_recv_multi(struct cdns_mhdp_base *base,
+                                   u8 module_id, u8 opcode,
+                                   u16 msg_size, u8 *msg,
+                                   u8 opcode_resp,
+                                   u16 resp1_size, u8 *resp1,
+                                   u16 resp2_size, u8 *resp2) {

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+     int ret;
+
+     mutex_lock(&mhdp_mailbox_mutex);
+
+     ret = mhdp_mailbox_send(base->regs, module_id,
+                             opcode, msg_size, msg);
+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_header(base->regs, module_id,

opcode_resp,

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +4 -0

+                                    resp1_size + resp2_size);
+     if (ret)
+             goto out;
+

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+     ret = mhdp_mailbox_recv_data(base->regs, resp1, resp1_size);
+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_data(base->regs, resp2, resp2_size);
+out:
+     mutex_unlock(&mhdp_mailbox_mutex);
+
+     if (ret)
+             dev_err(base->dev, "ModuleID=%d, MSG_CMD=%d

Resp_CMD=%d failed: %d\n",

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +11 -0

+                     module_id, opcode, opcode_resp, ret);
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send_recv_multi);
+
+/*
+ * Secure mailbox access functions:
+ * These functions handle secure mailbox communication, which differs
+ * from non-secure mailbox access. They use the secure address.
+ */
+int cdns_mhdp_secure_mailbox_send(struct cdns_mhdp_base *base, u8

module_id,

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +5 -0

+                               u8 opcode, u16 size, u8 *message) {
+     int ret;
+
+     mutex_lock(&mhdp_mailbox_mutex);
+

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+     ret = mhdp_mailbox_send(base->sapb_regs, module_id, opcode,
+ size, message);
+
+     mutex_unlock(&mhdp_mailbox_mutex);
+
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_secure_mailbox_send);
+
+int cdns_mhdp_secure_mailbox_send_recv(struct cdns_mhdp_base

*base,

Quoted 13 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +13 -0

+                                    u8 module_id, u8 opcode,
+                                    u16 msg_size, u8 *msg,
+                                    u16 resp_size, u8 *resp) {
+     int ret;
+
+     mutex_lock(&mhdp_mailbox_mutex);
+
+     ret = mhdp_mailbox_send(base->sapb_regs, module_id,
+                             opcode, msg_size, msg);
+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_header(base->sapb_regs, module_id,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+                                    opcode, resp_size);
+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_data(base->sapb_regs, resp, resp_size);
+out:
+     mutex_unlock(&mhdp_mailbox_mutex);
+
+     if (ret)
+             dev_err(base->dev, "ModuleID=%d, CMD=%d

failed: %d\n",

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +6 -0

+                     module_id, opcode, ret);
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_secure_mailbox_send_recv);
+
+int cdns_mhdp_secure_mailbox_send_recv_multi(struct cdns_mhdp_base

*base,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 246

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+                                          u8 module_id, u8

opcode,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 247

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+                                          u16 msg_size, u8

*msg,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 249

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +2 -0

+                                          u8 opcode_resp,
+                                          u16 resp1_size, u8

*resp1,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 250

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+                                          u16 resp2_size, u8

*resp2)

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +7 -0

+{
+     int ret;
+
+     mutex_lock(&mhdp_mailbox_mutex);
+
+     ret = mhdp_mailbox_send(base->sapb_regs, module_id,
+                             opcode, msg_size, msg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_header(base->sapb_regs, module_id,
+                                    opcode_resp,
+                                    resp1_size + resp2_size);
+     if (ret)
+             goto out;
+
+     ret = mhdp_mailbox_recv_data(base->sapb_regs, resp1,

resp1_size);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 281

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +5 -0

+     if (ret)
+             goto out;
+
+     if (module_id == MB_MODULE_ID_HDCP_TX &&
+         opcode == HDCP_TRAN_IS_REC_ID_VALID)

comment, please.

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 273

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+             ret = mhdp_mailbox_recv_data(base->sapb_regs, resp2, 5

* resp1[0]);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 8 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +8 -0

+     else
+             ret = mhdp_mailbox_recv_data(base->sapb_regs, resp2,
+resp2_size);
+out:
+     mutex_unlock(&mhdp_mailbox_mutex);
+
+     if (ret)
+             dev_err(base->dev, "ModuleID=%d, CMD=%d

failed: %d\n",

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +7 -0

+                     module_id, opcode, ret);
+     return ret;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_secure_mailbox_send_recv_multi);
+
+/* General read/write helper functions */ int
+cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32

*value)

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +7 -0

+{
+     u8 msg[4], resp[8];
+     int ret;
+
+     put_unaligned_be32(addr, msg);
+
+     ret = cdns_mhdp_mailbox_send_recv(base,

MB_MODULE_ID_GENERAL,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 296

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+

GENERAL_REGISTER_READ,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 297

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+                                       sizeof(msg), msg,

sizeof(resp), resp);

Quoted 18 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +18 -0

+     if (ret)
+             goto out;
+
+     /* Returned address value should be the same as requested */
+     if (memcmp(msg, resp, sizeof(msg))) {
+             ret = -EINVAL;
+             goto out;
+     }
+
+     *value = get_unaligned_be32(resp + 4);
+out:
+     if (ret) {
+             dev_err(base->dev, "Failed to read register\n");
+             *value = 0;
+     }
+
+     return ret;
+}

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_read);
+
+int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32
+val) {
+     u8 msg[8];
+
+     put_unaligned_be32(addr, msg);
+     put_unaligned_be32(val, msg + 4);
+
+     return cdns_mhdp_mailbox_send(base,

MB_MODULE_ID_GENERAL,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +6 -0

+                                  GENERAL_REGISTER_WRITE,
+                                  sizeof(msg), msg); }
+EXPORT_SYMBOL_GPL(cdns_mhdp_reg_write);
+
+/* DPTX helper functions */
+int cdns_mhdp_dp_reg_write(struct cdns_mhdp_base *base, u16 addr,

u32

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 8 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +8 -0

+val) {
+     u8 msg[6];
+
+     put_unaligned_be16(addr, msg);
+     put_unaligned_be32(val, msg + 2);
+
+     return cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
+                                   DPTX_WRITE_REGISTER,

sizeof(msg),

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 340

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+msg); } EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write);

Please don't add API without a user. If the function is required in the following patch, add it there.

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 13 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +12 -0

+
+int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr,
+                            u8 start_bit, u8 bits_no, u32 val) {
+     u8 field[8];
+
+     put_unaligned_be16(addr, field);
+     field[2] = start_bit;
+     field[3] = bits_no;
+     put_unaligned_be32(val, field + 4);
+
+     return cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
+                                   DPTX_WRITE_FIELD,

sizeof(field),

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 384

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +11 -0

+field); } EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write_bit);
+
+int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base,
+                     u32 addr, u8 *data, u16 len) {
+     u8 msg[5], reg[5];
+
+     put_unaligned_be16(len, msg);
+     put_unaligned_be24(addr, msg + 2);
+
+     return cdns_mhdp_mailbox_send_recv_multi(base,
+

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 364

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +1 -0

+

DPTX_READ_DPCD,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 384

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +2 -0

+                                              sizeof(msg), msg,
+

DPTX_READ_DPCD,

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +4 -0

+                                              sizeof(reg), reg,
+                                              len, data); }
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_read);
+

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +10 -0

+int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8
+value) {
+     u8 msg[6], reg[5];
+     int ret;
+
+     put_unaligned_be16(1, msg);
+     put_unaligned_be24(addr, msg + 2);
+     msg[5] = value;
+
+     ret = cdns_mhdp_mailbox_send_recv(base,

MB_MODULE_ID_DP_TX,

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 382

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +2 -0

+                                       DPTX_WRITE_DPCD,
+                                       sizeof(msg), msg,

sizeof(reg), reg);

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +7 -0

+     if (ret) {
+             dev_err(base->dev, "dpcd write failed: %d\n", ret);
+             return ret;
+     }
+
+     if (addr != get_unaligned_be24(reg + 2)) {
+             dev_err(base->dev, "Invalid response: expected address

0x%06x, got 0x%06x\n",

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c line 414

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file +11 -0

+                     addr, get_unaligned_be24(reg + 2));
+             return -EINVAL;
+     }
+
+     return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_write);
+
+MODULE_DESCRIPTION("Cadence MHDP Helper driver");
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_LICENSE("GPL");

--
With best wishes
Dmitry

Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union.

The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users.

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +5 -0

+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +10 -0

+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 46

Quoted 5 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +5 -0

+  data-lanes:
+    $ref: /schemas/media/video-interfaces.yaml#/properties/data-lanes
+    minItems: 4
+    maxItems: 4
+    description: Lane reordering for HDMI or DisplayPort interface.

Please look how existing bindings do it. data-lanes is a property of port. Otherwise why would you like this to be applied to the input?

Best regards,
Krzysztof

Quoted 12 lines · Sandor Yu

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +10 -0

+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+

Quoted 8 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 46

Quoted 5 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +5 -0

+  data-lanes:
+    $ref: /schemas/media/video-interfaces.yaml#/properties/data-lanes
+    minItems: 4
+    maxItems: 4
+    description: Lane reordering for HDMI or DisplayPort interface.

Please look how existing bindings do it. data-lanes is a property of port. Otherwise why would you like this to be applied to the input?

'lane reordering' is a feature of the MHDP IP, and different boards have different mappings.

Benjamin comments in v16, the imx8mq-zii-ultra board's lane mapping differs from the default in my driver, so we need to treat it as an input.

As data-lanes is a property of port, so there is no exist property could be reused,

How about revert 'data-lanes' back to my previous implementation of 'lane-mapping'?

Quoted 14 lines

Quoted 6 lines · Sandor Yu

Quoted 4 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +4 -0

+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.

Quoted 8 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

Quoted 8 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +8 -0

+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  data-lanes:
+    $ref:

/schemas/media/video-interfaces.yaml#/properties/data-lanes

Quoted 8 lines

Quoted 6 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 46

Quoted 3 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +3 -0

+    minItems: 4
+    maxItems: 4
+    description: Lane reordering for HDMI or DisplayPort interface.

Please look how existing bindings do it. data-lanes is a property of port. Otherwise why would you like this to be applied to the input?

'lane reordering' is a feature of the MHDP IP, and different boards have

different mappings.

Yeah, and?

Quoted 3 lines

Benjamin comments in v16, the imx8mq-zii-ultra board's lane mapping differs from the default in my driver, so we need to treat it as an input.

But HDMI is not your input port. At least that's what few lines below! This is confusing.

Quoted 3 lines

As data-lanes is a property of port, so there is no exist property could be reused,

data-lanes, really, what is the problem here?

Quoted 1 line

How about revert 'data-lanes' back to my previous implementation of

'lane-mapping'?

No.

Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.

Signed-off-by Sandor Yu <[email protected]>

---
v17->v18:
- remove lane-mapping and replace it with data-lanes
- remove r-b tag as property changed.

v16->v17:
- Add lane-mapping property

v9->v16:
*No change

 .../display/bridge/cdns,mhdp8501.yaml         | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +36 -0

new file mode 100644
index 0000000000000..e4b900ecf1ac9
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8501.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP8501 DP/HDMI bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  Cadence MHDP8501 DisplayPort/HDMI interface.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mq-mhdp8501
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: MHDP8501 DP/HDMI APB clock.
+
+  phys:
+    maxItems: 1
+    description:
+      phandle to the DP/HDMI PHY
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +34 -0

+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Input port from display controller output.
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port to DisplayPort or HDMI connector.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+  - phys
+  - data-lanes
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +22 -0

+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mhdp_in: endpoint {
+                    remote-endpoint = <&dcss_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                mhdp_out: endpoint {
+                    remote-endpoint = <&dp_connector>;
+                };
+            };
+        };
+    };

Signature · 1 line

2.34.1

Quoted 65 lines · Sandor Yu

Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.

Signed-off-by Sandor Yu <[email protected]>

---
v17->v18:
- remove lane-mapping and replace it with data-lanes
- remove r-b tag as property changed.

v16->v17:
- Add lane-mapping property

v9->v16:
*No change

 .../display/bridge/cdns,mhdp8501.yaml         | 112 ++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +41 -0

new file mode 100644
index 0000000000000..e4b900ecf1ac9
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8501.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP8501 DP/HDMI bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  Cadence MHDP8501 DisplayPort/HDMI interface.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mq-mhdp8501
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: MHDP8501 DP/HDMI APB clock.
+
+  phys:
+    maxItems: 1
+    description:
+      phandle to the DP/HDMI PHY
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 46

Quoted 5 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +5 -0

+  data-lanes:
+    $ref: /schemas/media/video-interfaces.yaml#/properties/data-lanes
+    minItems: 4
+    maxItems: 4
+    description: Lane reordering for HDMI or DisplayPort interface.

So, HDMI or DP port? I don't think the format is actually the same, so it is either-or.

Quoted 8 lines

Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.

Signed-off-by Sandor Yu <[email protected]>

---
v17->v18:
- remove lane-mapping and replace it with data-lanes
- remove r-b tag as property changed.

Quoted 7 lines

v16->v17:
- Add lane-mapping property

v9->v16:
*No change

 .../display/bridge/cdns,mhdp8501.yaml         | 112

++++++++++++++++++

Quoted 11 lines

 1 file changed, 112 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file mode 100644
index 0000000000000..e4b900ecf1ac9
--- /dev/null
+++

b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.y

Review line 4

Quoted 7 lines

+++ aml

(quoted diff) +4 -0

@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
+---
+$id:
+https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi

+cetree.org%2Fschemas%2Fdisplay%2Fbridge%2Fcdns%2Cmhdp8501.yaml% 23&dat

Quoted 1 line

+a=05%7C02%7CSandor.yu%40nxp.com%7Cda19a2cbbf2148c7f6f208dcf9e6 050f%7C

Quoted 1 line

+686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63866001353856588 4%7CUnkno

Quoted 1 line

+wn%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1 haWwi

Quoted 1 line

+LCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=WZvYuredQsK8abMP4bFoWGF a2DXUgzD0k5D

Review

Quoted 4 lines

(quoted diff) +3 -0

+MNnMdc3M%3D&reserved=0
+$schema:
+https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi

+cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C02%7CSandor. yu%40n

Quoted 1 line

+xp.com%7Cda19a2cbbf2148c7f6f208dcf9e6050f%7C686ea1d3bc2b4c6fa92 cd99c5

Quoted 1 line

+c301635%7C0%7C0%7C638660013538587632%7CUnknown%7CTWFpbGZs b3d8eyJWIjoi

Quoted 1 line

+MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0 %7C%7C%

Quoted 1 line

+7C&sdata=OVinvIp2pzVTtMo%2FA6jsMaypCUch31CA0PhINPOx%2FrU%3D& reserved=

Quoted 32 lines

+0

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +31 -0

+
+title: Cadence MHDP8501 DP/HDMI bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  Cadence MHDP8501 DisplayPort/HDMI interface.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8mq-mhdp8501
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: MHDP8501 DP/HDMI APB clock.
+
+  phys:
+    maxItems: 1
+    description:
+      phandle to the DP/HDMI PHY
+
+  interrupts:
+    items:
+      - description: Hotplug cable plugin.
+      - description: Hotplug cable plugout.
+

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 46

Quoted 10 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +10 -0

+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  data-lanes:
+    $ref: /schemas/media/video-interfaces.yaml#/properties/data-lanes
+    minItems: 4
+    maxItems: 4
+    description: Lane reordering for HDMI or DisplayPort interface.

So, HDMI or DP port? I don't think the format is actually the same, so it is either-or.

Quoted 38 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +38 -0

+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Input port from display controller output.
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port to DisplayPort or HDMI connector.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - interrupt-names
+  - phys
+  - data-lanes
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    mhdp: display-bridge@32c00000 {
+        compatible = "fsl,imx8mq-mhdp8501";
+        reg = <0x32c00000 0x100000>;

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml line 90

Quoted 6 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +6 -0

+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "plug_in", "plug_out";
+        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+        phys = <&mdhp_phy>;
+        data-lanes = <1 2 3 4>;

0 1 2 3

Quoted 24 lines

Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml new file +22 -1

+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                mhdp_in: endpoint {
+                    remote-endpoint = <&dcss_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+
+                mhdp_out: endpoint {
+                    remote-endpoint = <&dp_connector>;
+                };
+            };
+        };
+    };
--

Quoted 2 lines

2.34.1

--
With best wishes
Dmitry

Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.

Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort or HDMI PHY mode is configured in the driver.

Signed-off-by Sandor Yu <[email protected]>

Signed-off-by Alexander Stein <[email protected]>

---
v17->v18:
- fix build error as code rebase to latest kernel version.

 drivers/phy/freescale/Kconfig                |   10 +
 drivers/phy/freescale/Makefile               |    1 +
 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1337 ++++++++++++++++++
 3 files changed, 1348 insertions(+)
 create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c

drivers/phy/freescale/Kconfig +0 -0

index dcd9acff6d01a..2b1210367b31c 100644

drivers/phy/freescale/Kconfig +4 -0

+	help
+	  Enable this to support the Cadence HDPTX DP/HDMI PHY driver
+	  on i.MX8MQ SOC.
+
 config PHY_FSL_IMX8QM_HSIO
 	tristate "Freescale i.MX8QM HSIO PHY"
 	depends on OF && HAS_IOMEM

drivers/phy/freescale/Makefile +1 -0

index 658eac7d0a622..a946b87905498 100644
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_PHY_FSL_IMX8MQ_HDPTX)	+= phy-fsl-imx8mq-hdptx.o
 obj-$(CONFIG_PHY_FSL_IMX8MQ_USB)	+= phy-fsl-imx8mq-usb.o
 obj-$(CONFIG_PHY_MIXEL_LVDS_PHY)	+= phy-fsl-imx8qm-lvds-phy.o
 obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)	+= phy-fsl-imx8-mipi-dphy.o

drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c new file +255 -0

new file mode 100644
index 0000000000000..7aac39df0ab02
@@ -0,0 +1,1337 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence DP/HDMI PHY driver
+ *
+ * Copyright (C) 2022-2024 NXP Semiconductor, Inc.
+ */
+#include <drm/bridge/cdns-mhdp-helper.h>
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/unaligned.h>
+
+#define ADDR_PHY_AFE	0x80000
+
+/* PHY registers */
+#define CMN_SSM_BIAS_TMR			0x0022
+#define CMN_PLLSM0_PLLEN_TMR			0x0029
+#define CMN_PLLSM0_PLLPRE_TMR			0x002a
+#define CMN_PLLSM0_PLLVREF_TMR			0x002b
+#define CMN_PLLSM0_PLLLOCK_TMR			0x002c
+#define CMN_PLLSM0_USER_DEF_CTRL		0x002f
+#define CMN_PSM_CLK_CTRL			0x0061
+#define CMN_CDIAG_REFCLK_CTRL			0x0062
+#define CMN_PLL0_VCOCAL_START			0x0081
+#define CMN_PLL0_VCOCAL_INIT_TMR		0x0084
+#define CMN_PLL0_VCOCAL_ITER_TMR		0x0085
+#define CMN_PLL0_INTDIV				0x0094
+#define CMN_PLL0_FRACDIV			0x0095
+#define CMN_PLL0_HIGH_THR			0x0096
+#define CMN_PLL0_DSM_DIAG			0x0097
+#define CMN_PLL0_SS_CTRL2			0x0099
+#define CMN_ICAL_INIT_TMR			0x00c4
+#define CMN_ICAL_ITER_TMR			0x00c5
+#define CMN_RXCAL_INIT_TMR			0x00d4
+#define CMN_RXCAL_ITER_TMR			0x00d5
+#define CMN_TXPUCAL_CTRL			0x00e0
+#define CMN_TXPUCAL_INIT_TMR			0x00e4
+#define CMN_TXPUCAL_ITER_TMR			0x00e5
+#define CMN_TXPDCAL_CTRL			0x00f0
+#define CMN_TXPDCAL_INIT_TMR			0x00f4
+#define CMN_TXPDCAL_ITER_TMR			0x00f5
+#define CMN_ICAL_ADJ_INIT_TMR			0x0102
+#define CMN_ICAL_ADJ_ITER_TMR			0x0103
+#define CMN_RX_ADJ_INIT_TMR			0x0106
+#define CMN_RX_ADJ_ITER_TMR			0x0107
+#define CMN_TXPU_ADJ_CTRL			0x0108
+#define CMN_TXPU_ADJ_INIT_TMR			0x010a
+#define CMN_TXPU_ADJ_ITER_TMR			0x010b
+#define CMN_TXPD_ADJ_CTRL			0x010c
+#define CMN_TXPD_ADJ_INIT_TMR			0x010e
+#define CMN_TXPD_ADJ_ITER_TMR			0x010f
+#define CMN_DIAG_PLL0_FBH_OVRD			0x01c0
+#define CMN_DIAG_PLL0_FBL_OVRD			0x01c1
+#define CMN_DIAG_PLL0_OVRD			0x01c2
+#define CMN_DIAG_PLL0_TEST_MODE			0x01c4
+#define CMN_DIAG_PLL0_V2I_TUNE			0x01c5
+#define CMN_DIAG_PLL0_CP_TUNE			0x01c6
+#define CMN_DIAG_PLL0_LF_PROG			0x01c7
+#define CMN_DIAG_PLL0_PTATIS_TUNE1		0x01c8
+#define CMN_DIAG_PLL0_PTATIS_TUNE2		0x01c9
+#define CMN_DIAG_PLL0_INCLK_CTRL		0x01ca
+#define CMN_DIAG_PLL0_PXL_DIVH			0x01cb
+#define CMN_DIAG_PLL0_PXL_DIVL			0x01cc
+#define CMN_DIAG_HSCLK_SEL			0x01e0
+#define CMN_DIAG_PER_CAL_ADJ			0x01ec
+#define CMN_DIAG_CAL_CTRL			0x01ed
+#define CMN_DIAG_ACYA				0x01ff
+#define XCVR_PSM_RCTRL				0x4001
+#define XCVR_PSM_CAL_TMR			0x4002
+#define XCVR_PSM_A0IN_TMR			0x4003
+#define TX_TXCC_CAL_SCLR_MULT_0			0x4047
+#define TX_TXCC_CPOST_MULT_00_0			0x404c
+#define XCVR_DIAG_PLLDRC_CTRL			0x40e0
+#define XCVR_DIAG_HSCLK_SEL			0x40e1
+#define XCVR_DIAG_BIDI_CTRL			0x40e8
+#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR		0x40f2
+#define TX_PSC_A0				0x4100
+#define TX_PSC_A1				0x4101
+#define TX_PSC_A2				0x4102
+#define TX_PSC_A3				0x4103
+#define TX_RCVDET_EN_TMR			0x4122
+#define TX_RCVDET_ST_TMR			0x4123
+#define TX_DIAG_TX_CTRL				0x41e0
+#define TX_DIAG_TX_DRV				0x41e1
+#define TX_DIAG_BGREF_PREDRV_DELAY		0x41e7
+#define TX_DIAG_ACYA_0				0x41ff
+#define TX_DIAG_ACYA_1				0x43ff
+#define TX_DIAG_ACYA_2				0x45ff
+#define TX_DIAG_ACYA_3				0x47ff
+#define TX_ANA_CTRL_REG_1			0x5020
+#define TX_ANA_CTRL_REG_2			0x5021
+#define TX_DIG_CTRL_REG_1			0x5023
+#define TX_DIG_CTRL_REG_2			0x5024
+#define TXDA_CYA_AUXDA_CYA			0x5025
+#define TX_ANA_CTRL_REG_3			0x5026
+#define TX_ANA_CTRL_REG_4			0x5027
+#define TX_ANA_CTRL_REG_5			0x5029
+#define RX_PSC_A0				0x8000
+#define RX_PSC_CAL				0x8006
+#define PHY_HDP_MODE_CTRL			0xc008
+#define PHY_HDP_CLK_CTL				0xc009
+#define PHY_ISO_CMN_CTRL			0xc010
+#define PHY_PMA_CMN_CTRL1			0xc800
+#define PHY_PMA_ISO_CMN_CTRL			0xc810
+#define PHY_PMA_ISO_PLL_CTRL1			0xc812
+#define PHY_PMA_ISOLATION_CTRL			0xc81f
+
+/* PHY_HDP_CLK_CTL */
+#define PLL_DATA_RATE_CLK_DIV_MASK		GENMASK(15, 8)
+#define PLL_DATA_RATE_CLK_DIV_HBR		0x24
+#define PLL_DATA_RATE_CLK_DIV_HBR2		0x12
+#define PLL_CLK_EN_ACK				BIT(3)
+#define PLL_CLK_EN				BIT(2)
+#define PLL_READY				BIT(1)
+#define PLL_EN					BIT(0)
+
+/* PHY_PMA_CMN_CTRL1 */
+#define CMA_REF_CLK_DIG_DIV_MASK		GENMASK(13, 12)
+#define CMA_REF_CLK_SEL_MASK			GENMASK(6, 4)
+#define CMA_REF_CLK_RCV_EN_MASK			BIT(3)
+#define CMA_REF_CLK_RCV_EN			1
+#define CMN_READY				BIT(0)
+
+/* PHY_PMA_ISO_PLL_CTRL1 */
+#define CMN_PLL0_CLK_DATART_DIV_MASK		GENMASK(7, 0)
+
+/* TX_DIAG_TX_DRV */
+#define TX_DRIVER_PROG_BOOST_ENABLE		BIT(10)
+#define TX_DRIVER_PROG_BOOST_LEVEL_MASK		GENMASK(9, 8)
+#define TX_DRIVER_LDO_BG_DEPENDENT_REF_ENABLE	BIT(7)
+#define TX_DRIVER_LDO_BANDGAP_REF_ENABLE	BIT(6)
+
+/* TX_TXCC_CAL_SCLR_MULT_0 */
+#define SCALED_RESISTOR_CALIBRATION_CODE_ADD	BIT(8)
+#define RESISTOR_CAL_MULT_VAL_32_128		BIT(5)
+
+/* CMN_CDIAG_REFCLK_CTRL */
+#define DIG_REF_CLK_DIV_SCALER_MASK		GENMASK(14, 12)
+#define REFCLK_TERMINATION_EN_OVERRIDE_EN	BIT(7)
+#define REFCLK_TERMINATION_EN_OVERRIDE		BIT(6)
+
+/* CMN_DIAG_HSCLK_SEL */
+#define HSCLK1_SEL_MASK				GENMASK(5, 4)
+#define HSCLK0_SEL_MASK				GENMASK(1, 0)
+#define HSCLK_PLL0_DIV2				1
+
+/* XCVR_DIAG_HSCLK_SEL */
+#define HSCLK_SEL_MODE3_MASK			GENMASK(13, 12)
+#define HSCLK_SEL_MODE3_HSCLK1			1
+
+/* CMN_PLL0_VCOCAL_START */
+#define VCO_CALIB_CODE_START_POINT_VAL_MASK	GENMASK(8, 0)
+
+/* CMN_DIAG_PLL0_FBH_OVRD */
+#define PLL_FEEDBACK_DIV_HI_OVERRIDE_EN		BIT(15)
+
+/* CMN_DIAG_PLL0_FBL_OVRD */
+#define PLL_FEEDBACK_DIV_LO_OVERRIDE_EN		BIT(15)
+
+/* CMN_DIAG_PLL0_PXL_DIVH */
+#define PLL_PCLK_DIV_EN				BIT(15)
+
+/* XCVR_DIAG_PLLDRC_CTRL */
+#define DPLL_CLK_SEL_MODE3			BIT(14)
+#define DPLL_DATA_RATE_DIV_MODE3_MASK		GENMASK(13, 12)
+
+/* TX_DIAG_TX_CTRL */
+#define TX_IF_SUBRATE_MODE3_MASK		GENMASK(7, 6)
+
+/* PHY_HDP_MODE_CTRL */
+#define POWER_STATE_A3_ACK			BIT(7)
+#define POWER_STATE_A2_ACK			BIT(6)
+#define POWER_STATE_A1_ACK			BIT(5)
+#define POWER_STATE_A0_ACK			BIT(4)
+#define POWER_STATE_A3				BIT(3)
+#define POWER_STATE_A2				BIT(2)
+#define POWER_STATE_A1				BIT(1)
+#define POWER_STATE_A0				BIT(0)
+
+/* PHY_PMA_ISO_CMN_CTRL */
+#define CMN_MACRO_PWR_EN_ACK			BIT(5)
+
+#define KEEP_ALIVE		0x18
+
+#define REF_CLK_27MHZ		27000000
+
+/* HDMI TX clock control settings */
+struct hdptx_hdmi_ctrl {
+	u32 pixel_clk_freq_min;
+	u32 pixel_clk_freq_max;
+	u32 feedback_factor;
+	u32 data_range_kbps_min;
+	u32 data_range_kbps_max;
+	u32 cmnda_pll0_ip_div;
+	u32 cmn_ref_clk_dig_div;
+	u32 ref_clk_divider_scaler;
+	u32 pll_fb_div_total;
+	u32 cmnda_pll0_fb_div_low;
+	u32 cmnda_pll0_fb_div_high;
+	u32 pixel_div_total;
+	u32 cmnda_pll0_pxdiv_low;
+	u32 cmnda_pll0_pxdiv_high;
+	u32 vco_freq_min;
+	u32 vco_freq_max;
+	u32 vco_ring_select;
+	u32 cmnda_hs_clk_0_sel;
+	u32 cmnda_hs_clk_1_sel;
+	u32 hsclk_div_at_xcvr;
+	u32 hsclk_div_tx_sub_rate;
+	u32 cmnda_pll0_hs_sym_div_sel;
+	u32 cmnda_pll0_clk_freq_min;
+	u32 cmnda_pll0_clk_freq_max;
+};
+
+struct cdns_hdptx_phy {
+	struct cdns_mhdp_base base;
+
+	void __iomem *regs;	/* DPTX registers base */
+	struct device *dev;
+	struct phy *phy;
+	struct clk *ref_clk, *apb_clk;
+	u32 ref_clk_rate;
+	bool power_up;
+	union {
+		struct phy_configure_opts_hdmi hdmi;
+		struct phy_configure_opts_dp dp;
+	};
+};
+
+/* HDMI TX clock control settings, pixel clock is output */
+static const struct hdptx_hdmi_ctrl pixel_clk_output_ctrl_table[] = {
+/*Minclk  Maxclk Fdbak  DR_min   DR_max  ip_d  dig  DS    Totl */
+{ 27000,  27000, 1000,  270000,  270000, 0x03, 0x1, 0x1,  240, 0x0bc, 0x030,  80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x3,  27000,  27000},
+{ 27000,  27000, 1250,  337500,  337500, 0x03, 0x1, 0x1,  300, 0x0ec, 0x03c, 100, 0x030, 0x030, 2700000, 2700000, 0, 2, 2, 2, 4, 0x3,  33750,  33750},
+{ 27000,  27000, 1500,  405000,  405000, 0x03, 0x1, 0x1,  360, 0x11c, 0x048, 120, 0x03a, 0x03a, 3240000, 3240000, 0, 2, 2, 2, 4, 0x3,  40500,  40500},
+{ 27000,  27000, 2000,  540000,  540000, 0x03, 0x1, 0x1,  240, 0x0bc, 0x030,  80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x2,  54000,  54000},
+{ 54000,  54000, 1000,  540000,  540000, 0x03, 0x1, 0x1,  480, 0x17c, 0x060,  80, 0x026, 0x026, 4320000, 4320000, 1, 2, 2, 2, 4, 0x3,  54000,  54000},
+{ 54000,  54000, 1250,  675000,  675000, 0x04, 0x1, 0x1,  400, 0x13c, 0x050,  50, 0x017, 0x017, 2700000, 2700000, 0, 1, 1, 2, 4, 0x2,  67500,  67500},
+{ 54000,  54000, 1500,  810000,  810000, 0x04, 0x1, 0x1,  480, 0x17c, 0x060,  60, 0x01c, 0x01c, 3240000, 3240000, 0, 2, 2, 2, 2, 0x2,  81000,  81000},
+{ 54000,  54000, 2000, 1080000, 1080000, 0x03, 0x1, 0x1,  240, 0x0bc, 0x030,  40, 0x012, 0x012, 2160000, 2160000, 0, 2, 2, 2, 1, 0x1, 108000, 108000},
+{ 74250,  74250, 1000,  742500,  742500, 0x03, 0x1, 0x1,  660, 0x20c, 0x084,  80, 0x026, 0x026, 5940000, 5940000, 1, 2, 2, 2, 4, 0x3,  74250,  74250},
+{ 74250,  74250, 1250,  928125,  928125, 0x04, 0x1, 0x1,  550, 0x1b4, 0x06e,  50, 0x017, 0x017, 3712500, 3712500, 1, 1, 1, 2, 4, 0x2,  92812,  92812},
+{ 74250,  74250, 1500, 1113750, 1113750, 0x04, 0x1, 0x1,  660, 0x20c, 0x084,  60, 0x01c, 0x01c, 4455000, 4455000, 1, 2, 2, 2, 2, 0x2, 111375, 111375},
+{ 74250,  74250, 2000, 1485000, 1485000, 0x03, 0x1, 0x1,  330, 0x104, 0x042,  40, 0x012, 0x012, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500},
+{ 99000,  99000, 1000,  990000,  990000, 0x03, 0x1, 0x1,  440, 0x15c, 0x058,  40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 2, 0x2,  99000,  99000},
+{ 99000,  99000, 1250, 1237500, 1237500, 0x03, 0x1, 0x1,  275, 0x0d8, 0x037,  25, 0x00b, 0x00a, 2475000, 2475000, 0, 1, 1, 2, 2, 0x1, 123750, 123750},
+{ 99000,  99000, 1500, 1485000, 1485000, 0x03, 0x1, 0x1,  330, 0x104, 0x042,  30, 0x00d, 0x00d, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500},
+{ 99000,  99000, 2000, 1980000, 1980000, 0x03, 0x1, 0x1,  440, 0x15c, 0x058,  40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 1, 0x1, 198000, 198000},
+{148500, 148500, 1000, 1485000, 1485000, 0x03, 0x1, 0x1,  660, 0x20c, 0x084,  40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 2, 0x2, 148500, 148500},
+{148500, 148500, 1250, 1856250, 1856250, 0x04, 0x1, 0x1,  550, 0x1b4, 0x06e,  25, 0x00b, 0x00a, 3712500, 3712500, 1, 1, 1, 2, 2, 0x1, 185625, 185625},
+{148500, 148500, 1500, 2227500, 2227500, 0x03, 0x1, 0x1,  495, 0x188, 0x063,  30, 0x00d, 0x00d, 4455000, 4455000, 1, 1, 1, 2, 2, 0x1, 222750, 222750},
+{148500, 148500, 2000, 2970000, 2970000, 0x03, 0x1, 0x1,  660, 0x20c, 0x084,  40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 1, 0x1, 297000, 297000},
+{198000, 198000, 1000, 1980000, 1980000, 0x03, 0x1, 0x1,  220, 0x0ac, 0x02c,  10, 0x003, 0x003, 1980000, 1980000, 0, 1, 1, 2, 1, 0x0, 198000, 198000},

drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c new file +84 -0

+};
+
+/* HDMI TX PLL tuning settings */
+struct hdptx_hdmi_pll_tuning {
+	u32 vco_freq_bin;
+	u32 vco_freq_min;
+	u32 vco_freq_max;
+	u32 volt_to_current_coarse;
+	u32 volt_to_current;
+	u32 ndac_ctrl;
+	u32 pmos_ctrl;
+	u32 ptat_ndac_ctrl;
+	u32 feedback_div_total;
+	u32 charge_pump_gain;
+	u32 coarse_code;
+	u32 v2i_code;
+	u32 vco_cal_code;
+};
+
+/* HDMI TX PLL tuning settings, pixel clock is output */
+static const struct hdptx_hdmi_pll_tuning pixel_clk_output_pll_table[] = {
+/*bin VCO_freq min/max  coar  cod NDAC  PMOS PTAT div-T P-Gain Coa V2I CAL */
+{  1, 1980000, 1980000, 0x4, 0x3, 0x0, 0x09, 0x09, 220, 0x42, 160, 5, 183 },
+{  2, 2160000, 2160000, 0x4, 0x3, 0x0, 0x09, 0x09, 240, 0x42, 166, 6, 208 },
+{  3, 2475000, 2475000, 0x5, 0x3, 0x1, 0x00, 0x07, 275, 0x42, 167, 6, 209 },
+{  4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 300, 0x42, 188, 6, 230 },
+{  4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 400, 0x4c, 188, 6, 230 },
+{  5, 2970000, 2970000, 0x6, 0x3, 0x1, 0x00, 0x07, 330, 0x42, 183, 6, 225 },
+{  6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 360, 0x42, 203, 7, 256 },
+{  6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 480, 0x4c, 203, 7, 256 },
+{  7, 3712500, 3712500, 0x4, 0x3, 0x0, 0x07, 0x0F, 550, 0x4c, 212, 7, 257 },
+{  8, 3960000, 3960000, 0x5, 0x3, 0x0, 0x07, 0x0F, 440, 0x42, 184, 6, 226 },
+{  9, 4320000, 4320000, 0x5, 0x3, 0x1, 0x07, 0x0F, 480, 0x42, 205, 7, 258 },
+{ 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 495, 0x42, 219, 7, 272 },
+{ 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 660, 0x4c, 219, 7, 272 },
+{ 11, 4950000, 4950000, 0x6, 0x3, 0x1, 0x00, 0x07, 550, 0x42, 213, 7, 258 },
+{ 12, 5940000, 5940000, 0x7, 0x3, 0x1, 0x00, 0x07, 660, 0x42, 244, 8, 292 },
+};
+
+enum dp_link_rate {
+	RATE_1_6 = 162000,
+	RATE_2_1 = 216000,
+	RATE_2_4 = 243000,
+	RATE_2_7 = 270000,
+	RATE_3_2 = 324000,
+	RATE_4_3 = 432000,
+	RATE_5_4 = 540000,
+};
+
+#define MAX_LINK_RATE RATE_5_4
+
+struct phy_pll_reg {
+	u16 val[7];
+	u32 addr;
+};
+
+static const struct phy_pll_reg phy_pll_27m_cfg[] = {
+	/*  1.62    2.16    2.43    2.7     3.24    4.32    5.4      register address */
+	{{ 0x010e, 0x010e, 0x010e, 0x010e, 0x010e, 0x010e, 0x010e }, CMN_PLL0_VCOCAL_INIT_TMR },
+	{{ 0x001b, 0x001b, 0x001b, 0x001b, 0x001b, 0x001b, 0x001b }, CMN_PLL0_VCOCAL_ITER_TMR },
+	{{ 0x30b9, 0x3087, 0x3096, 0x30b4, 0x30b9, 0x3087, 0x30b4 }, CMN_PLL0_VCOCAL_START },
+	{{ 0x0077, 0x009f, 0x00b3, 0x00c7, 0x0077, 0x009f, 0x00c7 }, CMN_PLL0_INTDIV },
+	{{ 0xf9da, 0xf7cd, 0xf6c7, 0xf5c1, 0xf9da, 0xf7cd, 0xf5c1 }, CMN_PLL0_FRACDIV },
+	{{ 0x001e, 0x0028, 0x002d, 0x0032, 0x001e, 0x0028, 0x0032 }, CMN_PLL0_HIGH_THR },
+	{{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_PLL0_DSM_DIAG },
+	{{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL },
+	{{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_OVRD },
+	{{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBH_OVRD },
+	{{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBL_OVRD },
+	{{ 0x0006, 0x0007, 0x0007, 0x0007, 0x0006, 0x0007, 0x0007 }, CMN_DIAG_PLL0_V2I_TUNE },
+	{{ 0x0043, 0x0043, 0x0043, 0x0042, 0x0043, 0x0043, 0x0042 }, CMN_DIAG_PLL0_CP_TUNE },
+	{{ 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 }, CMN_DIAG_PLL0_LF_PROG },
+	{{ 0x0100, 0x0001, 0x0001, 0x0001, 0x0100, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE1 },
+	{{ 0x0007, 0x0001, 0x0001, 0x0001, 0x0007, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE2 },
+	{{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_DIAG_PLL0_TEST_MODE},
+	{{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 }, CMN_PSM_CLK_CTRL }
+};
+
+static int dp_link_rate_index(u32 rate)
+{
+	switch (rate) {
+	case RATE_1_6:
+		return 0;
+	case RATE_2_1:

drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c new file +199 -0

+	}
+}
+
+static int cdns_phy_reg_write(struct cdns_hdptx_phy *cdns_phy, u32 addr, u32 val)
+{
+	return cdns_mhdp_reg_write(&cdns_phy->base, ADDR_PHY_AFE + (addr << 2), val);
+}
+
+static u32 cdns_phy_reg_read(struct cdns_hdptx_phy *cdns_phy, u32 addr)
+{
+	u32 reg32;
+
+	cdns_mhdp_reg_read(&cdns_phy->base, ADDR_PHY_AFE + (addr << 2), &reg32);
+
+	return reg32;
+}
+
+static void hdptx_dp_aux_cfg(struct cdns_hdptx_phy *cdns_phy)
+{
+	/* Power up Aux */
+	cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 1);
+
+	cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_1, 0x3);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, 36);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa018);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030c);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0000);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x1001);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa098);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa198);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
+	ndelay(150);
+	cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f);
+}
+
+/* PMA common configuration for 27MHz */
+static void hdptx_dp_phy_pma_cmn_cfg_27mhz(struct cdns_hdptx_phy *cdns_phy)
+{
+	u32 num_lanes = cdns_phy->dp.lanes;
+	u16 val;
+	int k;
+
+	/* Enable PMA input ref clk(CMN_REF_CLK_RCV_EN) */
+	val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+	val &= ~CMA_REF_CLK_RCV_EN_MASK;
+	val |= FIELD_PREP(CMA_REF_CLK_RCV_EN_MASK, CMA_REF_CLK_RCV_EN);
+	cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
+
+	/* Startup state machine registers */
+	cdns_phy_reg_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0087);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLEN_TMR, 0x001b);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0036);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLVREF_TMR, 0x001b);
+	cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x006c);
+
+	/* Current calibration registers */
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_INIT_TMR, 0x0044);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_ITER_TMR, 0x0006);
+
+	/* Resistor calibration registers */
+	cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
+	cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_INIT_TMR, 0x0022);
+	cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_ITER_TMR, 0x0006);
+
+	for (k = 0; k < num_lanes; k = k + 1) {
+		/* Power state machine registers */
+		cdns_phy_reg_write(cdns_phy, XCVR_PSM_CAL_TMR  | (k << 9), 0x016d);
+		cdns_phy_reg_write(cdns_phy, XCVR_PSM_A0IN_TMR | (k << 9), 0x016d);
+		/* Transceiver control and diagnostic registers */
+		cdns_phy_reg_write(cdns_phy, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x00a2);
+		cdns_phy_reg_write(cdns_phy, TX_DIAG_BGREF_PREDRV_DELAY | (k << 9), 0x0097);
+		/* Transmitter receiver detect registers */
+		cdns_phy_reg_write(cdns_phy, TX_RCVDET_EN_TMR | (k << 9), 0x0a8c);
+		cdns_phy_reg_write(cdns_phy, TX_RCVDET_ST_TMR | (k << 9), 0x0036);
+	}
+
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
+	cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
+}
+
+static void hdptx_dp_phy_pma_cmn_pll0_27mhz(struct cdns_hdptx_phy *cdns_phy)
+{
+	u32 num_lanes = cdns_phy->dp.lanes;
+	u32 link_rate = cdns_phy->dp.link_rate;
+	u16 val;
+	int index, i, k;
+
+	/* DP PLL data rate 0/1 clock divider value */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= ~PLL_DATA_RATE_CLK_DIV_MASK;
+	if (link_rate <= RATE_2_7)
+		val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
+				  PLL_DATA_RATE_CLK_DIV_HBR);
+	else
+		val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
+				  PLL_DATA_RATE_CLK_DIV_HBR2);
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+
+	/* High speed clock 0/1 div */
+	val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
+	val &= ~(HSCLK1_SEL_MASK | HSCLK0_SEL_MASK);
+	if (link_rate <= RATE_2_7) {
+		val |= FIELD_PREP(HSCLK1_SEL_MASK, HSCLK_PLL0_DIV2);
+		val |= FIELD_PREP(HSCLK0_SEL_MASK, HSCLK_PLL0_DIV2);
+	}
+	cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
+
+	for (k = 0; k < num_lanes; k++) {
+		val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
+		val &= ~HSCLK_SEL_MODE3_MASK;
+		if (link_rate <= RATE_2_7)
+			val |= FIELD_PREP(HSCLK_SEL_MODE3_MASK, HSCLK_SEL_MODE3_HSCLK1);
+		cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val);
+	}
+
+	/* DP PHY PLL 27MHz configuration */
+	index = dp_link_rate_index(link_rate);
+	for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
+		cdns_phy_reg_write(cdns_phy, phy_pll_27m_cfg[i].addr,
+				   phy_pll_27m_cfg[i].val[index]);
+
+	/* Transceiver control and diagnostic registers */
+	for (k = 0; k < num_lanes; k++) {
+		val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
+		val &= ~(DPLL_DATA_RATE_DIV_MODE3_MASK | DPLL_CLK_SEL_MODE3);
+		if (link_rate <= RATE_2_7)
+			val |= FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK, 2);
+		else
+			val |= FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK, 1);
+		cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);
+	}
+
+	for (k = 0; k < num_lanes; k = k + 1) {
+		/* Power state machine registers */
+		cdns_phy_reg_write(cdns_phy, (XCVR_PSM_RCTRL | (k << 9)), 0xbefc);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A0 | (k << 9)), 0x6799);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A1 | (k << 9)), 0x6798);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A2 | (k << 9)), 0x0098);
+		cdns_phy_reg_write(cdns_phy, (TX_PSC_A3 | (k << 9)), 0x0098);
+		/* Receiver calibration power state definition register */
+		val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
+		val &= 0xffbb;
+		cdns_phy_reg_write(cdns_phy, (RX_PSC_CAL | (k << 9)), val);
+		val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0 | (k << 9));
+		val &= 0xffbb;
+		cdns_phy_reg_write(cdns_phy, (RX_PSC_A0 | (k << 9)), val);
+	}
+}
+
+static void hdptx_dp_phy_ref_clock_type(struct cdns_hdptx_phy *cdns_phy)
+{
+	u32 val;
+
+	val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
+	val &= ~CMA_REF_CLK_SEL_MASK;
+	/*
+	 * single ended reference clock (val |= 0x0030);
+	 * differential clock  (val |= 0x0000);
+	 *
+	 * for differential clock on the refclk_p and
+	 * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
+	 * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
+	 */
+	val |= FIELD_PREP(CMA_REF_CLK_SEL_MASK, 3);
+	cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
+}
+
+static int wait_for_ack(struct cdns_hdptx_phy *cdns_phy, u32 reg, u32 mask,

drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c new file +99 -0

+
+	dev_err(cdns_phy->dev, "%s\n", err_msg);
+	return -ETIMEDOUT;
+}
+
+static int wait_for_ack_clear(struct cdns_hdptx_phy *cdns_phy, u32 reg, u32 mask,
+			      const char *err_msg)
+{
+	u32 val, i;
+
+	for (i = 0; i < 10; i++) {
+		val = cdns_phy_reg_read(cdns_phy, reg);
+		if (!(val & mask))
+			return 0;
+		msleep(20);
+	}
+
+	dev_err(cdns_phy->dev, "%s\n", err_msg);
+	return -ETIMEDOUT;
+}
+
+static int hdptx_dp_phy_power_up(struct cdns_hdptx_phy *cdns_phy)
+{
+	u32 val;
+	int ret;
+
+	/* Enable HDP PLL's for high speed clocks */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val |= PLL_EN;
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	ret = wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
+			   "Wait PLL Ack failed");
+	if (ret < 0)
+		return ret;
+
+	/* Enable HDP PLL's data rate and full rate clocks out of PMA. */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val |= PLL_CLK_EN;
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	ret = wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_CLK_EN_ACK,
+			   "Wait PLL clock enable ACK failed");
+	if (ret < 0)
+		return ret;
+
+	/* Configure PHY in A2 Mode */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2);
+	ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2_ACK,
+			   "Wait A2 Ack failed");
+	if (ret < 0)
+		return ret;
+
+	/* Configure PHY in A0 mode (PHY must be in the A0 power
+	 * state in order to transmit data)
+	 */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0);
+	ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0_ACK,
+			   "Wait A0 Ack failed");
+	if (ret < 0)
+		return ret;
+
+	cdns_phy->power_up = true;
+
+	return ret;
+}
+
+static int hdptx_dp_phy_power_down(struct cdns_hdptx_phy *cdns_phy)
+{
+	u16 val;
+	int ret;
+
+	if (!cdns_phy->power_up)
+		return 0;
+
+	/* Place the PHY lanes in the A3 power state. */
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3);
+	ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3_ACK,
+			   "Wait A3 Ack failed");
+	if (ret)
+		return ret;
+
+	/* Disable HDP PLL's data rate and full rate clocks out of PMA. */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= ~PLL_CLK_EN;
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	ret = wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL, PLL_CLK_EN_ACK,
+				 "Wait PLL clock Ack clear failed");
+	if (ret)
+		return ret;
+
+	/* Disable HDP PLL's for high speed clocks */
+	val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
+	val &= ~PLL_EN;
+	cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
+	ret = wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
+				 "Wait PLL Ack clear failed");
+	if (ret)
+		return ret;
+
+	cdns_phy->power_up = false;

drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c new file +13 -0

+
+	if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) {
+		hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy);
+		hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy);
+	} else {
+		dev_err(cdns_phy->dev, "Not support ref clock rate\n");
+	}
+
+	/* PHY power up */
+	return hdptx_dp_phy_power_up(cdns_phy);
+}
+
+static bool hdptx_phy_check_alive(struct cdns_hdptx_phy *cdns_phy)