riscv: sophgo: add clock support for sg2042
Subsystems (4)
v8 cover riscv: sophgo: add clock support for sg2042
From: Chen Wang <[email protected]>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen
---
Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9].
In this version, the main change is to split one clock provider into two. Strictly follow the hardware instructions, in the memoymap, the control registers of some clocks are defined in the SYS_CTRL segment, and the control registers of other clocks are defined in the CLOCK segment. Therefore, the new design defines two clock controllers, one as a child node of the system control and the other as an independent clock controller node.
This modification involves a major modification to the binding files, so the reviewed-by tags has been deleted.
Changes in v7:
The patch series is based on v6.7. You can simply review or test the patches at the link [8].
- fixed initval issue.
- fixed pll clk crash issue.
- fixed warning reported by <[email protected]>
- code optimization as per review comments.
- code cleanup and style improvements as per review comments and checkpatch
with "--strict"
Changes in v6:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [7].
- fixed some warnings/errors reported by kernel test robot <[email protected]>.
Changes in v5:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [6].
- dt-bindings: improved yaml, such as:
- add vendor prefix for system-ctrl property for clock generator.
- Add explanation for system-ctrl property.
- move sophgo,sg2042-clkgen.yaml to directly under clock folder.
- fixed bugs for driver Makefile/Kconfig
- continue cleaning-up debug print for driver code.
Changes in v4:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5].
- dt-bindings: fixed a dt_binding_check error.
Changes in v3:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3].
- DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4].
- Updating minor issues in dt-bindings as per input from reviews.
Changes in v2:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2].
- Squashed the patch adding clock definitions with the patch adding the binding for the clock controller.
- Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon.
- DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC.
- Fixed some bugs in driver code during testing, including removing warnings for rv32_defconfig.
- Updated MAINTAINERS info.
Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].
---
Chen Wang (5):
dt-bindings: clock: sophgo: add sysclk for SG2042
dt-bindings: soc: sophgo: Add Sophgo system control module
dt-bindings: clock: sophgo: add clkgen for SG2042
clk: sophgo: Add SG2042 clock generator driver
riscv: dts: add clock generator for Sophgo SG2042 SoC
.../bindings/clock/sophgo,sg2042-clkgen.yaml | 40 + .../bindings/clock/sophgo,sg2042-sysclk.yaml | 44 + .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46 + MAINTAINERS | 7 + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 39 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 8 + drivers/clk/sophgo/Makefile | 2 + drivers/clk/sophgo/clk-sophgo-sg2042.c | 1387 +++++++++++++++++ drivers/clk/sophgo/clk-sophgo-sg2042.h | 233 +++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++ .../dt-bindings/clock/sophgo,sg2042-sysclk.h | 63 + 14 files changed, 1994 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-sysclk.yaml create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-sysclk.h
base-commit: 0dd3ee31125508cd67f7e7172247f05b7fd1753a
Signature · 1 line
2.25.1
PATCH v8 1/5 dt-bindings: clock: sophgo: add sysclk for SG2042
From: Chen Wang <[email protected]>
Add bindings for the clocks of which configuration registers are in the range of SYS_CTRL in the memory-map.
.
--- .../bindings/clock/sophgo,sg2042-sysclk.yaml | 44 +++++++++++++ .../dt-bindings/clock/sophgo,sg2042-sysclk.h | 63 +++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-sysclk.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-sysclk.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-sysclk.yaml new file +44 -0
@@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-sysclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Clock Generator in System-Control + +description: + These clocks have configuration registers in the SYS_CTRL range of memory-map. + So the node should be a child of system-control node. + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-sysclk + + clocks: + items: + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-sysclk.h> for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "sophgo,sg2042-sysclk"; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-sysclk.h new file +63 -0
63 lines not on this page · raw message
Signature · 1 line
2.25.1
Re: [PATCH v8 1/5] dt-bindings: clock: sophgo: add sysclk for SG2042
Quoted 4 lines · Chen Wang
From: Chen Wang <[email protected]>
Add bindings for the clocks of which configuration registers are in the range of
SYS_CTRLin the memory-map.
This means it is not a separate device and should be just merged with parent node. Otherwise please give us some arguments why this should be a separate device node.
Quoted 4 lines
Signed-off-by Chen Wang <[email protected]>.
Some stray characters above ^^^. Clean your commit msg. Also, I have doubts it passes checkpatch.
Best regards,
Krzysztof
PATCH v8 2/5 dt-bindings: soc: sophgo: Add Sophgo system control module
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
--- .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +46 -0
@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL), providing multiple + low level platform functions like chip configuration, clock control, etc. + +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child node + $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object + +required: + - compatible + - reg + - clock-controller + +additionalProperties: false + +examples: + - | + system-control@30010000 { + compatible = "sophgo,sg2042-sysctrl"; + reg = <0x30010000 0x1000>; + + clock-controller { + compatible = "sophgo,sg2042-sysclk"; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; + };
Signature · 1 line
2.25.1
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
Quoted 30 lines · Chen Wang
From: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
Signed-off-by Chen Wang <[email protected]>--- .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +14
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL), providing multiple + low level platform functions like chip configuration, clock control, etc.
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 24
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Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +10
-0+ +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child node
Drop the comment, it is obvious. It cannot be anything else.
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 26
Quoted 2 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +2
-0+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object
Why isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 37
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Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +11
-0+ +required: + - compatible + - reg + - clock-controller + +additionalProperties: false + +examples: + - | + system-control@30010000 {
Why did you change the name? Please provide detailed changelog with explanation of such changes.
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 40
Quoted 3 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +3
-0+ compatible = "sophgo,sg2042-sysctrl"; + reg = <0x30010000 0x1000>; +
Best regards,
Krzysztof
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
Quoted 43 lines · Krzysztof Kozlowski
Quoted 30 lines · Chen Wang
From: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
Signed-off-by Chen Wang <[email protected]>--- .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+)create mode 100644
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +14
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL), providing multiple + low level platform functions like chip configuration, clock control, etc.Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +10
-0+ +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child nodeDrop the comment, it is obvious. It cannot be anything else.
Quoted 5 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 26
Quoted 2 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +2
-0+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: objectWhy isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
Quoted 5 lines
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Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +5
-0+ +required: + - compatible + - reg + - clock-controller
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Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 37
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Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +6
-0+ +additionalProperties: false + +examples: + - | + system-control@30010000 {Why did you change the name? Please provide detailed changelog with explanation of such changes.
I changed the name due to I find the TRM(https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/system-control.rst) call it "system control", so I changed it in v8.
Which one do you prefer? I'm not sure if there are any requirements for this?
Quoted 6 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 40
Quoted 3 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +3
-0+ compatible = "sophgo,sg2042-sysctrl"; + reg = <0x30010000 0x1000>; +Best regards,
Krzysztof
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
Quoted 66 lines · Chen Wang
Quoted 43 lines · Krzysztof Kozlowski
Quoted 30 lines · Chen Wang
From: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
Signed-off-by Chen Wang <[email protected]>--- .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+)create mode 100644
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +14
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL), providing multiple + low level platform functions like chip configuration, clock control, etc.Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +10
-0+ +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child nodeDrop the comment, it is obvious. It cannot be anything else.
Quoted 5 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 26
Quoted 2 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +2
-0+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: objectWhy isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
Quoted 5 lines
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Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +5
-0+ +required: + - compatible + - reg + - clock-controllerQuoted 8 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 37
Quoted 6 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +6
-0+ +additionalProperties: false + +examples: + - | + system-control@30010000 {Why did you change the name? Please provide detailed changelog with explanation of such changes.
Quoted 6 lines
I changed the name due to I find the TRM(https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/system-control.rst) call it "system control", so I changed it in v8.
Which one do you prefer? I'm not sure if there are any requirements for this?
Node names should be generic and follow common guidelines, not match your TRM. Please use the same name all other devices use for the same class.
Best regards,
Krzysztof
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
In reply to Chen WangQuoted 51 lines · Chen Wang
Quoted 49 lines · Krzysztof Kozlowski
Quoted 36 lines · Chen Wang
From: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
Signed-off-by Chen Wang <[email protected]>---
.../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46
+++++++++++++++++++1 file changed, 46 insertions(+)create mode 100644
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +0
-0new file mode 100644
index 000000000000..7b50bb56b4cf
---/dev/null
+++b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +4
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id:http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +8
-0+ +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL),providing multiple
+ low level platform functions like chip configuration, clock control, etc.Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +10
-0+ +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child nodeDrop the comment, it is obvious. It cannot be anything else.
Quoted 6 lines
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+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object
Why isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
hi, Krzysztof,
After some double check, I find we will have more devices in system-control. For example, in the SYS_CTRL area, there is also a section of registers used to control the "General Purpose Interrupt". The pcie controller of sg2042 will use this interrupt controller which is defined in SYS_CTRL, we will add it in later work.
Specifically, the distribution (offset) of registers in SYS_CTRL is as follows:
- 0x0C0 ~ 0x0FC: for some PLL clocks :
- ......
- 0x2E0 ~ 0x30C: for General Purpose Interrupt:
- ......
- 0x368 ~ 0x3FC: For some gate clocks
So it seems that it is still necessary to keep the current child node method, and it will also facilitate future expansion.
What do you think, please feel free let me know.
Thanks,
Chen
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
Quoted 77 lines · Chen Wang
Quoted 52 lines · Chen Wang
Quoted 50 lines · Krzysztof Kozlowski
Quoted 37 lines · Chen Wang
From: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
Signed-off-by Chen Wang <[email protected]>---
.../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46
+++++++++++++++++++1 file changed, 46 insertions(+)create mode 100644
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +0
-0new file mode 100644
index 000000000000..7b50bb56b4cf
---/dev/null
+++b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +4
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id:http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +8
-0+ +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL),providing multiple
+ low level platform functions like chip configuration, clock control, etc.Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml +10
-0+ +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child nodeDrop the comment, it is obvious. It cannot be anything else.
Quoted 6 lines
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+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object
Why isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
hi, Krzysztof,
After some double check, I find we will have more devices in system-control. For example, in the
SYS_CTRLarea, there is also a section of registers used to control the "General Purpose Interrupt". The pcie controller of sg2042 will use this interrupt controller which is defined inSYS_CTRL, we will add it in later work.Specifically, the distribution (offset) of registers in
SYS_CTRLis as follows:-
0x0C0~0x0FC: for some PLL clocks :- ......
-
0x2E0~0x30C: for General Purpose Interrupt:- ......
-
0x368~0x3FC: For some gate clocks
Quoted 7 lines
So it seems that it is still necessary to keep the current child node method, and it will also facilitate future expansion.
What do you think, please feel free let me know.
Thanks,
Chen
hi, Krzysztof,
Can you please take a look if you have time, looking forward to your reply.
Thanks,
Chen
Quoted 6 lines
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Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
In reply to Chen WangQuoted 64 lines · Chen Wang
Quoted 54 lines · Chen Wang
Quoted 52 lines · Krzysztof Kozlowski
Quoted 39 lines · Chen Wang
From: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
Signed-off-by Chen Wang <[email protected]>---
.../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46
+++++++++++++++++++1 file changed, 46 insertions(+)create mode 100644
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml(quoted diff) +0
-0
a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlb/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlnew file mode 100644
index 000000000000..7b50bb56b4cf
---/dev/null
+++b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +4
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id:http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +8
-0+ +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL),providing multiple
+ low level platform functions like chip configuration, clock control, etc.Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +10
-0+ +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child nodeDrop the comment, it is obvious. It cannot be anything else.
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+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object
Why isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
Quoted 8 lines
hi, Krzysztof,
After some double check, I find we will have more devices in system-control. For example, in the
SYS_CTRLarea, there is also a section of registers used to control the "General Purpose Interrupt". The pcie controller of sg2042 will use this interrupt controller which is defined inSYS_CTRL, we will add it in later work.
I expect then all devices to be documented.
Best regards,
Krzysztof
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
Quoted 64 lines · Krzysztof Kozlowski
Quoted 63 lines · Chen Wang
Quoted 53 lines · Chen Wang
Quoted 52 lines · Krzysztof Kozlowski
Quoted 39 lines · Chen Wang
From: Chen Wang <[email protected]>
Add documentation to describe Sophgo System Control for SG2042.
Signed-off-by Chen Wang <[email protected]>--- .../soc/sophgo/sophgo,sg2042-sysctrl.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+)create mode 100644
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamldiff --git
a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlb/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlnew file mode 100644
index 000000000000..7b50bb56b4cf
---/dev/null
+++b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yamlDocumentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +4
-0@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id:http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +8
-0+ +title: Sophgo SG2042 SoC system control + +maintainers: + - Chen Wang <[email protected]> + +description: + The Sophgo system control is a registers block (SYS_CTRL),providing multiple
+ low level platform functions like chip configuration, clock control, etc.Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml line 24
Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-sysctrl.yaml new file +10
-0+ +properties: + compatible: + const: sophgo,sg2042-sysctrl + + reg: + maxItems: 1 + + clock-controller: + # Child nodeDrop the comment, it is obvious. It cannot be anything else.
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+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object
Why isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
hi, Krzysztof,
Quoted 7 lines
Quoted 6 lines
After some double check, I find we will have more devices in system-control. For example, in the
SYS_CTRLarea, there is also a section of registers used to control the "General Purpose Interrupt". The pcie controller of sg2042 will use this interrupt controller which is defined inSYS_CTRL, we will add it in later work.I expect then all devices to be documented.
hi, Krzysztof.
First, I'm very sorry for having double-checked with you for this system controller and child node issue, but this time I'm sure there should be no more child nodes except the clock and interrupt controllers, though there are some other registers in SYS_CTRL section, but we will not use them till now.
One question, when you say "to be documented", do you mean I need write binding/yaml files for other child node? But they exceed the scope of this patchset (this patchset is for clock support only). That's why I suggest just add clock-controller in this patchset and to add the interrupt controller in another patchset for pcie support. This mechanism should be suitable for our expansion.
Thanks,
Chen
Quoted 4 lines
Best regards,
Krzysztof
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
Quoted 25 lines · Chen Wang
Quoted 9 lines
Quoted 9 lines
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object
Why isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
hi, Krzysztof,
Quoted 7 lines
Quoted 6 lines
After some double check, I find we will have more devices in system-control. For example, in the
SYS_CTRLarea, there is also a section of registers used to control the "General Purpose Interrupt". The pcie controller of sg2042 will use this interrupt controller which is defined inSYS_CTRL, we will add it in later work.I expect then all devices to be documented.
hi, Krzysztof.
First, I'm very sorry for having double-checked with you for this system controller and child node issue, but this time I'm sure there should be no more child nodes except the clock and interrupt controllers, though there are some other registers in
SYS_CTRLsection, but we will not use them till now.
Quoted 3 lines
One question, when you say "to be documented", do you mean I need write binding/yaml files for other child node? But they exceed the scope of this patchset (this patchset is for clock support only). That's why I
That's not true. The scope of this patch is to add DT binding description for your device. If you choose any other scope, I don't agree and I am not going to provide positive review.
Quoted 3 lines
suggest just add clock-controller in this patchset and to add the interrupt controller in another patchset for pcie support. This mechanism should be suitable for our expansion.
How then are you going to solve the requirement: "DO attempt to make bindings complete even"?
Best regards,
Krzysztof
Re: [PATCH v8 2/5] dt-bindings: soc: sophgo: Add Sophgo system control module
Quoted 32 lines · Krzysztof Kozlowski
Quoted 24 lines · Chen Wang
Quoted 9 lines
Quoted 9 lines
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
+ $ref: /schemas/clock/sophgo,sg2042-sysclk.yaml# + type: object
Why isn't this merged here? You do not need the child node really... unless the clock inputs are specific to that clock controller and you will have here more devices? But where are they in such case?
I don't see more devices will be included later. It should be ok to merge them into one.
hi, Krzysztof,
Quoted 7 lines
Quoted 6 lines
After some double check, I find we will have more devices in system-control. For example, in the
SYS_CTRLarea, there is also a section of registers used to control the "General Purpose Interrupt". The pcie controller of sg2042 will use this interrupt controller which is defined inSYS_CTRL, we will add it in later work.I expect then all devices to be documented.
hi, Krzysztof.
First, I'm very sorry for having double-checked with you for this system controller and child node issue, but this time I'm sure there should be no more child nodes except the clock and interrupt controllers, though there are some other registers in
SYS_CTRLsection, but we will not use them till now.Quoted 3 lines
One question, when you say "to be documented", do you mean I need write binding/yaml files for other child node? But they exceed the scope of this patchset (this patchset is for clock support only). That's why I
That's not true. The scope of this patch is to add DT binding description for your device. If you choose any other scope, I don't agree and I am not going to provide positive review.
Quoted 7 lines
Quoted 3 lines
suggest just add clock-controller in this patchset and to add the interrupt controller in another patchset for pcie support. This mechanism should be suitable for our expansion.
How then are you going to solve the requirement: "DO attempt to make bindings complete even"?
Learned and I will try to make bindings for system-controller device complete, thanks.
Quoted 4 lines
Best regards,
Krzysztof
PATCH v8 3/5 dt-bindings: clock: sophgo: add clkgen for SG2042
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add bindings for the clocks of which configuration registers are in the range of CLOCK in the memory-map.
--- .../bindings/clock/sophgo,sg2042-clkgen.yaml | 40 +++++++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++++++++++++++++++ 2 files changed, 151 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml new file +40 -0
@@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Clock Generator + +description: + These clocks have configuration registers in the CLOCK range of memory-map. + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-clkgen + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices. + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@30012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x30012000 0x1000>; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-clkgen.h new file +111 -0
111 lines not on this page · raw message
Signature · 1 line
2.25.1
PATCH v8 4/5 clk: sophgo: Add SG2042 clock generator driver
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add a driver for the SOPHGO SG2042 clock generator.
--- MAINTAINERS | 7 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 8 + drivers/clk/sophgo/Makefile | 2 + drivers/clk/sophgo/clk-sophgo-sg2042.c | 1387 ++++++++++++++++++++++++ drivers/clk/sophgo/clk-sophgo-sg2042.h | 233 ++++ 7 files changed, 1639 insertions(+) create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
MAINTAINERS +7 -0
@@ -20197,6 +20197,13 @@ S: Maintained F: arch/riscv/boot/dts/sophgo/ F: Documentation/devicetree/bindings/riscv/sophgo.yaml +SOPHGO CLOCK DRIVER +M: Chen Wang <[email protected]> +S: Maintained +F: Documentation/devicetree/bindings/clock/sophgo/ +F: drivers/clk/sophgo/ +F: include/dt-bindings/clock/sophgo,sg2042-clkgen.h + SOUND M: Jaroslav Kysela <[email protected]> M: Takashi Iwai <[email protected]>
drivers/clk/Kconfig +1 -0
@@ -499,6 +499,7 @@ source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/socfpga/Kconfig" +source "drivers/clk/sophgo/Kconfig" source "drivers/clk/sprd/Kconfig" source "drivers/clk/starfive/Kconfig" source "drivers/clk/sunxi/Kconfig"
drivers/clk/Makefile +1 -0
@@ -119,6 +119,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-y += socfpga/ +obj-y += sophgo/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_ARCH_STI) += st/
drivers/clk/sophgo/Kconfig new file +8 -0
@@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 + +config CLK_SOPHGO_SG2042 + bool "Sophgo SG2042 clock support" + depends on ARCH_SOPHGO || COMPILE_TEST + default y + help + Say yes here to support the clock controller on the Sophgo SG2042 SoC.
drivers/clk/sophgo/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CLK_SOPHGO_SG2042) += clk-sophgo-sg2042.o
drivers/clk/sophgo/clk-sophgo-sg2042.c new file +1387 -0
1,387 lines not on this page · raw message
drivers/clk/sophgo/clk-sophgo-sg2042.h new file +233 -0
233 lines not on this page · raw message
Signature · 1 line
2.25.1
PATCH v8 5/5 riscv: dts: add clock generator for Sophgo SG2042 SoC
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add clock generator node to device tree for SG2042, and enable clock for uart.
--- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 39 +++++++++++++++++++ 2 files changed, 51 insertions(+)
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +12 -0
@@ -14,6 +14,18 @@ chosen { }; }; +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; };
arch/riscv/boot/dts/sophgo/sg2042.dtsi +39 -0
@@ -5,6 +5,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sophgo,sg2042-clkgen.h> #include "sg2042-cpus.dtsi"
@@ -18,6 +19,24 @@ aliases { serial0 = &uart0; }; + cgi_main: oscillator0 { + compatible = "fixed-clock"; + clock-output-names = "cgi_main"; + #clock-cells = <0>; + }; + + cgi_dpll0: oscillator1 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll0"; + #clock-cells = <0>; + }; + + cgi_dpll1: oscillator2 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll1"; + #clock-cells = <0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>;
@@ -311,12 +330,32 @@ intc: interrupt-controller@7090000000 { riscv,ndev = <224>; }; + system-control@7030010000 { + compatible = "sophgo,sg2042-sysctrl"; + reg = <0x70 0x30010000 0x0 0x1000>; + + sysclk: clock-controller { + compatible = "sophgo,sg2042-sysclk"; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; + }; + + clkgen: clock-controller@7030012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x70 0x30012000 0x0 0x1000>; + #clock-cells = <1>; + }; + uart0: serial@7040000000 { compatible = "snps,dw-apb-uart"; reg = <0x00000070 0x40000000 0x00000000 0x00001000>; interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; + clocks = <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled";
Signature · 1 line
2.25.1
Quoted 13 lines · Chen Wang
From: Chen Wang <[email protected]>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen---
Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9].
...
Quoted 4 lines
Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].
Quoted 9 lines
lore links are useful to previous discussions. This shows what was at v7, but I cannot see my comments and compare whether you applied them.
Best regards,
Krzysztof
Quoted 29 lines · Krzysztof Kozlowski
Quoted 13 lines · Chen Wang
From: Chen Wang <[email protected]>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen---
Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9]....
Quoted 4 lines
Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].
Quoted 2 lines
lore links are useful to previous discussions. This shows what was at v7, but I cannot see my comments and compare whether you applied them.
Ok, I will replace them with lore links in next revision.
Quoted 4 lines
Best regards,
Krzysztof