riscv: sophgo: add clock support for sg2042
Subsystems (4)
v16 cover riscv: sophgo: add clock support for sg2042
From: Chen Wang <[email protected]>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen
---
Changes in v16:
The patch series is based on v6.10-rc1.
Improved the dirvier code as per comments from Emil Renner Berthing.
- Split driver source file into three and change from built-in to module.
- Directly use status/enable pll register, no need to store them.
- Use FIELD_PREP/FIELD_GET to simplify the code.
- Some misc code improvements, such as for macro and local variables.
Changes in v15:
The patch series is based on v6.9-rc5. You can simply review or test the patches at the link [16].
Improved the dirvier code as per 3rd review comments from Stephen Boyd.
- Converted all parents described by strings to use clk_parent_data or clk_hw directly.
- Just use struct clk_init_data::parent_hws when only have a clk_hw.
- Removed extra cleanup when use devm.
- Some misc code improvements.
Changes in v14:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [15].
Improved the dirvier code as per 2nd review comments from Stephen Boyd.
- Inline the header file into source file.
- Use devm_xxx functions for pll/div/gate registeration.
- Use clk_parent_data for mux clocks initialization.
- Use u32 for registers readl/writel.
- Use devm_platform_ioremap_resource instead of devm_of_iomap.
- Cleanup some dead code and add definitions for some magic numbers.
- Add include files missed.
- Use kernel-doc to improve comments for some structure and functions.
- Other misc code cleanup work as per input from reviewers.
Changes in v13:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [14].
Just added a minor fix for clk driver which was missed in v12.
Changes in v12:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [13].
Improved the dirvier code as per review comments from Stephen Boyd.
- Remove default y for CLK_SOPHGO_SG2042.
- Optimize sg2042_pll_get_postdiv_1_2, move postdiv1_2 to the function. scope and add more explaniation.
- Optimize sg2042_get_pll_ctl_setting.
- Switch to platform driver.
- Use clk_hw for initialization of struct clks.
- Don't use ignore_unused when using critical.
- Other code cleanup as per input form the reviewers.
Changes in v11:
The patch series is based on v6.8-rc5. You can simply review or test the patches at the link [12].
Quick fixed some dt_binding_check errors reported by Rob.
Changes in v10:
The patch series is based on v6.8-rc4. You can simply review or test the patches at the link [11].
Add input clocks for rpgate & clkgen.
Changes in v9:
The patch series is based on v6.8-rc2. You can simply review or test the patches at the link [10].
From this version, drop the system-controller node due to there is no actual device corresponding to it in IC design. SYS_CTRL is just a registers segment defined on TRM for misc functions. Now three clock-controllers are defined for SG2042, the control registers of the three clock-controllers are scattered in different memory address spaces:
- the first one is for pll clocks;
- the second one is for gate clocks for RP subsystem;
- the third one is for div/mux, and gate clocks working for other subsystem than RP subsystem.
Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9].
In this version, the main change is to split one clock provider into two. Strictly follow the hardware instructions, in the memoymap, the control registers of some clocks are defined in the SYS_CTRL segment, and the control registers of other clocks are defined in the CLOCK segment. Therefore, the new design defines two clock controllers, one as a child node of the system control and the other as an independent clock controller node.
This modification involves a major modification to the binding files, so the reviewed-by tags has been deleted.
Changes in v7:
The patch series is based on v6.7. You can simply review or test the patches at the link [8].
- fixed initval issue.
- fixed pll clk crash issue.
- fixed warning reported by <[email protected]>
- code optimization as per review comments.
- code cleanup and style improvements as per review comments and checkpatch
with "--strict"
Changes in v6:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [7].
- fixed some warnings/errors reported by kernel test robot <[email protected]>.
Changes in v5:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [6].
- dt-bindings: improved yaml, such as:
- add vendor prefix for system-ctrl property for clock generator.
- Add explanation for system-ctrl property.
- move sophgo,sg2042-clkgen.yaml to directly under clock folder.
- fixed bugs for driver Makefile/Kconfig
- continue cleaning-up debug print for driver code.
Changes in v4:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5].
- dt-bindings: fixed a dt_binding_check error.
Changes in v3:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3].
- DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4].
- Updating minor issues in dt-bindings as per input from reviews.
Changes in v2:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2].
- Squashed the patch adding clock definitions with the patch adding the binding for the clock controller.
- Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon.
- DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC.
- Fixed some bugs in driver code during testing, including removing warnings for rv32_defconfig.
- Updated MAINTAINERS info.
Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].
---
Chen Wang (5):
dt-bindings: clock: sophgo: add pll clocks for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add clkgen for SG2042
clk: sophgo: Add SG2042 clock driver
riscv: dts: add clock generator for Sophgo SG2042 SoC
.../bindings/clock/sophgo,sg2042-clkgen.yaml | 61 + .../bindings/clock/sophgo,sg2042-pll.yaml | 53 + .../bindings/clock/sophgo,sg2042-rpgate.yaml | 49 + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 +- drivers/clk/sophgo/Kconfig | 28 + drivers/clk/sophgo/Makefile | 4 + drivers/clk/sophgo/clk-sg2042-clkgen.c | 1152 +++++++++++++++++ drivers/clk/sophgo/clk-sg2042-pll.c | 570 ++++++++ drivers/clk/sophgo/clk-sg2042-rpgate.c | 291 +++++ drivers/clk/sophgo/clk-sg2042.h | 18 + .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 + .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 + 14 files changed, 2475 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml create mode 100644 drivers/clk/sophgo/clk-sg2042-clkgen.c create mode 100644 drivers/clk/sophgo/clk-sg2042-pll.c create mode 100644 drivers/clk/sophgo/clk-sg2042-rpgate.c create mode 100644 drivers/clk/sophgo/clk-sg2042.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
Signature · 1 line
2.25.1
PATCH v16 1/5 dt-bindings: clock: sophgo: add pll clocks for SG2042
From: Chen Wang <[email protected]>
Add bindings for the pll clocks for Sophgo SG2042.
--- .../bindings/clock/sophgo,sg2042-pll.yaml | 53 +++++++++++++++++++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 +++++ 2 files changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml new file +53 -0
@@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PLL Clock Generator + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) + + clock-names: + items: + - const: cgi_main + - const: cgi_dpll0 + - const: cgi_dpll1 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000000 { + compatible = "sophgo,sg2042-pll"; + reg = <0x10000000 0x10000>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1"; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-pll.h new file +14 -0
@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* +* Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. +*/ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ + +#define MPLL_CLK 0 +#define FPLL_CLK 1 +#define DPLL0_CLK 2 +#define DPLL1_CLK 3 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */
Signature · 1 line
2.25.1
PATCH v16 2/5 dt-bindings: clock: sophgo: add RP gate clocks for SG2042
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
--- .../bindings/clock/sophgo,sg2042-rpgate.yaml | 49 ++++++++++++++++ .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 +++++++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +49 -0
@@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-rpgate + + reg: + maxItems: 1 + + clocks: + items: + - description: Gate clock for RP subsystem + + clock-names: + items: + - const: rpgate + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@20000000 { + compatible = "sophgo,sg2042-rpgate"; + reg = <0x20000000 0x10000>; + clocks = <&clkgen 85>; + clock-names = "rpgate"; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-rpgate.h new file +58 -0
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Signature · 1 line
2.25.1
PATCH v16 3/5 dt-bindings: clock: sophgo: add clkgen for SG2042
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add bindings for the clock generator of divider/mux and gates working for other subsystem than RP subsystem for Sophgo SG2042.
--- .../bindings/clock/sophgo,sg2042-clkgen.yaml | 61 ++++++++++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++++++++++++++++++ 2 files changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml new file +61 -0
@@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Clock Generator for divider/mux/gate + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-clkgen + + reg: + maxItems: 1 + + clocks: + items: + - description: Main PLL + - description: Fixed PLL + - description: DDR PLL 0 + - description: DDR PLL 1 + + clock-names: + items: + - const: mpll + - const: fpll + - const: dpll0 + - const: dpll1 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@30012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x30012000 0x1000>; + clocks = <&pllclk 0>, + <&pllclk 1>, + <&pllclk 2>, + <&pllclk 3>; + clock-names = "mpll", + "fpll", + "dpll0", + "dpll1"; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-clkgen.h new file +111 -0
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Signature · 1 line
2.25.1
PATCH v16 4/5 clk: sophgo: Add SG2042 clock driver
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add a driver for the SOPHGO SG2042 clocks.
--- drivers/clk/sophgo/Kconfig | 28 + drivers/clk/sophgo/Makefile | 4 + drivers/clk/sophgo/clk-sg2042-clkgen.c | 1152 ++++++++++++++++++++++++ drivers/clk/sophgo/clk-sg2042-pll.c | 570 ++++++++++++ drivers/clk/sophgo/clk-sg2042-rpgate.c | 291 ++++++ drivers/clk/sophgo/clk-sg2042.h | 18 + 6 files changed, 2063 insertions(+) create mode 100644 drivers/clk/sophgo/clk-sg2042-clkgen.c create mode 100644 drivers/clk/sophgo/clk-sg2042-pll.c create mode 100644 drivers/clk/sophgo/clk-sg2042-rpgate.c create mode 100644 drivers/clk/sophgo/clk-sg2042.h
drivers/clk/sophgo/Kconfig +28 -0
@@ -9,3 +9,31 @@ config CLK_SOPHGO_CV1800 The driver require a 25MHz Oscillator to function generate clock. It includes PLLs, common clock function and some vendor clock for IPs of CV18XX series SoC + +config CLK_SOPHGO_SG2042_PLL + tristate "Sophgo SG2042 PLL clock support" + depends on ARCH_SOPHGO || COMPILE_TEST + help + This driver supports the PLL clock controller on the + Sophgo SG2042 SoC. This clock IP uses three oscillators with + frequency of 25 MHz as input, which are used for Main/Fixed + PLL, DDR PLL 0 and DDR PLL 1 respectively. + +config CLK_SOPHGO_SG2042_CLKGEN + tristate "Sophgo SG2042 Clock Generator support" + depends on CLK_SOPHGO_SG2042_PLL + help + This driver supports the Clock Generator on the + Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock + because it uses PLL clocks as input. + This driver provides clock function such as DIV/Mux/Gate. + +config CLK_SOPHGO_SG2042_RPGATE + tristate "Sophgo SG2042 RP subsystem clock controller support" + depends on CLK_SOPHGO_SG2042_CLKGEN + help + This driver supports the RP((Riscv Processors)) subsystem clock + controller on the Sophgo SG2042 SoC. + This clock IP depends on SG2042 Clock Generator because it uses + clock from Clock Generator IP as input. + This driver provides Gate function for RP.
drivers/clk/sophgo/Makefile +4 -0
@@ -5,3 +5,7 @@ clk-sophgo-cv1800-y += clk-cv1800.o clk-sophgo-cv1800-y += clk-cv18xx-common.o clk-sophgo-cv1800-y += clk-cv18xx-ip.o clk-sophgo-cv1800-y += clk-cv18xx-pll.o + +obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o +obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o +obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
drivers/clk/sophgo/clk-sg2042-clkgen.c new file +1152 -0
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drivers/clk/sophgo/clk-sg2042-pll.c new file +570 -0
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drivers/clk/sophgo/clk-sg2042-rpgate.c new file +291 -0
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drivers/clk/sophgo/clk-sg2042.h new file +18 -0
@@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _CLK_SOPHGO_SG2042_H_ +#define _CLK_SOPHGO_SG2042_H_ + +#include <linux/io.h> +#include <linux/clk-provider.h> + +/** +* struct sg2042_clk_data - Common data of clock-controller +* @iobase: base address of clock-controller +* @onecell_data: used for adding providers. +*/ +struct sg2042_clk_data { +void __iomem *iobase; +struct clk_hw_onecell_data onecell_data; +}; + +#endif /* _CLK_SOPHGO_SG2042_H_ */
Signature · 1 line
2.25.1
PATCH v16 5/5 riscv: dts: add clock generator for Sophgo SG2042 SoC
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add clock generator node to device tree for SG2042, and enable clock for uart.
--- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 ++++++++++++++++++- 2 files changed, 66 insertions(+), 1 deletion(-)
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +12 -0
@@ -14,6 +14,18 @@ chosen { }; }; +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; };
arch/riscv/boot/dts/sophgo/sg2042.dtsi +54 -1
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Signature · 1 line
2.25.1
ping ~~~
Quoted 221 lines · Chen Wang
From: Chen Wang <[email protected]>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen---
Changes in v16:
The patch series is based on v6.10-rc1.
Improved the dirvier code as per comments from Emil Renner Berthing.
- Split driver source file into three and change from built-in to module.
- Directly use status/enable pll register, no need to store them.
- Use FIELD_PREP/FIELD_GET to simplify the code.
- Some misc code improvements, such as for macro and local variables.Changes in v15:
The patch series is based on v6.9-rc5. You can simply review or test the patches at the link [16].
Improved the dirvier code as per 3rd review comments from Stephen Boyd.
- Converted all parents described by strings to useclk_parent_dataorclk_hwdirectly.
- Just use structclk_init_data::parent_hwswhen only have aclk_hw.
- Removed extra cleanup when use devm.
- Some misc code improvements.Changes in v14:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [15].
Improved the dirvier code as per 2nd review comments from Stephen Boyd.
- Inline the header file into source file.
- Usedevm_xxxfunctions for pll/div/gate registeration.
- Useclk_parent_datafor mux clocks initialization.
- Use u32 for registers readl/writel.
- Usedevm_platform_ioremap_resourceinstead ofdevm_of_iomap.
- Cleanup some dead code and add definitions for some magic numbers.
- Add include files missed.
- Use kernel-doc to improve comments for some structure and functions.
- Other misc code cleanup work as per input from reviewers.Changes in v13:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [14].
Just added a minor fix for clk driver which was missed in v12.
Changes in v12:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [13].
Improved the dirvier code as per review comments from Stephen Boyd.
- Remove default y forCLK_SOPHGO_SG2042.
- Optimizesg2042_pll_get_postdiv_1_2, movepostdiv1_2to the function. scope and add more explaniation.
- Optimizesg2042_get_pll_ctl_setting.
- Switch to platform driver.
- Useclk_hwfor initialization of struct clks.
- Don't useignore_unusedwhen using critical.
- Other code cleanup as per input form the reviewers.Changes in v11:
The patch series is based on v6.8-rc5. You can simply review or test the patches at the link [12].
Quick fixed some
dt_binding_checkerrors reported by Rob.Changes in v10:
The patch series is based on v6.8-rc4. You can simply review or test the patches at the link [11].
Add input clocks for rpgate & clkgen.
Changes in v9:
The patch series is based on v6.8-rc2. You can simply review or test the patches at the link [10].From this version, drop the system-controller node due to there is no actual device corresponding to it in IC design.
SYS_CTRLis just a registers segment defined on TRM for misc functions. Now three clock-controllers are defined for SG2042, the control registers of the three clock-controllers are scattered in different memory address spaces:
- the first one is for pll clocks;
- the second one is for gate clocks for RP subsystem;
- the third one is for div/mux, and gate clocks working for other subsystem than RP subsystem.Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9].In this version, the main change is to split one clock provider into two. Strictly follow the hardware instructions, in the memoymap, the control registers of some clocks are defined in the
SYS_CTRLsegment, and the control registers of other clocks are defined in the CLOCK segment. Therefore, the new design defines two clock controllers, one as a child node of the system control and the other as an independent clock controller node.This modification involves a major modification to the binding files, so the reviewed-by tags has been deleted.
Changes in v7:
The patch series is based on v6.7. You can simply review or test the patches at the link [8].
- fixed initval issue.
- fixed pll clk crash issue.
- fixed warning reported by <[email protected]>
- code optimization as per review comments.
- code cleanup and style improvements as per review comments and checkpatchwith "--strict"Changes in v6:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [7].
- fixed some warnings/errors reported by kernel test robot <[email protected]>.Changes in v5:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [6].
- dt-bindings: improved yaml, such as:
- add vendor prefix for system-ctrl property for clock generator.
- Add explanation for system-ctrl property.
- move sophgo,sg2042-clkgen.yaml to directly under clock folder.
- fixed bugs for driver Makefile/Kconfig
- continue cleaning-up debug print for driver code.Changes in v4:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5].
- dt-bindings: fixed adt_binding_checkerror.Changes in v3:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3].
- DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4].
- Updating minor issues in dt-bindings as per input from reviews.Changes in v2:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2].
- Squashed the patch adding clock definitions with the patch adding the binding for the clock controller.
- Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon.
- DTS changes: mergesg2042-clock.dtsiintosg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC.
- Fixed some bugs in driver code during testing, including removing warnings forrv32_defconfig.
- UpdatedMAINTAINERSinfo.Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].---
Chen Wang (5):
dt-bindings: clock: sophgo: add pll clocks for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add clkgen for SG2042
clk: sophgo: Add SG2042 clock driver
riscv: dts: add clock generator for Sophgo SG2042 SoC.../bindings/clock/sophgo,sg2042-clkgen.yaml | 61 + .../bindings/clock/sophgo,sg2042-pll.yaml | 53 + .../bindings/clock/sophgo,sg2042-rpgate.yaml | 49 + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 +- drivers/clk/sophgo/Kconfig | 28 + drivers/clk/sophgo/Makefile | 4 + drivers/clk/sophgo/clk-sg2042-clkgen.c | 1152 +++++++++++++++++ drivers/clk/sophgo/clk-sg2042-pll.c | 570 ++++++++ drivers/clk/sophgo/clk-sg2042-rpgate.c | 291 +++++ drivers/clk/sophgo/clk-sg2042.h | 18 + .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 + .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 + 14 files changed, 2475 insertions(+), 1 deletion(-)create mode 100644
Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yamlcreate mode 100644Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yamlcreate mode 100644Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yamlcreate mode 100644drivers/clk/sophgo/clk-sg2042-clkgen.c
create mode 100644drivers/clk/sophgo/clk-sg2042-pll.c
create mode 100644drivers/clk/sophgo/clk-sg2042-rpgate.c
create mode 100644drivers/clk/sophgo/clk-sg2042.h
create mode 100644include/dt-bindings/clock/sophgo,sg2042-clkgen.hcreate mode 100644include/dt-bindings/clock/sophgo,sg2042-pll.hcreate mode 100644include/dt-bindings/clock/sophgo,sg2042-rpgate.hbase-commit:
1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
Quoted 1 line · Chen Wang
ping ~~~
My suggestion is that you, as platform maintainer for sophgo, apply these patches and send Stephen a pull request. That's usually the best way to expedite patches for clock drivers.
Thanks,
Conor.
Quoted 222 lines · Chen Wang
Quoted 220 lines
From: Chen Wang <[email protected]>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen---
Changes in v16:
The patch series is based on v6.10-rc1.
Improved the dirvier code as per comments from Emil Renner Berthing.
- Split driver source file into three and change from built-in to module.
- Directly use status/enable pll register, no need to store them.
- Use FIELD_PREP/FIELD_GET to simplify the code.
- Some misc code improvements, such as for macro and local variables.Changes in v15:
The patch series is based on v6.9-rc5. You can simply review or test the patches at the link [16].
Improved the dirvier code as per 3rd review comments from Stephen Boyd.
- Converted all parents described by strings to useclk_parent_dataorclk_hwdirectly.
- Just use structclk_init_data::parent_hwswhen only have aclk_hw.
- Removed extra cleanup when use devm.
- Some misc code improvements.Changes in v14:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [15].
Improved the dirvier code as per 2nd review comments from Stephen Boyd.
- Inline the header file into source file.
- Usedevm_xxxfunctions for pll/div/gate registeration.
- Useclk_parent_datafor mux clocks initialization.
- Use u32 for registers readl/writel.
- Usedevm_platform_ioremap_resourceinstead ofdevm_of_iomap.
- Cleanup some dead code and add definitions for some magic numbers.
- Add include files missed.
- Use kernel-doc to improve comments for some structure and functions.
- Other misc code cleanup work as per input from reviewers.Changes in v13:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [14].
Just added a minor fix for clk driver which was missed in v12.
Changes in v12:
The patch series is based on v6.9-rc1. You can simply review or test the patches at the link [13].
Improved the dirvier code as per review comments from Stephen Boyd.
- Remove default y forCLK_SOPHGO_SG2042.
- Optimizesg2042_pll_get_postdiv_1_2, movepostdiv1_2to the function. scope and add more explaniation.
- Optimizesg2042_get_pll_ctl_setting.
- Switch to platform driver.
- Useclk_hwfor initialization of struct clks.
- Don't useignore_unusedwhen using critical.
- Other code cleanup as per input form the reviewers.Changes in v11:
The patch series is based on v6.8-rc5. You can simply review or test the patches at the link [12].
Quick fixed some
dt_binding_checkerrors reported by Rob.Changes in v10:
The patch series is based on v6.8-rc4. You can simply review or test the patches at the link [11].
Add input clocks for rpgate & clkgen.
Changes in v9:
The patch series is based on v6.8-rc2. You can simply review or test the patches at the link [10].From this version, drop the system-controller node due to there is no actual device corresponding to it in IC design.
SYS_CTRLis just a registers segment defined on TRM for misc functions. Now three clock-controllers are defined for SG2042, the control registers of the three clock-controllers are scattered in different memory address spaces:
- the first one is for pll clocks;
- the second one is for gate clocks for RP subsystem;
- the third one is for div/mux, and gate clocks working for other subsystem than RP subsystem.Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9].
In this version, the main change is to split one clock provider into two. Strictly follow the hardware instructions, in the memoymap, the control registers of some clocks are defined in theSYS_CTRLsegment, and the control registers of other clocks are defined in the CLOCK segment. Therefore, the new design defines two clock controllers, one as a child node of the system control and the other as an independent clock controller node.This modification involves a major modification to the binding files, so the reviewed-by tags has been deleted.
Changes in v7:
The patch series is based on v6.7. You can simply review or test the patches at the link [8].
- fixed initval issue.
- fixed pll clk crash issue.
- fixed warning reported by <[email protected]>
- code optimization as per review comments.
- code cleanup and style improvements as per review comments and checkpatchwith "--strict"Changes in v6:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [7].
- fixed some warnings/errors reported by kernel test robot <[email protected]>.Changes in v5:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [6].
- dt-bindings: improved yaml, such as:
- add vendor prefix for system-ctrl property for clock generator.
- Add explanation for system-ctrl property.
- move sophgo,sg2042-clkgen.yaml to directly under clock folder.
- fixed bugs for driver Makefile/Kconfig
- continue cleaning-up debug print for driver code.Changes in v4:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5].
- dt-bindings: fixed adt_binding_checkerror.Changes in v3:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3].
- DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4].
- Updating minor issues in dt-bindings as per input from reviews.Changes in v2:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2].
- Squashed the patch adding clock definitions with the patch adding the binding for the clock controller.
- Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon.
- DTS changes: mergesg2042-clock.dtsiintosg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC.
- Fixed some bugs in driver code during testing, including removing warnings forrv32_defconfig.
- UpdatedMAINTAINERSinfo.Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].---
Chen Wang (5):
dt-bindings: clock: sophgo: add pll clocks for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add clkgen for SG2042
clk: sophgo: Add SG2042 clock driver
riscv: dts: add clock generator for Sophgo SG2042 SoC.../bindings/clock/sophgo,sg2042-clkgen.yaml | 61 + .../bindings/clock/sophgo,sg2042-pll.yaml | 53 + .../bindings/clock/sophgo,sg2042-rpgate.yaml | 49 + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 +- drivers/clk/sophgo/Kconfig | 28 + drivers/clk/sophgo/Makefile | 4 + drivers/clk/sophgo/clk-sg2042-clkgen.c | 1152 +++++++++++++++++ drivers/clk/sophgo/clk-sg2042-pll.c | 570 ++++++++ drivers/clk/sophgo/clk-sg2042-rpgate.c | 291 +++++ drivers/clk/sophgo/clk-sg2042.h | 18 + .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 + .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 + 14 files changed, 2475 insertions(+), 1 deletion(-)create mode 100644
Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yamlcreate mode 100644Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yamlcreate mode 100644Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yamlcreate mode 100644drivers/clk/sophgo/clk-sg2042-clkgen.c
create mode 100644drivers/clk/sophgo/clk-sg2042-pll.c
create mode 100644drivers/clk/sophgo/clk-sg2042-rpgate.c
create mode 100644drivers/clk/sophgo/clk-sg2042.h
create mode 100644include/dt-bindings/clock/sophgo,sg2042-clkgen.hcreate mode 100644include/dt-bindings/clock/sophgo,sg2042-pll.hcreate mode 100644include/dt-bindings/clock/sophgo,sg2042-rpgate.hbase-commit:
1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
Quoted 8 lines · Conor Dooley
Quoted 1 line · Chen Wang
ping ~~~
My suggestion is that you, as platform maintainer for sophgo, apply these patches and send Stephen a pull request. That's usually the best way to expedite patches for clock drivers.
Thanks,
Conor.
Thank you, Conor, I will try this.
Regards,
Chen
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