riscv: sophgo: add clock support for sg2042
Subsystems (4)
v10 cover riscv: sophgo: add clock support for sg2042
From: Chen Wang <[email protected]>
This series adds clock controller support for sophgo sg2042.
Thanks,
Chen
---
Changes in v10:
The patch series is based on v6.8-rc4.
Add input clocks for rpgate & clkgen.
Changes in v9:
The patch series is based on v6.8-rc2. You can simply review or test the patches at the link [10].
From this version, drop the system-controller node due to there is no actual device corresponding to it in IC design. SYS_CTRL is just a registers segment defined on TRM for misc functions. Now three clock-controllers are defined for SG2042, the control registers of the three clock-controllers are scattered in different memory address spaces:
- the first one is for pll clocks;
- the second one is for gate clocks for RP subsystem;
- the third one is for div/mux, and gate clocks working for other subsystem than RP subsystem.
Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9].
In this version, the main change is to split one clock provider into two. Strictly follow the hardware instructions, in the memoymap, the control registers of some clocks are defined in the SYS_CTRL segment, and the control registers of other clocks are defined in the CLOCK segment. Therefore, the new design defines two clock controllers, one as a child node of the system control and the other as an independent clock controller node.
This modification involves a major modification to the binding files, so the reviewed-by tags has been deleted.
Changes in v7:
The patch series is based on v6.7. You can simply review or test the patches at the link [8].
- fixed initval issue.
- fixed pll clk crash issue.
- fixed warning reported by <[email protected]>
- code optimization as per review comments.
- code cleanup and style improvements as per review comments and checkpatch
with "--strict"
Changes in v6:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [7].
- fixed some warnings/errors reported by kernel test robot <[email protected]>.
Changes in v5:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [6].
- dt-bindings: improved yaml, such as:
- add vendor prefix for system-ctrl property for clock generator.
- Add explanation for system-ctrl property.
- move sophgo,sg2042-clkgen.yaml to directly under clock folder.
- fixed bugs for driver Makefile/Kconfig
- continue cleaning-up debug print for driver code.
Changes in v4:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5].
- dt-bindings: fixed a dt_binding_check error.
Changes in v3:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3].
- DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4].
- Updating minor issues in dt-bindings as per input from reviews.
Changes in v2:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2].
- Squashed the patch adding clock definitions with the patch adding the binding for the clock controller.
- Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon.
- DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC.
- Fixed some bugs in driver code during testing, including removing warnings for rv32_defconfig.
- Updated MAINTAINERS info.
Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].
---
Chen Wang (5):
dt-bindings: clock: sophgo: add pll clocks for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add clkgen for SG2042
clk: sophgo: Add SG2042 clock driver
riscv: dts: add clock generator for Sophgo SG2042 SoC
.../bindings/clock/sophgo,sg2042-clkgen.yaml | 49 + .../bindings/clock/sophgo,sg2042-pll.yaml | 45 + .../bindings/clock/sophgo,sg2042-rpgate.yaml | 43 + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 48 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 8 + drivers/clk/sophgo/Makefile | 2 + drivers/clk/sophgo/clk-sophgo-sg2042.c | 1401 +++++++++++++++++ drivers/clk/sophgo/clk-sophgo-sg2042.h | 233 +++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 + .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 + 14 files changed, 2026 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
base-commit: 841c35169323cd833294798e58b9bf63fa4fa1de
Signature · 1 line
2.25.1
PATCH v10 1/5 dt-bindings: clock: sophgo: add pll clocks for SG2042
From: Chen Wang <[email protected]>
Add bindings for the pll clocks for Sophgo SG2042.
--- .../bindings/clock/sophgo,sg2042-pll.yaml | 45 +++++++++++++++++++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++ 2 files changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml new file +45 -0
@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PLL Clock Generator + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000000 { + compatible = "sophgo,sg2042-pll"; + reg = <0x10000000 0x10000>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-pll.h new file +14 -0
@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* +* Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. +*/ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ + +#define MPLL_CLK 0 +#define FPLL_CLK 1 +#define DPLL0_CLK 2 +#define DPLL1_CLK 3 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */
Signature · 1 line
2.25.1
Re: [PATCH v10 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042
Quoted 86 lines · Chen Wang
From: Chen Wang <[email protected]>
Add bindings for the pll clocks for Sophgo SG2042.
Signed-off-by Chen Wang <[email protected]>Reviewed-by Rob Herring <[email protected]>--- .../bindings/clock/sophgo,sg2042-pll.yaml | 45 +++++++++++++++++++ include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++ 2 files changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.hDocumentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml new file +45
-0@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PLL Clock Generator + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-pll + + reg: + maxItems: 1 + + clocks: + items: + - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz) + - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000000 { + compatible = "sophgo,sg2042-pll"; + reg = <0x10000000 0x10000>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + };include/dt-bindings/clock/sophgo,sg2042-pll.h new file +14
-1@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* +* Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. +*/ + +#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ + +#define MPLL_CLK 0 +#define FPLL_CLK 1 +#define DPLL0_CLK 2 +#define DPLL1_CLK 3 + +#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */ --
Quoted 2 lines
2.25.1
Signature · 2 lines
Best Regards Guo Ren
PATCH v10 2/5 dt-bindings: clock: sophgo: add RP gate clocks for SG2042
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
--- .../bindings/clock/sophgo,sg2042-rpgate.yaml | 43 ++++++++++++++ .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 +++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +43 -0
@@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-rpgate + + reg: + maxItems: 1 + + clocks: + items: + - description: Gate clock for RP subsystem + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10000000 { + compatible = "sophgo,sg2042-rpgate"; + reg = <0x10000000 0x10000>; + clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-rpgate.h new file +58 -0
58 lines not on this page · raw message
Signature · 1 line
2.25.1
Rob Herring
maintainerRe: [PATCH v10 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042
Quoted 4 lines · Chen Wang
From: Chen Wang <[email protected]>
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
Quoted 8 lines
Signed-off-by Chen Wang <[email protected]>--- .../bindings/clock/sophgo,sg2042-rpgate.yaml | 43 ++++++++++++++ .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 +++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.example.dts:21.29-30 syntax error FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1428: dt_binding_check] Error 2
make: *** [Makefile:240: __sub-make] Error 2
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
PATCH v10 3/5 dt-bindings: clock: sophgo: add clkgen for SG2042
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add bindings for the clock generator of divider/mux and gates working for other subsystem than RP subsystem for Sophgo SG2042.
--- .../bindings/clock/sophgo,sg2042-clkgen.yaml | 49 ++++++++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++++++++++++++++++ 2 files changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml new file +49 -0
@@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Clock Generator for divider/mux/gate + +maintainers: + - Chen Wang <[email protected]> + +properties: + compatible: + const: sophgo,sg2042-clkgen + + reg: + maxItems: 1 + + clocks: + items: + - description: Main PLL + - description: Fixed PLL + - description: DDR PLL 0 + - description: DDR PLL 1 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@30012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x30012000 0x1000>; + clocks = <&pllclk MPLL_CLK>, + <&pllclk FPLL_CLK>, + <&pllclk DPLL0_CLK>, + <&pllclk DPLL1_CLK>; + #clock-cells = <1>; + };
include/dt-bindings/clock/sophgo,sg2042-clkgen.h new file +111 -0
111 lines not on this page · raw message
Signature · 1 line
2.25.1
Rob Herring
maintainerRe: [PATCH v10 3/5] dt-bindings: clock: sophgo: add clkgen for SG2042
Quoted 5 lines · Chen Wang
From: Chen Wang <[email protected]>
Add bindings for the clock generator of divider/mux and gates working for other subsystem than RP subsystem for Sophgo SG2042.
Quoted 8 lines
Signed-off-by Chen Wang <[email protected]>--- .../bindings/clock/sophgo,sg2042-clkgen.yaml | 49 ++++++++ .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++++++++++++++++++ 2 files changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
PATCH v10 4/5 clk: sophgo: Add SG2042 clock driver
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add a driver for the SOPHGO SG2042 clocks.
--- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 8 + drivers/clk/sophgo/Makefile | 2 + drivers/clk/sophgo/clk-sophgo-sg2042.c | 1401 ++++++++++++++++++++++++ drivers/clk/sophgo/clk-sophgo-sg2042.h | 233 ++++ 6 files changed, 1646 insertions(+) create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
drivers/clk/Kconfig +1 -0
@@ -489,6 +489,7 @@ source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/socfpga/Kconfig" +source "drivers/clk/sophgo/Kconfig" source "drivers/clk/sprd/Kconfig" source "drivers/clk/starfive/Kconfig" source "drivers/clk/sunxi/Kconfig"
drivers/clk/Makefile +1 -0
@@ -118,6 +118,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-y += socfpga/ +obj-y += sophgo/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_ARCH_STI) += st/
drivers/clk/sophgo/Kconfig new file +8 -0
@@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 + +config CLK_SOPHGO_SG2042 + bool "Sophgo SG2042 clock support" + depends on ARCH_SOPHGO || COMPILE_TEST + default y + help + Say yes here to support the clock controller on the Sophgo SG2042 SoC.
drivers/clk/sophgo/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_CLK_SOPHGO_SG2042) += clk-sophgo-sg2042.o
drivers/clk/sophgo/clk-sophgo-sg2042.c new file +1401 -0
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drivers/clk/sophgo/clk-sophgo-sg2042.h new file +233 -0
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Signature · 1 line
2.25.1
PATCH v10 5/5 riscv: dts: add clock generator for Sophgo SG2042 SoC
In reply to Chen WangFrom: Chen Wang <[email protected]>
Add clock generator node to device tree for SG2042, and enable clock for uart.
--- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 48 +++++++++++++++++++ 2 files changed, 60 insertions(+)
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +12 -0
@@ -14,6 +14,18 @@ chosen { }; }; +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; };
arch/riscv/boot/dts/sophgo/sg2042.dtsi +48 -0
72 lines not on this page · raw message
Signature · 1 line
2.25.1
Re: [PATCH v10 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC
Quoted 22 lines · Chen Wang
From: Chen Wang <[email protected]>
Add clock generator node to device tree for SG2042, and enable clock for uart.
Signed-off-by Chen Wang <[email protected]>--- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 48 +++++++++++++++++++ 2 files changed, 60 insertions(+)arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +2
-0@@ -14,6 +14,18 @@ chosen { }; }; +&cgi_main { + clock-frequency = <25000000>;
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts chosen { · line 28
Quoted 10 lines
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +10
-0+}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; +
If all are fixed, why do we separate them into three pieces? To show real internal hardware?
Quoted 83 lines
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +0
-0&uart0 { status = "okay"; };arch/riscv/boot/dts/sophgo/sg2042.dtsi +48
-1@@ -5,6 +5,9 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sophgo,sg2042-pll.h> +#include <dt-bindings/clock/sophgo,sg2042-rpgate.h> +#include <dt-bindings/clock/sophgo,sg2042-clkgen.h> #include "sg2042-cpus.dtsi"@@ -18,12 +21,54 @@ aliases { serial0 = &uart0; }; + cgi_main: oscillator0 { + compatible = "fixed-clock"; + clock-output-names = "cgi_main"; + #clock-cells = <0>; + }; + + cgi_dpll0: oscillator1 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll0"; + #clock-cells = <0>; + }; + + cgi_dpll1: oscillator2 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll1"; + #clock-cells = <0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; + pllclk: clock-controller@70300100c0 { + compatible = "sophgo,sg2042-pll"; + reg = <0x70 0x300100c0 0x0 0x40>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; + + rpgate: clock-controller@7030010368 { + compatible = "sophgo,sg2042-rpgate"; + reg = <0x70 0x30010368 0x0 0x98>; + clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; + #clock-cells = <1>; + }; + + clkgen: clock-controller@7030012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x70 0x30012000 0x0 0x1000>; + clocks = <&pllclk MPLL_CLK>, + <&pllclk FPLL_CLK>, + <&pllclk DPLL0_CLK>, + <&pllclk DPLL1_CLK>; + #clock-cells = <1>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>;@@ -333,6 +378,9 @@ uart0: serial@7040000000 { interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; + clocks = <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; --
Quoted 2 lines
2.25.1
Others LGTM.
Signature · 2 lines
Best Regards Guo Ren
Re: [PATCH v10 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC
Quoted 20 lines · Guo Ren
Quoted 19 lines · Chen Wang
From: Chen Wang <[email protected]>
Add clock generator node to device tree for SG2042, and enable clock for uart.
Signed-off-by Chen Wang <[email protected]>--- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 48 +++++++++++++++++++ 2 files changed, 60 insertions(+)arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +0
-0@@ -14,6 +14,18 @@ chosen { }; };
Quoted 14 lines
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts chosen { · line 28
Quoted 12 lines
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +12
-0+&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; +If all are fixed, why do we separate them into three pieces? To show real internal hardware?
Yes, according to TRM, there are three input cgi(Clock Generator IC) on board.
Quoted 90 lines
Quoted 84 lines
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +0
-0&uart0 { status = "okay"; };arch/riscv/boot/dts/sophgo/sg2042.dtsi +48
-1@@ -5,6 +5,9 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sophgo,sg2042-pll.h> +#include <dt-bindings/clock/sophgo,sg2042-rpgate.h> +#include <dt-bindings/clock/sophgo,sg2042-clkgen.h> #include "sg2042-cpus.dtsi"@@ -18,12 +21,54 @@ aliases { serial0 = &uart0; }; + cgi_main: oscillator0 { + compatible = "fixed-clock"; + clock-output-names = "cgi_main"; + #clock-cells = <0>; + }; + + cgi_dpll0: oscillator1 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll0"; + #clock-cells = <0>; + }; + + cgi_dpll1: oscillator2 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll1"; + #clock-cells = <0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; + pllclk: clock-controller@70300100c0 { + compatible = "sophgo,sg2042-pll"; + reg = <0x70 0x300100c0 0x0 0x40>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; + + rpgate: clock-controller@7030010368 { + compatible = "sophgo,sg2042-rpgate"; + reg = <0x70 0x30010368 0x0 0x98>; + clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; + #clock-cells = <1>; + }; + + clkgen: clock-controller@7030012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x70 0x30012000 0x0 0x1000>; + clocks = <&pllclk MPLL_CLK>, + <&pllclk FPLL_CLK>, + <&pllclk DPLL0_CLK>, + <&pllclk DPLL1_CLK>; + #clock-cells = <1>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>;@@ -333,6 +378,9 @@ uart0: serial@7040000000 { interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; + clocks = <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; --Quoted 2 lines
2.25.1
Others LGTM.
Reviewed-by Guo Ren <[email protected]>