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riscv: sophgo: add clock support for sg2042

PATCH Superseded Chen Wang 6 participants 19 messages Nov 13, 2023 – Nov 19, 2023

Subsystems (4)
Device tree bindings Common clk RISC-V Sophgo devicetrees and drivers

v1 of 16 Superseded Latest is v16 →

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Chen Wang

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#0 lore raw

cover riscv: sophgo: add clock support for sg2042

From: Chen Wang <[email protected]>

This series adds clock controller support for sophgo sg2042.

Chen Wang (5):
dt-bindings: clock: sophgo: Add SG2042 clock definitions
dt-bindings: soc: sophgo: Add Sophgo syscon module
dt-bindings: clock: sophgo: Add SG2042 bindings
clk: sophgo: Add SG2042 clock generator driver
riscv: dts: add clock generator for Sophgo SG2042 SoC

 .../clock/sophgo/sophgo,sg2042-clkgen.yaml    |   48 +
 .../soc/sophgo/sophgo,sg2042-syscon.yaml      |   38 +
 MAINTAINERS                                   |    8 +
 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi  |   76 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |   10 +
 drivers/clk/Kconfig                           |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/sophgo/Kconfig                    |    8 +
 drivers/clk/sophgo/Makefile                   |    2 +
 drivers/clk/sophgo/clk-sophgo-sg2042.c        | 1259 +++++++++++++++++
 drivers/clk/sophgo/clk-sophgo-sg2042.h        |  226 +++
 include/dt-bindings/clock/sophgo-sg2042-clk.h |  169 +++
 12 files changed, 1846 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
 create mode 100644 include/dt-bindings/clock/sophgo-sg2042-clk.h

base-commit: b85ea95d086471afb4ad062012a4d73cd328fa86

Signature · 1 line
2.25.1
author
#1 lore raw

PATCH 1/5 dt-bindings: clock: sophgo: Add SG2042 clock definitions

From: Chen Wang <[email protected]>

Add all clock outputs for the Sophgo SG2042 clock generator.

Signed-off-by Chen Wang <[email protected]>
---
 include/dt-bindings/clock/sophgo-sg2042-clk.h | 169 ++++++++++++++++++
 1 file changed, 169 insertions(+)
 create mode 100644 include/dt-bindings/clock/sophgo-sg2042-clk.h
include/dt-bindings/clock/sophgo-sg2042-clk.h new file +169 -0
new file mode 100644
index 000000000000..a8e05c00c3bf
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
+#define __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
+
+/* Divider clocks */
+#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
+#define DIV_CLK_MPLL_AXI_DDR_0 1
+#define DIV_CLK_FPLL_DDR01_1 2
+#define DIV_CLK_FPLL_DDR23_1 3
+#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4
+#define DIV_CLK_FPLL_50M_A53 5
+#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6
+#define DIV_CLK_FPLL_UART_500M 7
+#define DIV_CLK_FPLL_AHB_LPC 8
+#define DIV_CLK_FPLL_EFUSE 9
+#define DIV_CLK_FPLL_TX_ETH0 10
+#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11
+#define DIV_CLK_FPLL_REF_ETH0 12
+#define DIV_CLK_FPLL_EMMC 13
+#define DIV_CLK_FPLL_SD 14
+#define DIV_CLK_FPLL_TOP_AXI0 15
+#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16
+#define DIV_CLK_FPLL_AXI_DDR_1 17
+#define DIV_CLK_FPLL_DIV_TIMER1 18
+#define DIV_CLK_FPLL_DIV_TIMER2 19
+#define DIV_CLK_FPLL_DIV_TIMER3 20
+#define DIV_CLK_FPLL_DIV_TIMER4 21
+#define DIV_CLK_FPLL_DIV_TIMER5 22
+#define DIV_CLK_FPLL_DIV_TIMER6 23
+#define DIV_CLK_FPLL_DIV_TIMER7 24
+#define DIV_CLK_FPLL_DIV_TIMER8 25
+#define DIV_CLK_FPLL_100K_EMMC 26
+#define DIV_CLK_FPLL_100K_SD 27
+#define DIV_CLK_FPLL_GPIO_DB 28
+#define DIV_CLK_DPLL0_DDR01_0 29
+#define DIV_CLK_DPLL1_DDR23_0 30
+
+/* Gate clocks */
+#define GATE_CLK_RP_CPU_NORMAL_DIV0 31
+#define GATE_CLK_AXI_DDR_DIV0 32
+
+#define GATE_CLK_RP_CPU_NORMAL_DIV1 33
+#define GATE_CLK_A53_50M 34
+#define GATE_CLK_TOP_RP_CMN_DIV2 35
+#define GATE_CLK_HSDMA 36
+#define GATE_CLK_EMMC_100M 37
+#define GATE_CLK_SD_100M 38
+#define GATE_CLK_TX_ETH0 39
+#define GATE_CLK_PTP_REF_I_ETH0 40
+#define GATE_CLK_REF_ETH0 41
+#define GATE_CLK_UART_500M 42
+#define GATE_CLK_EFUSE 43
+
+#define GATE_CLK_AHB_LPC 44
+#define GATE_CLK_AHB_ROM 45
+#define GATE_CLK_AHB_SF 46
+
+#define GATE_CLK_APB_UART 47
+#define GATE_CLK_APB_TIMER 48
+#define GATE_CLK_APB_EFUSE 49
+#define GATE_CLK_APB_GPIO 50
+#define GATE_CLK_APB_GPIO_INTR 51
+#define GATE_CLK_APB_SPI 52
+#define GATE_CLK_APB_I2C 53
+#define GATE_CLK_APB_WDT 54
+#define GATE_CLK_APB_PWM 55
+#define GATE_CLK_APB_RTC 56
+
+#define GATE_CLK_AXI_PCIE0 57
+#define GATE_CLK_AXI_PCIE1 58
+#define GATE_CLK_SYSDMA_AXI 59
+#define GATE_CLK_AXI_DBG_I2C 60
+#define GATE_CLK_AXI_SRAM 61
+#define GATE_CLK_AXI_ETH0 62
+#define GATE_CLK_AXI_EMMC 63
+#define GATE_CLK_AXI_SD 64
+#define GATE_CLK_TOP_AXI0 65
+#define GATE_CLK_TOP_AXI_HSPERI 66
+
+#define GATE_CLK_TIMER1 67
+#define GATE_CLK_TIMER2 68
+#define GATE_CLK_TIMER3 69
+#define GATE_CLK_TIMER4 70
+#define GATE_CLK_TIMER5 71
+#define GATE_CLK_TIMER6 72
+#define GATE_CLK_TIMER7 73
+#define GATE_CLK_TIMER8 74
+#define GATE_CLK_100K_EMMC 75
+#define GATE_CLK_100K_SD 76
+#define GATE_CLK_GPIO_DB 77
+
+#define GATE_CLK_AXI_DDR_DIV1 78
+#define GATE_CLK_DDR01_DIV1 79
+#define GATE_CLK_DDR23_DIV1 80
+/* DPLL0 */
+#define GATE_CLK_DDR01_DIV0 81
+/* DPLL1 */
+#define GATE_CLK_DDR23_DIV0 82
+
+#define GATE_CLK_DDR01 83
+#define GATE_CLK_DDR23 84
+#define GATE_CLK_RP_CPU_NORMAL 85
+#define GATE_CLK_AXI_DDR 86
+#define GATE_CLK_RXU0 87
+#define GATE_CLK_RXU1 88
+#define GATE_CLK_RXU2 89
+#define GATE_CLK_RXU3 90
+#define GATE_CLK_RXU4 91
+#define GATE_CLK_RXU5 92
+#define GATE_CLK_RXU6 93
+#define GATE_CLK_RXU7 94
+#define GATE_CLK_RXU8 95
+#define GATE_CLK_RXU9 96
+#define GATE_CLK_RXU10 97
+#define GATE_CLK_RXU11 98
+#define GATE_CLK_RXU12 99
+#define GATE_CLK_RXU13 100
+#define GATE_CLK_RXU14 101
+#define GATE_CLK_RXU15 102
+#define GATE_CLK_RXU16 103
+#define GATE_CLK_RXU17 104
+#define GATE_CLK_RXU18 105
+#define GATE_CLK_RXU19 106
+#define GATE_CLK_RXU20 107
+#define GATE_CLK_RXU21 108
+#define GATE_CLK_RXU22 109
+#define GATE_CLK_RXU23 110
+#define GATE_CLK_RXU24 111
+#define GATE_CLK_RXU25 112
+#define GATE_CLK_RXU26 113
+#define GATE_CLK_RXU27 114
+#define GATE_CLK_RXU28 115
+#define GATE_CLK_RXU29 116
+#define GATE_CLK_RXU30 117
+#define GATE_CLK_RXU31 118
+#define GATE_CLK_MP0 119
+#define GATE_CLK_MP1 120
+#define GATE_CLK_MP2 121
+#define GATE_CLK_MP3 122
+#define GATE_CLK_MP4 123
+#define GATE_CLK_MP5 124
+#define GATE_CLK_MP6 125
+#define GATE_CLK_MP7 126
+#define GATE_CLK_MP8 127
+#define GATE_CLK_MP9 128
+#define GATE_CLK_MP10 129
+#define GATE_CLK_MP11 130
+#define GATE_CLK_MP12 131
+#define GATE_CLK_MP13 132
+#define GATE_CLK_MP14 133
+#define GATE_CLK_MP15 134
+
+/* MUX clocks */
+#define MUX_CLK_DDR01 135
+#define MUX_CLK_DDR23 136
+#define MUX_CLK_RP_CPU_NORMAL 137
+#define MUX_CLK_AXI_DDR 138
+
+/* PLL clocks */
+#define MPLL_CLK	139
+#define FPLL_CLK	140
+#define DPLL0_CLK	141
+#define DPLL1_CLK	142
+
+#endif /* __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__ */
Signature · 1 line
2.25.1
#2 lore raw

Re: [PATCH 1/5] dt-bindings: clock: sophgo: Add SG2042 clock definitions

Quoted 3 lines · Chen Wang

From: Chen Wang <[email protected]>

Add all clock outputs for the Sophgo SG2042 clock generator.

This patch can be squashed with the patch adding the binding for the clock controller.

Cheers,
Conor.

Quoted 185 lines
Signed-off-by Chen Wang <[email protected]>
---
 include/dt-bindings/clock/sophgo-sg2042-clk.h | 169 ++++++++++++++++++
 1 file changed, 169 insertions(+)
 create mode 100644 include/dt-bindings/clock/sophgo-sg2042-clk.h
include/dt-bindings/clock/sophgo-sg2042-clk.h new file +169 -0
new file mode 100644
index 000000000000..a8e05c00c3bf
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
+#define __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
+
+/* Divider clocks */
+#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
+#define DIV_CLK_MPLL_AXI_DDR_0 1
+#define DIV_CLK_FPLL_DDR01_1 2
+#define DIV_CLK_FPLL_DDR23_1 3
+#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4
+#define DIV_CLK_FPLL_50M_A53 5
+#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6
+#define DIV_CLK_FPLL_UART_500M 7
+#define DIV_CLK_FPLL_AHB_LPC 8
+#define DIV_CLK_FPLL_EFUSE 9
+#define DIV_CLK_FPLL_TX_ETH0 10
+#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11
+#define DIV_CLK_FPLL_REF_ETH0 12
+#define DIV_CLK_FPLL_EMMC 13
+#define DIV_CLK_FPLL_SD 14
+#define DIV_CLK_FPLL_TOP_AXI0 15
+#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16
+#define DIV_CLK_FPLL_AXI_DDR_1 17
+#define DIV_CLK_FPLL_DIV_TIMER1 18
+#define DIV_CLK_FPLL_DIV_TIMER2 19
+#define DIV_CLK_FPLL_DIV_TIMER3 20
+#define DIV_CLK_FPLL_DIV_TIMER4 21
+#define DIV_CLK_FPLL_DIV_TIMER5 22
+#define DIV_CLK_FPLL_DIV_TIMER6 23
+#define DIV_CLK_FPLL_DIV_TIMER7 24
+#define DIV_CLK_FPLL_DIV_TIMER8 25
+#define DIV_CLK_FPLL_100K_EMMC 26
+#define DIV_CLK_FPLL_100K_SD 27
+#define DIV_CLK_FPLL_GPIO_DB 28
+#define DIV_CLK_DPLL0_DDR01_0 29
+#define DIV_CLK_DPLL1_DDR23_0 30
+
+/* Gate clocks */
+#define GATE_CLK_RP_CPU_NORMAL_DIV0 31
+#define GATE_CLK_AXI_DDR_DIV0 32
+
+#define GATE_CLK_RP_CPU_NORMAL_DIV1 33
+#define GATE_CLK_A53_50M 34
+#define GATE_CLK_TOP_RP_CMN_DIV2 35
+#define GATE_CLK_HSDMA 36
+#define GATE_CLK_EMMC_100M 37
+#define GATE_CLK_SD_100M 38
+#define GATE_CLK_TX_ETH0 39
+#define GATE_CLK_PTP_REF_I_ETH0 40
+#define GATE_CLK_REF_ETH0 41
+#define GATE_CLK_UART_500M 42
+#define GATE_CLK_EFUSE 43
+
+#define GATE_CLK_AHB_LPC 44
+#define GATE_CLK_AHB_ROM 45
+#define GATE_CLK_AHB_SF 46
+
+#define GATE_CLK_APB_UART 47
+#define GATE_CLK_APB_TIMER 48
+#define GATE_CLK_APB_EFUSE 49
+#define GATE_CLK_APB_GPIO 50
+#define GATE_CLK_APB_GPIO_INTR 51
+#define GATE_CLK_APB_SPI 52
+#define GATE_CLK_APB_I2C 53
+#define GATE_CLK_APB_WDT 54
+#define GATE_CLK_APB_PWM 55
+#define GATE_CLK_APB_RTC 56
+
+#define GATE_CLK_AXI_PCIE0 57
+#define GATE_CLK_AXI_PCIE1 58
+#define GATE_CLK_SYSDMA_AXI 59
+#define GATE_CLK_AXI_DBG_I2C 60
+#define GATE_CLK_AXI_SRAM 61
+#define GATE_CLK_AXI_ETH0 62
+#define GATE_CLK_AXI_EMMC 63
+#define GATE_CLK_AXI_SD 64
+#define GATE_CLK_TOP_AXI0 65
+#define GATE_CLK_TOP_AXI_HSPERI 66
+
+#define GATE_CLK_TIMER1 67
+#define GATE_CLK_TIMER2 68
+#define GATE_CLK_TIMER3 69
+#define GATE_CLK_TIMER4 70
+#define GATE_CLK_TIMER5 71
+#define GATE_CLK_TIMER6 72
+#define GATE_CLK_TIMER7 73
+#define GATE_CLK_TIMER8 74
+#define GATE_CLK_100K_EMMC 75
+#define GATE_CLK_100K_SD 76
+#define GATE_CLK_GPIO_DB 77
+
+#define GATE_CLK_AXI_DDR_DIV1 78
+#define GATE_CLK_DDR01_DIV1 79
+#define GATE_CLK_DDR23_DIV1 80
+/* DPLL0 */
+#define GATE_CLK_DDR01_DIV0 81
+/* DPLL1 */
+#define GATE_CLK_DDR23_DIV0 82
+
+#define GATE_CLK_DDR01 83
+#define GATE_CLK_DDR23 84
+#define GATE_CLK_RP_CPU_NORMAL 85
+#define GATE_CLK_AXI_DDR 86
+#define GATE_CLK_RXU0 87
+#define GATE_CLK_RXU1 88
+#define GATE_CLK_RXU2 89
+#define GATE_CLK_RXU3 90
+#define GATE_CLK_RXU4 91
+#define GATE_CLK_RXU5 92
+#define GATE_CLK_RXU6 93
+#define GATE_CLK_RXU7 94
+#define GATE_CLK_RXU8 95
+#define GATE_CLK_RXU9 96
+#define GATE_CLK_RXU10 97
+#define GATE_CLK_RXU11 98
+#define GATE_CLK_RXU12 99
+#define GATE_CLK_RXU13 100
+#define GATE_CLK_RXU14 101
+#define GATE_CLK_RXU15 102
+#define GATE_CLK_RXU16 103
+#define GATE_CLK_RXU17 104
+#define GATE_CLK_RXU18 105
+#define GATE_CLK_RXU19 106
+#define GATE_CLK_RXU20 107
+#define GATE_CLK_RXU21 108
+#define GATE_CLK_RXU22 109
+#define GATE_CLK_RXU23 110
+#define GATE_CLK_RXU24 111
+#define GATE_CLK_RXU25 112
+#define GATE_CLK_RXU26 113
+#define GATE_CLK_RXU27 114
+#define GATE_CLK_RXU28 115
+#define GATE_CLK_RXU29 116
+#define GATE_CLK_RXU30 117
+#define GATE_CLK_RXU31 118
+#define GATE_CLK_MP0 119
+#define GATE_CLK_MP1 120
+#define GATE_CLK_MP2 121
+#define GATE_CLK_MP3 122
+#define GATE_CLK_MP4 123
+#define GATE_CLK_MP5 124
+#define GATE_CLK_MP6 125
+#define GATE_CLK_MP7 126
+#define GATE_CLK_MP8 127
+#define GATE_CLK_MP9 128
+#define GATE_CLK_MP10 129
+#define GATE_CLK_MP11 130
+#define GATE_CLK_MP12 131
+#define GATE_CLK_MP13 132
+#define GATE_CLK_MP14 133
+#define GATE_CLK_MP15 134
+
+/* MUX clocks */
+#define MUX_CLK_DDR01 135
+#define MUX_CLK_DDR23 136
+#define MUX_CLK_RP_CPU_NORMAL 137
+#define MUX_CLK_AXI_DDR 138
+
+/* PLL clocks */
+#define MPLL_CLK	139
+#define FPLL_CLK	140
+#define DPLL0_CLK	141
+#define DPLL1_CLK	142
+
+#endif /* __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__ */
Signature · 1 line
2.25.1
#3 lore raw

Re: [PATCH 1/5] dt-bindings: clock: sophgo: Add SG2042 clock definitions

Quoted 9 lines · Conor Dooley
Quoted 3 lines · Chen Wang

From: Chen Wang <[email protected]>

Add all clock outputs for the Sophgo SG2042 clock generator.

This patch can be squashed with the patch adding the binding for the clock controller.

Cheers,
Conor.

Thanks, I will handle this in next revision.

Quoted 184 lines
Quoted 184 lines
Signed-off-by Chen Wang <[email protected]>
---
  include/dt-bindings/clock/sophgo-sg2042-clk.h | 169 ++++++++++++++++++
  1 file changed, 169 insertions(+)

create mode 100644 include/dt-bindings/clock/sophgo-sg2042-clk.h

include/dt-bindings/clock/sophgo-sg2042-clk.h new file +169 -0
new file mode 100644
index 000000000000..a8e05c00c3bf
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
+#define __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
+
+/* Divider clocks */
+#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
+#define DIV_CLK_MPLL_AXI_DDR_0 1
+#define DIV_CLK_FPLL_DDR01_1 2
+#define DIV_CLK_FPLL_DDR23_1 3
+#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4
+#define DIV_CLK_FPLL_50M_A53 5
+#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6
+#define DIV_CLK_FPLL_UART_500M 7
+#define DIV_CLK_FPLL_AHB_LPC 8
+#define DIV_CLK_FPLL_EFUSE 9
+#define DIV_CLK_FPLL_TX_ETH0 10
+#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11
+#define DIV_CLK_FPLL_REF_ETH0 12
+#define DIV_CLK_FPLL_EMMC 13
+#define DIV_CLK_FPLL_SD 14
+#define DIV_CLK_FPLL_TOP_AXI0 15
+#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16
+#define DIV_CLK_FPLL_AXI_DDR_1 17
+#define DIV_CLK_FPLL_DIV_TIMER1 18
+#define DIV_CLK_FPLL_DIV_TIMER2 19
+#define DIV_CLK_FPLL_DIV_TIMER3 20
+#define DIV_CLK_FPLL_DIV_TIMER4 21
+#define DIV_CLK_FPLL_DIV_TIMER5 22
+#define DIV_CLK_FPLL_DIV_TIMER6 23
+#define DIV_CLK_FPLL_DIV_TIMER7 24
+#define DIV_CLK_FPLL_DIV_TIMER8 25
+#define DIV_CLK_FPLL_100K_EMMC 26
+#define DIV_CLK_FPLL_100K_SD 27
+#define DIV_CLK_FPLL_GPIO_DB 28
+#define DIV_CLK_DPLL0_DDR01_0 29
+#define DIV_CLK_DPLL1_DDR23_0 30
+
+/* Gate clocks */
+#define GATE_CLK_RP_CPU_NORMAL_DIV0 31
+#define GATE_CLK_AXI_DDR_DIV0 32
+
+#define GATE_CLK_RP_CPU_NORMAL_DIV1 33
+#define GATE_CLK_A53_50M 34
+#define GATE_CLK_TOP_RP_CMN_DIV2 35
+#define GATE_CLK_HSDMA 36
+#define GATE_CLK_EMMC_100M 37
+#define GATE_CLK_SD_100M 38
+#define GATE_CLK_TX_ETH0 39
+#define GATE_CLK_PTP_REF_I_ETH0 40
+#define GATE_CLK_REF_ETH0 41
+#define GATE_CLK_UART_500M 42
+#define GATE_CLK_EFUSE 43
+
+#define GATE_CLK_AHB_LPC 44
+#define GATE_CLK_AHB_ROM 45
+#define GATE_CLK_AHB_SF 46
+
+#define GATE_CLK_APB_UART 47
+#define GATE_CLK_APB_TIMER 48
+#define GATE_CLK_APB_EFUSE 49
+#define GATE_CLK_APB_GPIO 50
+#define GATE_CLK_APB_GPIO_INTR 51
+#define GATE_CLK_APB_SPI 52
+#define GATE_CLK_APB_I2C 53
+#define GATE_CLK_APB_WDT 54
+#define GATE_CLK_APB_PWM 55
+#define GATE_CLK_APB_RTC 56
+
+#define GATE_CLK_AXI_PCIE0 57
+#define GATE_CLK_AXI_PCIE1 58
+#define GATE_CLK_SYSDMA_AXI 59
+#define GATE_CLK_AXI_DBG_I2C 60
+#define GATE_CLK_AXI_SRAM 61
+#define GATE_CLK_AXI_ETH0 62
+#define GATE_CLK_AXI_EMMC 63
+#define GATE_CLK_AXI_SD 64
+#define GATE_CLK_TOP_AXI0 65
+#define GATE_CLK_TOP_AXI_HSPERI 66
+
+#define GATE_CLK_TIMER1 67
+#define GATE_CLK_TIMER2 68
+#define GATE_CLK_TIMER3 69
+#define GATE_CLK_TIMER4 70
+#define GATE_CLK_TIMER5 71
+#define GATE_CLK_TIMER6 72
+#define GATE_CLK_TIMER7 73
+#define GATE_CLK_TIMER8 74
+#define GATE_CLK_100K_EMMC 75
+#define GATE_CLK_100K_SD 76
+#define GATE_CLK_GPIO_DB 77
+
+#define GATE_CLK_AXI_DDR_DIV1 78
+#define GATE_CLK_DDR01_DIV1 79
+#define GATE_CLK_DDR23_DIV1 80
+/* DPLL0 */
+#define GATE_CLK_DDR01_DIV0 81
+/* DPLL1 */
+#define GATE_CLK_DDR23_DIV0 82
+
+#define GATE_CLK_DDR01 83
+#define GATE_CLK_DDR23 84
+#define GATE_CLK_RP_CPU_NORMAL 85
+#define GATE_CLK_AXI_DDR 86
+#define GATE_CLK_RXU0 87
+#define GATE_CLK_RXU1 88
+#define GATE_CLK_RXU2 89
+#define GATE_CLK_RXU3 90
+#define GATE_CLK_RXU4 91
+#define GATE_CLK_RXU5 92
+#define GATE_CLK_RXU6 93
+#define GATE_CLK_RXU7 94
+#define GATE_CLK_RXU8 95
+#define GATE_CLK_RXU9 96
+#define GATE_CLK_RXU10 97
+#define GATE_CLK_RXU11 98
+#define GATE_CLK_RXU12 99
+#define GATE_CLK_RXU13 100
+#define GATE_CLK_RXU14 101
+#define GATE_CLK_RXU15 102
+#define GATE_CLK_RXU16 103
+#define GATE_CLK_RXU17 104
+#define GATE_CLK_RXU18 105
+#define GATE_CLK_RXU19 106
+#define GATE_CLK_RXU20 107
+#define GATE_CLK_RXU21 108
+#define GATE_CLK_RXU22 109
+#define GATE_CLK_RXU23 110
+#define GATE_CLK_RXU24 111
+#define GATE_CLK_RXU25 112
+#define GATE_CLK_RXU26 113
+#define GATE_CLK_RXU27 114
+#define GATE_CLK_RXU28 115
+#define GATE_CLK_RXU29 116
+#define GATE_CLK_RXU30 117
+#define GATE_CLK_RXU31 118
+#define GATE_CLK_MP0 119
+#define GATE_CLK_MP1 120
+#define GATE_CLK_MP2 121
+#define GATE_CLK_MP3 122
+#define GATE_CLK_MP4 123
+#define GATE_CLK_MP5 124
+#define GATE_CLK_MP6 125
+#define GATE_CLK_MP7 126
+#define GATE_CLK_MP8 127
+#define GATE_CLK_MP9 128
+#define GATE_CLK_MP10 129
+#define GATE_CLK_MP11 130
+#define GATE_CLK_MP12 131
+#define GATE_CLK_MP13 132
+#define GATE_CLK_MP14 133
+#define GATE_CLK_MP15 134
+
+/* MUX clocks */
+#define MUX_CLK_DDR01 135
+#define MUX_CLK_DDR23 136
+#define MUX_CLK_RP_CPU_NORMAL 137
+#define MUX_CLK_AXI_DDR 138
+
+/* PLL clocks */
+#define MPLL_CLK	139
+#define FPLL_CLK	140
+#define DPLL0_CLK	141
+#define DPLL1_CLK	142
+
+#endif /* __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__ */
Signature · 1 line
2.25.1
author
#4 lore raw

PATCH 2/5 dt-bindings: soc: sophgo: Add Sophgo syscon module

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add documentation to describe Sophgo System Controller Registers for SG2042.

Signed-off-by Chen Wang <[email protected]>
---
 .../soc/sophgo/sophgo,sg2042-syscon.yaml      | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +38 -0
new file mode 100644
index 000000000000..829abede4fd5
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 SoC system controller
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+description:
+  The Sophgo SG2042 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - sophgo,sg2042-syscon
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@30010000 {
+        compatible = "sophgo,sg2042-syscon", "syscon";
+        reg = <0x30010000 0x1000>;
+    };
Signature · 1 line
2.25.1
#5 lore raw

Re: [PATCH 2/5] dt-bindings: soc: sophgo: Add Sophgo syscon module

Quoted 29 lines · Chen Wang

From: Chen Wang <[email protected]>

Add documentation to describe Sophgo System Controller Registers for SG2042.

Signed-off-by Chen Wang <[email protected]>
---
 .../soc/sophgo/sophgo,sg2042-syscon.yaml      | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +12 -0
new file mode 100644
index 000000000000..829abede4fd5
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 SoC system controller
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+description:

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml line 22

Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +10 -0
+  The Sophgo SG2042 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - sophgo,sg2042-syscon
+          - const: syscon

THere's only one option here, so the oneOf should be removed. Similarly, since there's only one SoC, and it sounds like the next large sophgo system is going to be using an entirely different core provider, I think should just simplify this to a pair of "const:" entries.

Quoted 6 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +6 -0
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml line 38

Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +10 -0
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@30010000 {
+        compatible = "sophgo,sg2042-syscon", "syscon";
+        reg = <0x30010000 0x1000>;
+    };

Per my comments elsewhere, I think the clock controller should be a child of this node, rather than an unrelated node, linked by a phandle.

Cheers,
Conor.

#6 lore raw

Re: [PATCH 2/5] dt-bindings: soc: sophgo: Add Sophgo syscon module

Quoted 36 lines · Conor Dooley
Quoted 35 lines · Chen Wang

From: Chen Wang <[email protected]>

Add documentation to describe Sophgo System Controller Registers for SG2042.

Signed-off-by Chen Wang <[email protected]>
---
  .../soc/sophgo/sophgo,sg2042-syscon.yaml      | 38 +++++++++++++++++++
  1 file changed, 38 insertions(+)

create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +18 -0
new file mode 100644
index 000000000000..829abede4fd5
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 SoC system controller
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+description:
+  The Sophgo SG2042 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules.
+
+properties:
+  compatible:
+    oneOf:
Quoted 8 lines

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml line 22

Quoted 4 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +4 -0
+      - items:
+          - enum:
+              - sophgo,sg2042-syscon
+          - const: syscon

THere's only one option here, so the oneOf should be removed. Similarly, since there's only one SoC, and it sounds like the next large sophgo system is going to be using an entirely different core provider, I think should just simplify this to a pair of "const:" entries.

Yes, "oneOf" should be removed.

Regarding the "enum", I heard from Sophgo people, that they will announce a new SG2044 chip next year and it will share some modules from SG2042, including syscon, clock ...

So it is better keeping the "enum" here and we may add another "sophgo,sg2044-syscon" later.

Regarding the next large sophgo system you mentioned, yes, there is anther chip, I think you are talking about SG2380, it will use core(P670) from SiFive. Maybe we can see it in next year also.

More news, I find a report from web: https://www.hpcwire.com/2023/11/13/chinese-company-developing-64-core-risc-v-chip-with-tech-from-u-s/, FYI.

Quoted 10 lines
Quoted 10 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +10 -0
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
Quoted 8 lines

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml line 38

Quoted 6 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +6 -0
+examples:
+  - |
+    syscon@30010000 {
+        compatible = "sophgo,sg2042-syscon", "syscon";
+        reg = <0x30010000 0x1000>;
+    };

Per my comments elsewhere, I think the clock controller should be a child of this node, rather than an unrelated node, linked by a phandle.

Agree, I will correct this in next revision.

Quoted 3 lines

Cheers,
Conor.

maintainer
#7 lore raw

Re: [PATCH 2/5] dt-bindings: soc: sophgo: Add Sophgo syscon module

In reply to Conor Dooley
Quoted 37 lines · Conor Dooley
Quoted 36 lines · Chen Wang

From: Chen Wang <[email protected]>

Add documentation to describe Sophgo System Controller Registers for SG2042.

Signed-off-by Chen Wang <[email protected]>
---
 .../soc/sophgo/sophgo,sg2042-syscon.yaml      | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +19 -0
new file mode 100644
index 000000000000..829abede4fd5
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 SoC system controller
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+description:
+  The Sophgo SG2042 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
Quoted 8 lines

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml line 22

Quoted 3 lines
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file +3 -0
+          - enum:
+              - sophgo,sg2042-syscon
+          - const: syscon

THere's only one option here, so the oneOf should be removed. Similarly, since there's only one SoC, and it sounds like the next large sophgo system is going to be using an entirely different core provider, I think should just simplify this to a pair of "const:" entries.

For a simple syscon binding like this, you can just add the compatible to syscon.yaml.

Rob

author
#8 lore raw

PATCH 3/5 dt-bindings: clock: sophgo: Add SG2042 bindings

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add bindings for the clock generator on the SG2042 RISC-V SoC.

Signed-off-by Chen Wang <[email protected]>
---
 .../clock/sophgo/sophgo,sg2042-clkgen.yaml    | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml new file +48 -0
new file mode 100644
index 000000000000..e372d5dca5b9
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Clock Generator
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-clkgen
+
+  system-ctrl:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to System Register Controller syscon node.
+    description:
+      The phandle to System Register Controller syscon node.
+
+  clocks:
+    items:
+      - description: Clock Generation IC (25 MHz)
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/sophgo-sg2042-clk.h> for valid indices.
+
+required:
+  - compatible
+  - system-ctrl
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller {
+            compatible = "sophgo,sg2042-clkgen";
+            clocks = <&cgi>;
+            system-ctrl = <&sys_ctrl>;
+            #clock-cells = <1>;
+    };
Signature · 1 line
2.25.1
maintainer
#9 lore raw

Re: [PATCH 3/5] dt-bindings: clock: sophgo: Add SG2042 bindings

Quoted 28 lines · Chen Wang

From: Chen Wang <[email protected]>

Add bindings for the clock generator on the SG2042 RISC-V SoC.

Signed-off-by Chen Wang <[email protected]>
---
 .../clock/sophgo/sophgo,sg2042-clkgen.yaml    | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml new file +12 -0
new file mode 100644
index 000000000000..e372d5dca5b9
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Clock Generator
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:

Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml line 22

Quoted 10 lines
Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml new file +10 -0
+  compatible:
+    const: sophgo,sg2042-clkgen
+
+  system-ctrl:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to System Register Controller syscon node.
+    description:
+      The phandle to System Register Controller syscon node.

Forget what I just said about syscon.yaml...

You don't need a phandle here. Just make this node a child of the syscon. However, why do you need a child at all? Just add 'clocks' and '#clock-cells' to the parent directly. You don't need a child node when there's only 1 child node. Maybe there's other functions, but I have no visibility into that. IOW, define what all the functions are so we can provide better guidance.

Rob

#10 lore raw

Re: [PATCH 3/5] dt-bindings: clock: sophgo: Add SG2042 bindings

Quoted 41 lines · Rob Herring
Quoted 28 lines · Chen Wang

From: Chen Wang <[email protected]>

Add bindings for the clock generator on the SG2042 RISC-V SoC.

Signed-off-by Chen Wang <[email protected]>
---
  .../clock/sophgo/sophgo,sg2042-clkgen.yaml    | 48 +++++++++++++++++++
  1 file changed, 48 insertions(+)

create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml

Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml new file +12 -0
new file mode 100644
index 000000000000..e372d5dca5b9
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Clock Generator
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:

Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml line 22

Quoted 10 lines
Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml new file +10 -0
+  compatible:
+    const: sophgo,sg2042-clkgen
+
+  system-ctrl:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to System Register Controller syscon node.
+    description:
+      The phandle to System Register Controller syscon node.

Forget what I just said about syscon.yaml...

Quoted 2 lines

You don't need a phandle here. Just make this node a child of the syscon.

Yes, making this node a child of syscon is a better solution and then we need not a phandle here.

Quoted 5 lines

However, why do you need a child at all? Just add 'clocks' and '#clock-cells' to the parent directly. You don't need a child node when there's only 1 child node. Maybe there's other functions, but I have no visibility into that. IOW, define what all the functions are so we can provide better guidance.

The syscon is a module in SG2042 that provides multipile functions, and clock control is just one of them. I will add more other functions's nodes later under the syscon in coming patches, such as reset, pinctrl etc.

Quoted 2 lines

Rob

author
#11 lore raw

PATCH 4/5 clk: sophgo: Add SG2042 clock generator driver

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add a driver for the SOPHGO SG2042 clock generator.

Signed-off-by Chen Wang <[email protected]>
---
 MAINTAINERS                            |    8 +
 drivers/clk/Kconfig                    |    1 +
 drivers/clk/Makefile                   |    1 +
 drivers/clk/sophgo/Kconfig             |    8 +
 drivers/clk/sophgo/Makefile            |    2 +
 drivers/clk/sophgo/clk-sophgo-sg2042.c | 1259 ++++++++++++++++++++++++
 drivers/clk/sophgo/clk-sophgo-sg2042.h |  226 +++++
 7 files changed, 1505 insertions(+)
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
MAINTAINERS +8 -0
index 97f51d5ec1cf..0a78a407d914 100644
@@ -20269,6 +20269,14 @@ S:	Maintained
 F:	arch/riscv/boot/dts/sophgo/
 F:	Documentation/devicetree/bindings/riscv/sophgo.yaml
 
+SOPHGO SG2042 CLOCK DRIVER
+M:	Chen Wang <[email protected]>
+S:	Maintained
+F:	Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
+F:	drivers/clk/sophgo/clk-sophgo-sg2042.c
+F:	drivers/clk/sophgo/clk-sophgo-sg2042.h
+F:	include/dt-bindings/clock/sophgo-sg2042-clk.h
+
 SOUND
 M:	Jaroslav Kysela <[email protected]>
 M:	Takashi Iwai <[email protected]>
drivers/clk/Kconfig +1 -0
index c30d0d396f7a..514343934fda 100644
@@ -499,6 +499,7 @@ source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
 source "drivers/clk/sifive/Kconfig"
 source "drivers/clk/socfpga/Kconfig"
+source "drivers/clk/sophgo/Kconfig"
 source "drivers/clk/sprd/Kconfig"
 source "drivers/clk/starfive/Kconfig"
 source "drivers/clk/sunxi/Kconfig"
drivers/clk/Makefile +1 -0
index ed71f2e0ee36..aa5d2cf0b6a6 100644
@@ -119,6 +119,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_CLK_SIFIVE)		+= sifive/
 obj-y					+= socfpga/
+obj-$(CONFIG_ARCH_SOPHGO)		+= sophgo/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/
 obj-y					+= sprd/
 obj-$(CONFIG_ARCH_STI)			+= st/
drivers/clk/sophgo/Kconfig new file +8 -0
new file mode 100644
index 000000000000..8a054dc2c051
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_SOPHGO_SG2042
+	bool "Sophgo SG2042 clock support"
+	depends on ARCH_SOPHGO
+	default ARCH_SOPHGO
+	help
+	  Say yes here to support the clock controller on the Sophgo SG2042 SoC.
drivers/clk/sophgo/Makefile new file +2 -0
new file mode 100644
index 000000000000..13834cce260c
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_SOPHGO_SG2042)	+= clk-sophgo-sg2042.o
drivers/clk/sophgo/clk-sophgo-sg2042.c new file +1259 -0

1,259 lines not on this page · raw message

drivers/clk/sophgo/clk-sophgo-sg2042.h new file +226 -0

226 lines not on this page · raw message

Signature · 1 line
2.25.1
build bot
#12 lore raw

Re: [PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver

kernel test robot noticed the following build warnings:

Hi Chen,

kernel test robot noticed the following build warnings:

[auto build test WARNING on b85ea95d086471afb4ad062012a4d73cd328fa86]

url:    https://github.com/intel-lab-lkp/linux/commits/Chen-Wang/dt-bindings-clock-sophgo-Add-SG2042-clock-definitions/20231113-212401
base:   b85ea95d086471afb4ad062012a4d73cd328fa86
patch link:    https://lore.kernel.org/r/1000e8d546514973364478271564356352a46ed5.1699879741.git.unicorn_wang%40outlook.com
patch subject: [PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver
config: riscv-rv32_defconfig (https://download.01.org/0day-ci/archive/20231115/[email protected]/config)
compiler: riscv32-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231115/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

drivers/clk/sophgo/clk-sophgo-sg2042.c: In function '__sg2042_get_pll_ctl_setting':

>> drivers/clk/sophgo/clk-sophgo-sg2042.c:25:28: warning: integer overflow in expression of type 'long int' results in '-1094967296' [-Woverflow]
      25 | #define PLL_FREQ_MAX (3200 * MHZ)
         |                            ^
   drivers/clk/sophgo/clk-sophgo-sg2042.c:217:65: note: in expansion of macro 'PLL_FREQ_MAX'
     217 |                         if (foutvco < PLL_FREQ_MIN || foutvco > PLL_FREQ_MAX
         |                                                                 ^~~~~~~~~~~~

vim +25 drivers/clk/sophgo/clk-sophgo-sg2042.c

    23	
    24	#define PLL_FREQ_MIN (16 * MHZ)
  > 25	#define PLL_FREQ_MAX (3200 * MHZ)
    26
Signature · 2 lines
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
build bot
#13 lore raw

Re: [PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver

In reply to Chen Wang
kernel test robot noticed the following build warnings:

Hi Chen,

kernel test robot noticed the following build warnings:

[auto build test WARNING on b85ea95d086471afb4ad062012a4d73cd328fa86]

url:    https://github.com/intel-lab-lkp/linux/commits/Chen-Wang/dt-bindings-clock-sophgo-Add-SG2042-clock-definitions/20231113-212401
base:   b85ea95d086471afb4ad062012a4d73cd328fa86
patch link:    https://lore.kernel.org/r/1000e8d546514973364478271564356352a46ed5.1699879741.git.unicorn_wang%40outlook.com
patch subject: [PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver
config: riscv-rv32_defconfig (https://download.01.org/0day-ci/archive/20231119/[email protected]/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231119/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

>> drivers/clk/sophgo/clk-sophgo-sg2042.c:217:44: warning: overflow in expression; result is -1094967296 with type 'long' [-Winteger-overflow]
     217 |                         if (foutvco < PLL_FREQ_MIN || foutvco > PLL_FREQ_MAX
         |                                                                 ^
   drivers/clk/sophgo/clk-sophgo-sg2042.c:25:28: note: expanded from macro 'PLL_FREQ_MAX'
      25 | #define PLL_FREQ_MAX (3200 * MHZ)
         |                            ^

1 warning generated.

vim +/long +217 drivers/clk/sophgo/clk-sophgo-sg2042.c

201
202 static int __sg2042_get_pll_ctl_setting(
203 struct sg2042_pll_ctrl *best,
204 unsigned long req_rate,
205 unsigned long parent_rate)
206 {
207 int ret;
208 unsigned int fbdiv, refdiv, fref, postdiv1, postdiv2;
209 unsigned long tmp = 0, foutvco;
210
211 fref = parent_rate;
212
213 for (refdiv = REFDIV_MIN; refdiv < REFDIV_MAX + 1; refdiv++) {
214 for (fbdiv = FBDIV_MIN; fbdiv < FBDIV_MAX + 1; fbdiv++) {
215 foutvco = fref * fbdiv / refdiv;
216 /* check fpostdiv pfd */

 > 217				if (foutvco < PLL_FREQ_MIN || foutvco > PLL_FREQ_MAX

218 || (fref / refdiv) < 10)
219 continue;
220
221 ret = __sg2042_pll_get_postdiv_1_2(req_rate, fref, fbdiv,
222 refdiv, &postdiv1, &postdiv2);
223 if (ret)
224 continue;
225
226 tmp = foutvco / (postdiv1 * postdiv2);
227 if (abs_diff(tmp, req_rate) < abs_diff(best->freq, req_rate)) {
228 best->freq = tmp;
229 best->refdiv = refdiv;
230 best->fbdiv = fbdiv;
231 best->postdiv1 = postdiv1;
232 best->postdiv2 = postdiv2;
233 if (tmp == req_rate)
234 return 0;
235 }
236 continue;
237 }
238 }
239
240 return 0;
241 }
242

Signature · 2 lines
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
author
#14 lore raw

PATCH 5/5 riscv: dts: add clock generator for Sophgo SG2042 SoC

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add clock generator node to device tree for SG2042, and enable clock for uart0.

Signed-off-by Chen Wang <[email protected]>
---
 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
 2 files changed, 86 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +76 -0
new file mode 100644
index 000000000000..66d2723fab35
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+	cgi: oscillator {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		clock-output-names = "cgi";
+		#clock-cells = <0>;
+	};
+
+	clkgen: clock-controller {
+		compatible = "sophgo,sg2042-clkgen";
+		#clock-cells = <1>;
+		system-ctrl = <&sys_ctrl>;
+		clocks = <&cgi>;
+		assigned-clocks = \
+			<&clkgen DIV_CLK_FPLL_RP_CPU_NORMAL_1>,
+			<&clkgen DIV_CLK_FPLL_50M_A53>,
+			<&clkgen DIV_CLK_FPLL_TOP_RP_CMN_DIV2>,
+			<&clkgen DIV_CLK_FPLL_UART_500M>,
+			<&clkgen DIV_CLK_FPLL_AHB_LPC>,
+			<&clkgen DIV_CLK_FPLL_EFUSE>,
+			<&clkgen DIV_CLK_FPLL_TX_ETH0>,
+			<&clkgen DIV_CLK_FPLL_PTP_REF_I_ETH0>,
+			<&clkgen DIV_CLK_FPLL_REF_ETH0>,
+			<&clkgen DIV_CLK_FPLL_EMMC>,
+			<&clkgen DIV_CLK_FPLL_SD>,
+			<&clkgen DIV_CLK_FPLL_TOP_AXI0>,
+			<&clkgen DIV_CLK_FPLL_TOP_AXI_HSPERI>,
+			<&clkgen DIV_CLK_FPLL_AXI_DDR_1>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER1>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER2>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER3>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER4>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER5>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER6>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER7>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER8>,
+			<&clkgen DIV_CLK_FPLL_100K_EMMC>,
+			<&clkgen DIV_CLK_FPLL_100K_SD>,
+			<&clkgen DIV_CLK_FPLL_GPIO_DB>,
+			<&clkgen DIV_CLK_MPLL_RP_CPU_NORMAL_0>,
+			<&clkgen DIV_CLK_MPLL_AXI_DDR_0>;
+		assigned-clock-rates = \
+			<2000000000>,
+			<50000000>,
+			<1000000000>,
+			<500000000>,
+			<200000000>,
+			<25000000>,
+			<125000000>,
+			<50000000>,
+			<25000000>,
+			<100000000>,
+			<100000000>,
+			<100000000>,
+			<250000000>,
+			<1000000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<100000>,
+			<100000>,
+			<100000>,
+			<2000000000>,
+			<1000000000>;
+	};
+};
arch/riscv/boot/dts/sophgo/sg2042.dtsi +10 -0
index 93256540d078..de79c0cdb4c1 100644
@@ -5,8 +5,10 @@
 
 /dts-v1/;
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo-sg2042-clk.h>
 
 #include "sg2042-cpus.dtsi"
+#include "sg2042-clock.dtsi"
 
 / {
 	compatible = "sophgo,sg2042";

@@ -311,12 +313,20 @@ intc: interrupt-controller@7090000000 {
 			riscv,ndev = <224>;
 		};
 
+		sys_ctrl: syscon@7030010000 {
+			compatible = "sophgo,sg2042-syscon", "syscon";
+			reg = <0x70 0x30010000 0x0 0x8000>;
+		};
+
 		uart0: serial@7040000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
 			interrupt-parent = <&intc>;
 			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
 			clock-frequency = <500000000>;
+			clocks = <&clkgen GATE_CLK_UART_500M>,
+				 <&clkgen GATE_CLK_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
Signature · 1 line
2.25.1
#15 lore raw

Re: [PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC

Quoted 8 lines · Chen Wang

From: Chen Wang <[email protected]>

Add clock generator node to device tree for SG2042, and enable clock for uart0.

Signed-off-by Chen Wang <[email protected]>
---
 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++

There's no need to create an entirely new file for this.

Quoted 12 lines
 arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
 2 files changed, 86 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +2 -0
new file mode 100644
index 000000000000..66d2723fab35
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi line 12

Quoted 10 lines
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +10 -0
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+	cgi: oscillator {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		clock-output-names = "cgi";
+		#clock-cells = <0>;
+	};

What actually is this oscillator?
Is it provided by another clock controller on the SoC, or is it provided by an oscillator on the board?

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi line 17

Quoted 5 lines
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +5 -0
+
+	clkgen: clock-controller {
+		compatible = "sophgo,sg2042-clkgen";
+		#clock-cells = <1>;
+		system-ctrl = <&sys_ctrl>;

Why is this node not a child of the system controller?

Cheers,
Conor.

#16 lore raw

Re: [PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC

Quoted 10 lines · Conor Dooley
Quoted 8 lines · Chen Wang

From: Chen Wang <[email protected]>

Add clock generator node to device tree for SG2042, and enable clock for uart0.

Signed-off-by Chen Wang <[email protected]>
---
  arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++

There's no need to create an entirely new file for this.

Agree, I will merge this into sg2042.dtsi in next revision.

Quoted 18 lines
Quoted 18 lines
  arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
  2 files changed, 86 insertions(+)

create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +7 -0
new file mode 100644
index 000000000000..66d2723fab35
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+	cgi: oscillator {
Quoted 8 lines

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi line 12

Quoted 5 lines
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +5 -0
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		clock-output-names = "cgi";
+		#clock-cells = <0>;
+	};

What actually is this oscillator?
Is it provided by another clock controller on the SoC, or is it provided by an oscillator on the board?

This oscillator is an individual ic chip outside the SoC on the board, that's why I list it outside soc node.

Actually the "cgi" is abbrevation for "Clock Generation IC chip".

Quoted 6 lines

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi line 17

Quoted 5 lines
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +5 -0
+
+	clkgen: clock-controller {
+		compatible = "sophgo,sg2042-clkgen";
+		#clock-cells = <1>;
+		system-ctrl = <&sys_ctrl>;

Why is this node not a child of the system controller?

I will move this node to child of syscon in next revision, thanks for your reminder.

Quoted 3 lines

Cheers,
Conor.

#17 lore raw

Re: [PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC

Quoted 40 lines · Chen Wang
Quoted 10 lines · Conor Dooley
Quoted 8 lines · Chen Wang

From: Chen Wang <[email protected]>

Add clock generator node to device tree for SG2042, and enable clock for uart0.

Signed-off-by Chen Wang <[email protected]>

---
  arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++

There's no need to create an entirely new file for this.

Agree, I will merge this into sg2042.dtsi in next revision.

Quoted 19 lines
Quoted 19 lines

  arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++

  2 files changed, 86 insertions(+)

  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +7 -0
new file mode 100644
index 000000000000..66d2723fab35
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+    cgi: oscillator {
Quoted 8 lines

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi line 12

Quoted 5 lines
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +5 -0
+        compatible = "fixed-clock";
+        clock-frequency = <25000000>;
+        clock-output-names = "cgi";
+        #clock-cells = <0>;
+    };

What actually is this oscillator?
Is it provided by another clock controller on the SoC, or is it provided by an oscillator on the board?

Quoted 4 lines

This oscillator is an individual ic chip outside the SoC on the board, that's why I list it outside soc node.

Actually the "cgi" is abbrevation for "Clock Generation IC chip".

Since the oscillator is outside the SoC, this node (or at least its clock-frequency property) belongs in the board devicetree, not the SoC .dtsi. See [1].

Regards,
Samuel

[1]:
https://lore.kernel.org/linux-riscv/[email protected]/

#18 lore raw

Re: [PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC

Quoted 47 lines · Samuel Holland
Quoted 38 lines · Chen Wang
Quoted 10 lines · Conor Dooley
Quoted 8 lines · Chen Wang

From: Chen Wang <[email protected]>

Add clock generator node to device tree for SG2042, and enable clock for uart0.

Signed-off-by Chen Wang <[email protected]>
---
   arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++

There's no need to create an entirely new file for this.

Agree, I will merge this into sg2042.dtsi in next revision.

Quoted 18 lines
Quoted 18 lines
   arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
   2 files changed, 86 insertions(+)

  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +7 -0
new file mode 100644
index 000000000000..66d2723fab35
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+    cgi: oscillator {
Quoted 8 lines

arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi line 12

Quoted 5 lines
arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi new file +5 -0
+        compatible = "fixed-clock";
+        clock-frequency = <25000000>;
+        clock-output-names = "cgi";
+        #clock-cells = <0>;
+    };

What actually is this oscillator?
Is it provided by another clock controller on the SoC, or is it provided by an oscillator on the board?

Quoted 4 lines

This oscillator is an individual ic chip outside the SoC on the board, that's why I list it outside soc node.

Actually the "cgi" is abbrevation for "Clock Generation IC chip".

Since the oscillator is outside the SoC, this node (or at least its clock-frequency property) belongs in the board devicetree, not the SoC .dtsi. See [1].

Quoted 5 lines

Regards,
Samuel

[1]:
https://lore.kernel.org/linux-riscv/[email protected]/

Thank you Samuel, I have learned this and will correct this in next revision.