Initial support for Cadence MHDP(HDMI/DP) for i.MX8MQ

Add bindings for i.MX8MQ MHDP HDMI.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +13 -0

new file mode 100644
index 000000000000..b2a769d4cb82
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence MHDP HDMI bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP TX HDMI interface.

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml new file +5 -0

+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.

Quoted 1 line · Sandor Yu

Add bindings for i.MX8MQ MHDP HDMI.

Typo in subject - bindings.

Also in the subject - drop redundant second word "bindings".

Quoted 6 lines

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml

Add bindings for i.MX8MQ MHDP DisplayPort.

Signed-off-by Sandor Yu <[email protected]>

---
 .../display/bridge/cdns,mhdp-imx8mq-dp.yaml   | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +43 -0

new file mode 100644
index 000000000000..06ed881247ea
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-dp.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence MHDP Displayport bridge
+
+maintainers:
+  - Sandor Yu <[email protected]>
+
+description:
+  The Cadence MHDP Displayport TX interface.
+
+properties:
+  compatible:
+    enum:
+      - cdns,mhdp-imx8mq-dp
+
+  reg:
+    items:
+      - description:
+          Memory mapped base address and length of mhdptx apb registers.
+
+  phys:
+    description:
+      phandle to the Displayport PHY.
+
+  phy-names:
+    items:
+      - const: dpphy
+
+  interrupts:
+    items:
+      - description: Hotplug detect interrupter for cable plugin event.
+      - description: Hotplug detect interrupter for cable plugout event.
+
+  interrupt-names:
+    items:
+      - const: plug_in
+      - const: plug_out
+
+  port:

Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml new file +4 -0

+        compatible = "cdns,mhdp-imx8mq-dp";
+        reg = <0x32c00000 0x100000>;
+        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

Add a new DRM HDMI bridge driver for Candence MHDP used in i.MX8MQ SOC. MHDP IP could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SOC, the HDMI FW was loaded and activated by SOC ROM code. Bootload binary included HDMI FW was required for the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/gpu/drm/bridge/cadence/Kconfig        |   12 +
 .../gpu/drm/bridge/cadence/cdns-hdmi-core.c   | 1038 +++++++++++++++++
 2 files changed, 1050 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Kconfig index e79ae1af3765..377452d09992 100644

drivers/gpu/drm/bridge/cadence/Kconfig +12 -0

@@ -26,6 +26,18 @@ config DRM_CDNS_MHDP8546_J721E
 	  clock and data muxes.
 endif
 
+config DRM_CDNS_HDMI
+	tristate "Cadence HDMI DRM driver"
+	select DRM_KMS_HELPER
+	select DRM_PANEL_BRIDGE
+	select DRM_DISPLAY_HELPER
+	select DRM_CDNS_AUDIO
+	depends on OF
+	help
+	  Support Cadence MHDP HDMI driver.
+	  Cadence MHDP Controller support one or more protocols,
+	  HDMI firmware is required for this driver.
+
 config DRM_CDNS_DP
 	tristate "Cadence DP DRM driver"
 	select DRM_KMS_HELPER

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file mode 100644 index 000000000000..b392aac015bd

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +23 -0

@@ -0,0 +1,1038 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence High-Definition Multimedia Interface (HDMI) driver
+ *
+ * Copyright (C) 2019-2022 NXP Semiconductor, Inc.
+ *
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/hdmi.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-hdmi.h>
+
+#include <drm/bridge/cdns-mhdp-mailbox.h>
+#include <drm/display/drm_hdmi_helper.h>
+#include <drm/display/drm_scdc_helper.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h>

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +25 -0

+		if (ret)
+			continue;
+
+		ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+		if (ret)
+			continue;
+
+		ret = cdns_mhdp_mailbox_recv_data(mhdp, edid, length);
+		if (ret)
+			continue;
+
+		if ((reg[3] << 8 | reg[4]) == length)
+			break;
+	}
+
+	mutex_unlock(&mhdp->mbox_mutex);
+
+	if (ret)
+		DRM_ERROR("get block[%d] edid failed: %d\n", block, ret);
+	return ret;
+}
+
+int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8 *data)
+{
+	u8 msg[4], reg[6];

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +22 -0

+	if (ret)
+		goto err_scdc_read;
+
+	ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+	if (ret)
+		goto err_scdc_read;
+
+	*data = reg[5];
+
+err_scdc_read:
+
+	mutex_unlock(&mhdp->mbox_mutex);
+
+	if (ret)
+		DRM_ERROR("scdc read failed: %d\n", ret);
+	return ret;
+}
+
+int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8 value)
+{
+	u8 msg[5], reg[5];
+	int ret;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +19 -0

+	if (ret)
+		goto err_scdc_write;
+
+	ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+	if (ret)
+		goto err_scdc_write;
+
+	if (reg[0] != 0)
+		ret = -EINVAL;
+
+err_scdc_write:
+
+	mutex_unlock(&mhdp->mbox_mutex);
+
+	if (ret)
+		DRM_ERROR("scdc write failed: %d\n", ret);
+	return ret;
+}
+

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +30 -0

+	if (ret < 0)
+		return ret;
+
+	/* open CARS */
+	ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF);
+	if (ret < 0)
+		return ret;
+	ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF);
+	if (ret < 0)
+		return ret;
+	ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF);
+	if (ret < 0)
+		return ret;
+	ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF);
+	if (ret < 0)
+		return ret;
+	ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF);
+	if (ret < 0)
+		return ret;
+	ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF);
+	if (ret < 0)
+		return ret;
+	ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3);
+	if (ret < 0)
+		return ret;
+
+	reg0 = reg1 = 0x7c1f;
+	if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) {
+		reg0 = 0;
+		reg1 = 0xFFFFF;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +8 -0

+{
+	int ret;
+	u32 val;
+	u32 vsync_lines = mode->vsync_end - mode->vsync_start;
+	u32 eof_lines = mode->vsync_start - mode->vdisplay;
+	u32 sof_lines = mode->vtotal - mode->vsync_end;
+	u32 hblank = mode->htotal - mode->hdisplay;
+	u32 hactive = mode->hdisplay;

hback); + if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +87 -0

+		return ret;
+
+	ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL, v_h_polarity);
+	if (ret < 0)
+		return ret;
+
+	/* Reset Data Enable */
+	cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER, &val);
+	val &= ~F_DATA_EN(1);
+	ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+	if (ret < 0)
+		return ret;
+
+	/* Set bpc */
+	val &= ~F_VIF_DATA_WIDTH(3);
+	switch (video_info->bpc) {
+	case 10:
+		val |= F_VIF_DATA_WIDTH(1);
+		break;
+	case 12:
+		val |= F_VIF_DATA_WIDTH(2);
+		break;
+	case 16:
+		val |= F_VIF_DATA_WIDTH(3);
+		break;
+	case 8:
+	default:
+		val |= F_VIF_DATA_WIDTH(0);
+		break;
+	}
+
+	/* select color encoding */
+	val &= ~F_HDMI_ENCODING(3);
+	switch (video_info->color_fmt) {
+	case DRM_COLOR_FORMAT_YCBCR444:
+		val |= F_HDMI_ENCODING(2);
+		break;
+	case DRM_COLOR_FORMAT_YCBCR422:
+		val |= F_HDMI_ENCODING(1);
+		break;
+	case DRM_COLOR_FORMAT_YCBCR420:
+		val |= F_HDMI_ENCODING(3);
+		break;
+	case DRM_COLOR_FORMAT_RGB444:
+	default:
+		val |= F_HDMI_ENCODING(0);
+		break;
+	}
+
+	ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+	if (ret < 0)
+		return ret;
+
+	/* set data enable */
+	val |= F_DATA_EN(1);
+	ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+
+	return ret;
+}
+
+int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp)
+{
+	u32 val;
+
+	cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER, &val);
+	val &= ~F_GCP_EN(1);
+
+	return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+}
+
+int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp)
+{
+	u32 val;
+
+	cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER, &val);
+	val |= F_GCP_EN(1);
+
+	return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+}
+
+static void hdmi_sink_config(struct cdns_mhdp_device *mhdp)
+{
+	struct drm_scdc *scdc = &mhdp->curr_conn->display_info.hdmi.scdc;
+	u8 buff = 0;
+
+	/* Default work in HDMI1.4 */
+	mhdp->hdmi.hdmi_type = MODE_HDMI_1_4;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +25 -0

+		 * be indicated in the HF-VSDB LTE_340Mcsc_scramble bit
+		 */
+		buff = SCDC_SCRAMBLING_ENABLE;
+		mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
+	}
+
+	/* TMDS config */
+	cdns_hdmi_scdc_write(mhdp, SCDC_TMDS_CONFIG, buff);
+}
+
+static void hdmi_lanes_config(struct cdns_mhdp_device *mhdp)
+{
+	u32 lane_mapping = mhdp->plat_data->lane_mapping;
+	/* Line swapping */
+	cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | lane_mapping);
+}
+
+int cdns_mhdp_hdmi_read_hpd(struct cdns_mhdp_device *mhdp)
+{
+	u8 status;
+	int ret;
+
+	mutex_lock(&mhdp->mbox_mutex);
+
+	ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX,

HDMI_TX_HPD_STATUS, + 0, NULL);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +20 -0

+	if (ret)
+		goto err_get_hpd;
+
+	ret = cdns_mhdp_mailbox_recv_data(mhdp, &status, sizeof(status));
+	if (ret)
+		goto err_get_hpd;
+
+	mutex_unlock(&mhdp->mbox_mutex);
+	return status;
+
+err_get_hpd:
+	mutex_unlock(&mhdp->mbox_mutex);
+	DRM_ERROR("read hpd  failed: %d\n", ret);
+	return ret;
+}
+
+static int hdmi_avi_info_set(struct cdns_mhdp_device *mhdp,
+			     struct drm_display_mode *mode)
+{
+	struct hdmi_avi_infoframe frame;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +37 -0

+
+	switch (format) {
+	case DRM_COLOR_FORMAT_YCBCR444:
+		frame.colorspace = HDMI_COLORSPACE_YUV444;
+		break;
+	case DRM_COLOR_FORMAT_YCBCR422:
+		frame.colorspace = HDMI_COLORSPACE_YUV422;
+		break;
+	case DRM_COLOR_FORMAT_YCBCR420:
+		frame.colorspace = HDMI_COLORSPACE_YUV420;
+		break;
+	default:
+		frame.colorspace = HDMI_COLORSPACE_RGB;
+		break;
+	}
+
+	drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state);
+
+	adj_mode = &mhdp->bridge.encoder->crtc->state->adjusted_mode;
+
+	qr = drm_default_rgb_quant_range(adj_mode);
+
+	drm_hdmi_avi_infoframe_quant_range(&frame, mhdp->curr_conn,
+					   adj_mode, qr);
+
+	ret = hdmi_avi_infoframe_check(&frame);
+	if (WARN_ON(ret))
+		return -EINVAL;
+
+	ret = hdmi_avi_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
+	if (ret < 0) {
+		DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
+		return -1;
+	}
+
+	buf[0] = 0;
+	cdns_mhdp_infoframe_set(mhdp, 0, sizeof(buf), buf,

HDMI_INFOFRAME_TYPE_AVI); +

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +12 -0

+	return 0;
+}
+
+static void hdmi_vendor_info_set(struct cdns_mhdp_device *mhdp,
+				struct drm_display_mode *mode)
+{
+	struct hdmi_vendor_infoframe frame;
+	u8 buf[32];
+	int ret;
+
+	/* Initialise vendor frame from DRM mode */
+	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mhdp-

curr_conn,
mode); + if (ret < 0) {

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +12 -0

+		DRM_INFO("No vendor infoframe\n");
+		return;
+	}
+
+	ret = hdmi_vendor_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
+	if (ret < 0) {
+		DRM_WARN("Unable to pack vendor infoframe: %d\n", ret);
+		return;
+	}
+
+	buf[0] = 0;
+	cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf,

HDMI_INFOFRAME_TYPE_VENDOR); +}

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +27 -0

+
+static void hdmi_drm_info_set(struct cdns_mhdp_device *mhdp)
+{
+	struct drm_connector_state *conn_state;
+	struct hdmi_drm_infoframe frame;
+	u8 buf[32];
+	int ret;
+
+	conn_state = mhdp->curr_conn->state;
+
+	if (!conn_state->hdr_output_metadata)
+		return;
+
+	ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
+	if (ret < 0) {
+		DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
+		return;
+	}
+
+	ret = hdmi_drm_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
+	if (ret < 0) {
+		DRM_DEBUG_KMS("couldn't pack HDR infoframe\n");
+		return;
+	}
+
+	buf[0] = 0;
+	cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf,

HDMI_INFOFRAME_TYPE_DRM); +}

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +39 -0

+
+static int hdmi_phy_colorspace(int color_fmt)
+{
+	int color_space;
+
+	switch (color_fmt) {
+	case DRM_COLOR_FORMAT_YCBCR444:
+		color_space = HDMI_PHY_COLORSPACE_YUV444;
+		break;
+	case DRM_COLOR_FORMAT_YCBCR422:
+		color_space = HDMI_PHY_COLORSPACE_YUV422;
+		break;
+	case DRM_COLOR_FORMAT_YCBCR420:
+		color_space = HDMI_PHY_COLORSPACE_YUV420;
+		break;
+	case DRM_COLOR_FORMAT_RGB444:
+	default:
+		color_space = HDMI_PHY_COLORSPACE_RGB;
+		break;
+	}
+
+	return color_space;
+}
+
+void cdns_hdmi_mode_set(struct cdns_mhdp_device *mhdp)
+{
+	struct drm_display_mode *mode = &mhdp->mode;
+	union phy_configure_opts phy_cfg;
+	int ret;
+
+	/* video mode check */
+	if (mode->clock == 0 || mode->hdisplay == 0 ||  mode->vdisplay == 0)
+		return;
+
+	hdmi_lanes_config(mhdp);
+
+	phy_cfg.hdmi.pixel_clk_rate = mode->clock;
+	phy_cfg.hdmi.bpc = mhdp->video_info.bpc;
+	phy_cfg.hdmi.color_space =

hdmi_phy_colorspace(mhdp->video_info.color_fmt); + ret =
phy_configure(mhdp->phy, &phy_cfg);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +9 -0

+	if (ret) {
+		dev_err(mhdp->dev, "%s: phy_configure() failed: %d\n",
+			__func__, ret);
+		return;
+	}
+
+	hdmi_sink_config(mhdp);
+
+	ret = cdns_hdmi_ctrl_init(mhdp, mhdp->hdmi.hdmi_type,

mhdp->hdmi.char_rate); + if (ret < 0) {

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +14 -0

+		DRM_ERROR("%s, ret = %d\n", __func__, ret);
+		return;
+	}
+
+	/* Config GCP */
+	if (mhdp->video_info.bpc == 8)
+		cdns_hdmi_disable_gcp(mhdp);
+	else
+		cdns_hdmi_enable_gcp(mhdp);
+
+	ret = hdmi_avi_info_set(mhdp, mode);
+	if (ret < 0) {
+		DRM_ERROR("%s ret = %d\n", __func__, ret);
+		return;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +20 -0

+		return;
+	}
+}
+static enum drm_connector_status
+cdns_hdmi_detect(struct cdns_mhdp_device *mhdp)
+{
+	u8 hpd = 0xf;
+
+	hpd = cdns_mhdp_hdmi_read_hpd(mhdp);
+	if (hpd == 1)
+		return connector_status_connected;
+	else if (hpd == 0)
+		return connector_status_disconnected;
+
+	DRM_INFO("Unknown cable status, hdp=%u\n", hpd);
+	return connector_status_unknown;
+}
+
+static enum drm_connector_status
+cdns_hdmi_bridge_detect(struct drm_bridge *bridge)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +32 -0

+	int num_modes = 0;
+	struct edid *edid;
+
+	edid = drm_do_get_edid(connector,
+				   cdns_hdmi_get_edid_block, mhdp);
+	if (edid) {
+		dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n",
+			 edid->header[0], edid->header[1],
+			 edid->header[2], edid->header[3],
+			 edid->header[4], edid->header[5],
+			 edid->header[6], edid->header[7]);
+		drm_connector_update_edid_property(connector, edid);
+		num_modes = drm_add_edid_modes(connector, edid);
+		kfree(edid);
+	}
+
+	if (num_modes == 0)
+		DRM_ERROR("Invalid edid\n");
+	return num_modes;
+}
+
+static bool blob_equal(const struct drm_property_blob *a,
+		       const struct drm_property_blob *b)
+{
+	if (a && b)
+		return a->length == b->length &&
+			!memcmp(a->data, b->data, a->length);
+
+	return !a == !b;
+}
+
+static int cdns_hdmi_connector_atomic_check(struct drm_connector

*connector, + struct

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +19 -0

+{
+	struct drm_connector_state *new_con_state =
+		drm_atomic_get_new_connector_state(state, connector);
+	struct drm_connector_state *old_con_state =
+		drm_atomic_get_old_connector_state(state, connector);
+	struct drm_crtc *crtc = new_con_state->crtc;
+	struct drm_crtc_state *new_crtc_state;
+
+	if (!blob_equal(new_con_state->hdr_output_metadata,
+			old_con_state->hdr_output_metadata) ||
+	    new_con_state->colorspace != old_con_state->colorspace) {
+		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
+		if (IS_ERR(new_crtc_state))
+			return PTR_ERR(new_crtc_state);
+
+		new_crtc_state->mode_changed =
+			!new_con_state->hdr_output_metadata ||
+			!old_con_state->hdr_output_metadata ||
+			new_con_state->colorspace != old_con_state-

colorspace;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_connector_helper_funcs

cdns_hdmi_connector_helper_funcs = { + .get_modes =
cdns_hdmi_connector_get_modes,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +6 -0

+	.atomic_check = cdns_hdmi_connector_atomic_check,
+};
+
+static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge,
+				 enum drm_bridge_attach_flags flags)
+{

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+				   DRM_MODE_CONNECTOR_HDMIA);
+
+		drm_object_attach_property(&connector->base,
+					   config-

hdr_output_metadata_property, 0);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+
+		if (!drm_mode_create_hdmi_colorspace_property(connector))
+			drm_object_attach_property(&connector->base,
+						connector-

colorspace_property, 0);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +32 -0

+
+		drm_connector_attach_encoder(connector, encoder);
+	}
+
+	return 0;
+}
+
+static enum drm_mode_status
+cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
+				const struct drm_display_info *info,
+				const struct drm_display_mode *mode)
+{
+	struct cdns_mhdp_device *mhdp = bridge->driver_private;
+	enum drm_mode_status mode_status = MODE_OK;
+	union phy_configure_opts phy_cfg;
+	int ret;
+
+	/* We don't support double-clocked and Interlaced modes */
+	if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
+			mode->flags & DRM_MODE_FLAG_INTERLACE)
+		return MODE_BAD;
+
+	/* MAX support pixel clock rate 594MHz */
+	if (mode->clock > 594000)
+		return MODE_CLOCK_HIGH;
+
+	/* 4096x2160 is not supported */
+	if (mode->hdisplay > 3840 || mode->vdisplay > 2160)
+		return MODE_BAD_HVALUE;
+
+	/* Check modes supported by PHY */
+	phy_cfg.hdmi.pixel_clk_rate = mode->clock;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +15 -0

+	if (WARN_ON(!connector))
+		return;
+
+	mhdp->curr_conn = connector;
+
+	conn_state = drm_atomic_get_new_connector_state(state, connector);
+	if (WARN_ON(!conn_state))
+		return;
+
+	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
+	if (WARN_ON(!crtc_state))
+		return;
+
+	mode = &crtc_state->adjusted_mode;
+	DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay, mode-

clock);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +17 -0

+	memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
+
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	mutex_lock(&mhdp->lock);
+	cdns_hdmi_mode_set(mhdp);
+	mutex_unlock(&mhdp->lock);
+}
+
+static const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = {
+	.attach = cdns_hdmi_bridge_attach,
+	.detect = cdns_hdmi_bridge_detect,
+	.get_edid = cdns_hdmi_bridge_get_edid,
+	.mode_valid = cdns_hdmi_bridge_mode_valid,
+	.mode_fixup = cdns_hdmi_bridge_mode_fixup,
+	.atomic_enable = cdns_hdmi_bridge_atomic_enable,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +40 -0

+	enum drm_connector_status status = cdns_hdmi_detect(mhdp);
+
+	drm_bridge_hpd_notify(&mhdp->bridge, status);
+
+	if (status == connector_status_connected) {
+		DRM_INFO("HDMI Cable Plug In\n");
+		enable_irq(mhdp->irq[IRQ_OUT]);
+	} else if (status == connector_status_disconnected) {
+		/* Cable Disconnedted  */
+		DRM_INFO("HDMI Cable Plug Out\n");
+		enable_irq(mhdp->irq[IRQ_IN]);
+	}
+}
+
+static irqreturn_t cdns_hdmi_irq_thread(int irq, void *data)
+{
+	struct cdns_mhdp_device *mhdp = data;
+
+	disable_irq_nosync(irq);
+
+	mod_delayed_work(system_wq, &mhdp->hotplug_work,
+			msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
+
+	return IRQ_HANDLED;
+}
+
+static int cdns_mhdp_imx_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cdns_mhdp_device *mhdp;
+	struct platform_device_info pdevinfo;
+	struct resource *res;
+	u32 reg;
+	int ret;
+
+	mhdp = devm_kzalloc(dev, sizeof(*mhdp), GFP_KERNEL);
+	if (!mhdp)
+		return -ENOMEM;
+
+	mutex_init(&mhdp->lock);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +18 -0

+		return ret;
+	}
+
+	ret = phy_init(mhdp->phy);
+	if (ret) {
+		dev_err(mhdp->dev, "Failed to initialize PHY: %d\n", ret);
+		return -ENODEV;
+	}
+
+	/* Enable Hotplug Detect thread */
+	irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN);
+	ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN],
+					NULL, cdns_hdmi_irq_thread,
+					IRQF_ONESHOT, dev_name(dev),
+					mhdp);
+	if (ret < 0) {
+		dev_err(dev, "can't claim irq %d\n",
+						mhdp-

irq[IRQ_IN]);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +11 -0

+		return -EINVAL;
+	}
+
+	irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN);
+	ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT],
+					NULL, cdns_hdmi_irq_thread,
+					IRQF_ONESHOT, dev_name(dev),
+					mhdp);
+	if (ret < 0) {
+		dev_err(dev, "can't claim irq %d\n",
+						mhdp-

irq[IRQ_OUT]);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +65 -0

+		return -EINVAL;
+	}
+
+	mhdp->dev = dev;
+
+	if (cdns_mhdp_hdmi_read_hpd(mhdp))
+		enable_irq(mhdp->irq[IRQ_OUT]);
+	else
+		enable_irq(mhdp->irq[IRQ_IN]);
+
+	mhdp->bridge.driver_private = mhdp;
+	mhdp->bridge.funcs = &cdns_hdmi_bridge_funcs;
+	mhdp->bridge.of_node = dev->of_node;
+	mhdp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
+			   DRM_BRIDGE_OP_HPD;
+	mhdp->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+	drm_bridge_add(&mhdp->bridge);
+
+	memset(&pdevinfo, 0, sizeof(pdevinfo));
+	pdevinfo.parent = dev;
+	pdevinfo.id = PLATFORM_DEVID_AUTO;
+
+	dev_set_drvdata(dev, mhdp);
+	mhdp->plat_data = of_device_get_match_data(dev);
+
+	return 0;
+}
+
+static int cdns_mhdp_imx_remove(struct platform_device *pdev)
+{
+	struct cdns_mhdp_device *mhdp = platform_get_drvdata(pdev);
+	int ret = 0;
+
+	drm_bridge_remove(&mhdp->bridge);
+
+	return ret;
+}
+
+static struct cdns_plat_data imx8mq_hdmi_drv_data = {
+	.lane_mapping = 0xe4,
+};
+
+static const struct of_device_id cdns_mhdp_imx_dt_ids[] = {
+	{ .compatible = "cdns,mhdp-imx8mq-hdmi",
+	  .data = &imx8mq_hdmi_drv_data
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, cdns_mhdp_imx_dt_ids);
+
+static struct platform_driver cdns_mhdp_imx_platform_driver = {
+	.probe  = cdns_mhdp_imx_probe,
+	.remove = cdns_mhdp_imx_remove,
+	.driver = {
+		.name = "cdns-mhdp-imx8mq-hdmi",
+		.of_match_table = cdns_mhdp_imx_dt_ids,
+	},
+};
+
+module_platform_driver(cdns_mhdp_imx_platform_driver);
+
+MODULE_AUTHOR("Sandor Yu <[email protected]>");
+MODULE_DESCRIPTION("Cadence HDMI transmitter driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:cdns-hdmi");

-----Original Message-----
From: Alexander Stein <[email protected]>
Sent: 2022年11月8日 21:17
To: [email protected]; Sandor Yu <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Oliver Brown <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; [email protected]; Sandor Yu <[email protected]>; [email protected]; [email protected]; [email protected]
Subject: [EXT] Re: [v2 06/10] drm: bridge: cadence: Add MHDP HDMI driver for i.MX8MQ

Caution: EXT Email

Hello,

thanks for working on this and the updated version.

Am Freitag, 4. November 2022, 07:44:56 CET schrieb Sandor Yu:

Quoted 5 lines

Add a new DRM HDMI bridge driver for Candence MHDP used in i.MX8MQ SOC. MHDP IP could support HDMI or DisplayPort standards according embedded Firmware running in the uCPU.

For iMX8MQ SOC, the HDMI FW was loaded and activated by SOC ROM

code.

Quoted 6 lines

Bootload binary included HDMI FW was required for the driver.

Signed-off-by Sandor Yu <[email protected]>

---
 drivers/gpu/drm/bridge/cadence/Kconfig        |   12 +
 .../gpu/drm/bridge/cadence/cdns-hdmi-core.c   | 1038

+++++++++++++++++

Quoted 29 lines

 2 files changed, 1050 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

(quoted diff) +0 -0

b/drivers/gpu/drm/bridge/cadence/Kconfig index
e79ae1af3765..377452d09992
100644

drivers/gpu/drm/bridge/cadence/Kconfig +12 -0

@@ -26,6 +26,18 @@ config DRM_CDNS_MHDP8546_J721E
        clock and data muxes.
 endif
 
+config DRM_CDNS_HDMI
+     tristate "Cadence HDMI DRM driver"
+     select DRM_KMS_HELPER
+     select DRM_PANEL_BRIDGE
+     select DRM_DISPLAY_HELPER
+     select DRM_CDNS_AUDIO
+     depends on OF
+     help
+       Support Cadence MHDP HDMI driver.
+       Cadence MHDP Controller support one or more protocols,
+       HDMI firmware is required for this driver.
+
 config DRM_CDNS_DP
      tristate "Cadence DP DRM driver"
      select DRM_KMS_HELPER

(quoted diff) +0 -0

Quoted 1 line

b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file mode

100644

Quoted 16 lines

index 000000000000..b392aac015bd

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +12 -0

@@ -0,0 +1,1038 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence High-Definition Multimedia Interface (HDMI) driver
+ *
+ * Copyright (C) 2019-2022 NXP Semiconductor, Inc.
+ *
+ */
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/hdmi.h>
+#include <linux/irq.h>
+#include <linux/module.h>

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 22

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+#include <linux/mfd/syscon.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-hdmi.h>
+
+#include <drm/bridge/cdns-mhdp-mailbox.h> #include
+<drm/display/drm_hdmi_helper.h> #include
+<drm/display/drm_scdc_helper.h> #include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h> #include <drm/drm_encoder_slave.h>

#include

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +7 -0

+<drm/drm_of.h> #include <drm/drm_probe_helper.h> #include
+<drm/drm_print.h> #include <drm/drm_vblank.h>
+
+#include "cdns-mhdp-common.h"
+
+void cdns_mhdp_infoframe_set(struct cdns_mhdp_device *mhdp,
+                                     u8 entry_id, u8 packet_len,

u8 *packet, u8 packet_type)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 8 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +8 -0

+{
+     u32 *packet32, len32;
+     u32 val, i;
+
+     /* invalidate entry */
+     val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id);
+     writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
+     writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs +

SOURCE_PIF_PKT_ALLOC_WR_EN);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+
+     /* flush fifo 1 */
+     writel(F_FIFO1_FLUSH(1), mhdp->regs +

SOURCE_PIF_FIFO1_FLUSH);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 47

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+
+     /* write packet into memory */
+     packet32 = (u32 *)packet;

This only works on little-endian machines, no?

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+     len32 = packet_len / 4;
+     for (i = 0; i < len32; i++)
+             writel(F_DATA_WR(packet32[i]), mhdp->regs +

SOURCE_PIF_DATA_WR);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+
+     /* write entry id */
+     writel(F_WR_ADDR(entry_id), mhdp->regs +

SOURCE_PIF_WR_ADDR);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +7 -0

+
+     /* write request */
+     writel(F_HOST_WR(1), mhdp->regs + SOURCE_PIF_WR_REQ);
+
+     /* update entry */
+     val =  F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) |
+                     F_PACKET_TYPE(packet_type) |

F_PKT_ALLOC_ADDRESS(entry_id);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+     writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
+
+     writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs +

SOURCE_PIF_PKT_ALLOC_WR_EN);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 75

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +11 -0

+}
+
+static int cdns_hdmi_get_edid_block(void *data, u8 *edid,
+                       u32 block, size_t length) {
+     struct cdns_mhdp_device *mhdp = data;
+     u8 msg[2], reg[5], i;
+     int ret;
+
+     mutex_lock(&mhdp->mbox_mutex);
+
+     for (i = 0; i < 4; i++) {

What is i? It is not used inside the loop.

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+             msg[0] = block / 2;
+             msg[1] = block % 2;
+
+             ret = cdns_mhdp_mailbox_send(mhdp,

MB_MODULE_ID_HDMI_TX,
HDMI_TX_EDID,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+                                       sizeof(msg), msg);
+             if (ret)
+                     continue;
+
+             ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_HDMI_TX,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 80

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1 -0

+

HDMI_TX_EDID, sizeof(reg) + length);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+             if (ret)
+                     continue;
+
+             ret = cdns_mhdp_mailbox_recv_data(mhdp, reg,

sizeof(reg));

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+             if (ret)
+                     continue;
+
+             ret = cdns_mhdp_mailbox_recv_data(mhdp, edid, length);
+             if (ret)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+                     continue;
+
+             if ((reg[3] << 8 | reg[4]) == length)
+                     break;
+     }
+
+     mutex_unlock(&mhdp->mbox_mutex);
+
+     if (ret)
+             DRM_ERROR("get block[%d] edid failed: %d\n", block,

ret);

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +6 -0

+     return ret;
+}
+
+int cdns_hdmi_scdc_read(struct cdns_mhdp_device *mhdp, u8 addr, u8
+*data) {
+     u8 msg[4], reg[6];

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     int ret;
+
+     msg[0] = 0x54;
+     msg[1] = addr;
+     msg[2] = 0;
+     msg[3] = 1;
+
+     mutex_lock(&mhdp->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX,

HDMI_TX_READ,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+                               sizeof(msg), msg);
+     if (ret)
+             goto err_scdc_read;
+
+     ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_HDMI_TX,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 121

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1 -0

+                                           HDMI_TX_READ,

sizeof(reg));

Quoted 22 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +22 -0

+     if (ret)
+             goto err_scdc_read;
+
+     ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+     if (ret)
+             goto err_scdc_read;
+
+     *data = reg[5];
+
+err_scdc_read:
+
+     mutex_unlock(&mhdp->mbox_mutex);
+
+     if (ret)
+             DRM_ERROR("scdc read failed: %d\n", ret);
+     return ret;
+}
+
+int cdns_hdmi_scdc_write(struct cdns_mhdp_device *mhdp, u8 addr, u8
+value) {
+     u8 msg[5], reg[5];
+     int ret;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+
+     msg[0] = 0x54;
+     msg[1] = addr;
+     msg[2] = 0;
+     msg[3] = 1;
+     msg[4] = value;
+
+     mutex_lock(&mhdp->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX,

HDMI_TX_WRITE,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+                               sizeof(msg), msg);
+     if (ret)
+             goto err_scdc_write;
+
+     ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_HDMI_TX,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 159

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1 -0

+                                           HDMI_TX_WRITE,

sizeof(reg));

Quoted 18 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +18 -0

+     if (ret)
+             goto err_scdc_write;
+
+     ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+     if (ret)
+             goto err_scdc_write;
+
+     if (reg[0] != 0)
+             ret = -EINVAL;
+
+err_scdc_write:
+
+     mutex_unlock(&mhdp->mbox_mutex);
+
+     if (ret)
+             DRM_ERROR("scdc write failed: %d\n", ret);
+     return ret;
+}

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+
+int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp,
+                              int protocol, u32 char_rate) {
+     u32 reg0;
+     u32 reg1;
+     u32 val;
+     int ret;
+
+     /* Set PHY to HDMI data */
+     ret = cdns_mhdp_reg_write(mhdp, PHY_DATA_SEL,

F_SOURCE_PHY_MHDP_SEL(1));

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+     if (ret < 0)
+             return ret;
+
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_HPD,
+                                     F_HPD_VALID_WIDTH(4) |

F_HPD_GLITCH_WIDTH(0));

Quoted 31 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +31 -0

+     if (ret < 0)
+             return ret;
+
+     /* open CARS */
+     ret = cdns_mhdp_reg_write(mhdp, SOURCE_PHY_CAR, 0xF);
+     if (ret < 0)
+             return ret;
+     ret = cdns_mhdp_reg_write(mhdp, SOURCE_HDTX_CAR, 0xFF);
+     if (ret < 0)
+             return ret;
+     ret = cdns_mhdp_reg_write(mhdp, SOURCE_PKT_CAR, 0xF);
+     if (ret < 0)
+             return ret;
+     ret = cdns_mhdp_reg_write(mhdp, SOURCE_AIF_CAR, 0xF);
+     if (ret < 0)
+             return ret;
+     ret = cdns_mhdp_reg_write(mhdp, SOURCE_CIPHER_CAR, 0xF);
+     if (ret < 0)
+             return ret;
+     ret = cdns_mhdp_reg_write(mhdp, SOURCE_CRYPTO_CAR, 0xF);
+     if (ret < 0)
+             return ret;
+     ret = cdns_mhdp_reg_write(mhdp, SOURCE_CEC_CAR, 3);
+     if (ret < 0)
+             return ret;
+
+     reg0 = reg1 = 0x7c1f;
+     if (protocol == MODE_HDMI_2_0 && char_rate >= 340000) {
+             reg0 = 0;
+             reg1 = 0xFFFFF;
+     }

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_0, reg0);
+     if (ret < 0)
+             return ret;
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_CLOCK_REG_1, reg1);
+     if (ret < 0)
+             return ret;
+
+     /* set hdmi mode and preemble mode data enable */
+     val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) |
+ F_DATA_EN(1)

|

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 234

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1 -0

+                     F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) |

F_PIC_3D(0XF);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +7 -0

+     ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+
+     return ret;
+}
+
+int cdns_hdmi_mode_config(struct cdns_mhdp_device *mhdp,
+                                           struct

drm_display_mode *mode,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 242

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1 -0

+                                               struct

video_info *video_info)

Quoted 7 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +7 -0

+{
+     int ret;
+     u32 val;
+     u32 vsync_lines = mode->vsync_end - mode->vsync_start;
+     u32 eof_lines = mode->vsync_start - mode->vdisplay;
+     u32 sof_lines = mode->vtotal - mode->vsync_end;
+     u32 hblank = mode->htotal - mode->hdisplay;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     u32 hactive = mode->hdisplay;
+     u32 vblank = mode->vtotal - mode->vdisplay;
+     u32 vactive = mode->vdisplay;
+     u32 hfront = mode->hsync_start - mode->hdisplay;
+     u32 hback = mode->htotal - mode->hsync_end;
+     u32 vfront = eof_lines;
+     u32 hsync = hblank - hfront - hback;
+     u32 vsync = vsync_lines;
+     u32 vback = sof_lines;
+     u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ?

0 : 1) +

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 260

Quoted 1 line

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1 -0

+                                             ((mode->flags &

DRM_MODE_FLAG_NVSYNC) ? 0 : 2);

Please fix the alignment.

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 13 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+
+     ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_H_SIZE, (hactive <<
+ 16) +

hblank); + if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+             return ret;
+
+     ret = cdns_mhdp_reg_write(mhdp, SCHEDULER_V_SIZE, (vactive <<
+ 16) +

vblank); + if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+             return ret;
+
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_FRONT_WIDTH,

(vfront

Quoted 1 line

+ <<

16) +

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

hfront); + if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+             return ret;
+
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_SYNC_WIDTH,

(vsync

Quoted 1 line

+ <<

16) +

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

hsync); + if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+             return ret;
+
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_SIGNAL_BACK_WIDTH,

(vback

Quoted 1 line

+ <<

16) +

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

hback); + if (ret < 0)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+             return ret;
+
+     ret = cdns_mhdp_reg_write(mhdp, HSYNC2VSYNC_POL_CTRL,

v_h_polarity);

Quoted 65 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +65 -0

+     if (ret < 0)
+             return ret;
+
+     /* Reset Data Enable */
+     cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER, &val);
+     val &= ~F_DATA_EN(1);
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+     if (ret < 0)
+             return ret;
+
+     /* Set bpc */
+     val &= ~F_VIF_DATA_WIDTH(3);
+     switch (video_info->bpc) {
+     case 10:
+             val |= F_VIF_DATA_WIDTH(1);
+             break;
+     case 12:
+             val |= F_VIF_DATA_WIDTH(2);
+             break;
+     case 16:
+             val |= F_VIF_DATA_WIDTH(3);
+             break;
+     case 8:
+     default:
+             val |= F_VIF_DATA_WIDTH(0);
+             break;
+     }
+
+     /* select color encoding */
+     val &= ~F_HDMI_ENCODING(3);
+     switch (video_info->color_fmt) {
+     case DRM_COLOR_FORMAT_YCBCR444:
+             val |= F_HDMI_ENCODING(2);
+             break;
+     case DRM_COLOR_FORMAT_YCBCR422:
+             val |= F_HDMI_ENCODING(1);
+             break;
+     case DRM_COLOR_FORMAT_YCBCR420:
+             val |= F_HDMI_ENCODING(3);
+             break;
+     case DRM_COLOR_FORMAT_RGB444:
+     default:
+             val |= F_HDMI_ENCODING(0);
+             break;
+     }
+
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+     if (ret < 0)
+             return ret;
+
+     /* set data enable */
+     val |= F_DATA_EN(1);
+     ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
+
+     return ret;
+}
+
+int cdns_hdmi_disable_gcp(struct cdns_mhdp_device *mhdp) {
+     u32 val;
+
+     cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER, &val);
+     val &= ~F_GCP_EN(1);
+
+     return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); }
+

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+int cdns_hdmi_enable_gcp(struct cdns_mhdp_device *mhdp) {
+     u32 val;
+
+     cdns_mhdp_reg_read(mhdp, HDTX_CONTROLLER, &val);
+     val |= F_GCP_EN(1);
+
+     return cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val); }
+
+static void hdmi_sink_config(struct cdns_mhdp_device *mhdp) {
+     struct drm_scdc *scdc =

&mhdp->curr_conn->display_info.hdmi.scdc;

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+     u8 buff = 0;
+
+     /* Default work in HDMI1.4 */
+     mhdp->hdmi.hdmi_type = MODE_HDMI_1_4;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+
+     /* check sink support SCDC or not */
+     if (scdc->supported != true) {
+             DRM_INFO("Sink Not Support SCDC\n");
+             return;
+     }
+
+     if (mhdp->hdmi.char_rate > 340000) {
+             /*
+              * TMDS Character Rate above 340MHz should working in

HDMI2.0

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 3 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+              * Enable scrambling and TMDS_Bit_Clock_Ratio
+              */
+             buff = SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 |

SCDC_SCRAMBLING_ENABLE;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+             mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
+     } else  if (scdc->scrambling.low_rates) {
+             /*
+              * Enable scrambling and HDMI2.0 when scrambling

capability of sink

Quoted 23 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +22 -0

+              * be indicated in the HF-VSDB LTE_340Mcsc_scramble bit
+              */
+             buff = SCDC_SCRAMBLING_ENABLE;
+             mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
+     }
+
+     /* TMDS config */
+     cdns_hdmi_scdc_write(mhdp, SCDC_TMDS_CONFIG, buff); }
+
+static void hdmi_lanes_config(struct cdns_mhdp_device *mhdp) {
+     u32 lane_mapping = mhdp->plat_data->lane_mapping;
+     /* Line swapping */
+     cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 |
+lane_mapping); }
+
+int cdns_mhdp_hdmi_read_hpd(struct cdns_mhdp_device *mhdp) {
+     u8 status;
+     int ret;
+
+     mutex_lock(&mhdp->mbox_mutex);
+
+     ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX,

HDMI_TX_HPD_STATUS, + 0, NULL);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+     if (ret)
+             goto err_get_hpd;
+
+     ret = cdns_mhdp_mailbox_recv_header(mhdp,

MB_MODULE_ID_HDMI_TX,

Quoted 1 line

+

HDMI_TX_HPD_STATUS, sizeof(status));

Quoted 19 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +19 -0

+     if (ret)
+             goto err_get_hpd;
+
+     ret = cdns_mhdp_mailbox_recv_data(mhdp, &status, sizeof(status));
+     if (ret)
+             goto err_get_hpd;
+
+     mutex_unlock(&mhdp->mbox_mutex);
+     return status;
+
+err_get_hpd:
+     mutex_unlock(&mhdp->mbox_mutex);
+     DRM_ERROR("read hpd  failed: %d\n", ret);
+     return ret;
+}
+
+static int hdmi_avi_info_set(struct cdns_mhdp_device *mhdp,
+                          struct drm_display_mode *mode) {
+     struct hdmi_avi_infoframe frame;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     int format = mhdp->video_info.color_fmt;
+     struct drm_connector_state *conn_state = mhdp->curr_conn->state;
+     struct drm_display_mode *adj_mode;
+     enum hdmi_quantization_range qr;
+     u8 buf[32];
+     int ret;
+
+     /* Initialise info frame from DRM mode */
+     drm_hdmi_avi_infoframe_from_display_mode(&frame,
+                                             mhdp->curr_conn,

mode);

Quoted 39 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +37 -0

+
+     switch (format) {
+     case DRM_COLOR_FORMAT_YCBCR444:
+             frame.colorspace = HDMI_COLORSPACE_YUV444;
+             break;
+     case DRM_COLOR_FORMAT_YCBCR422:
+             frame.colorspace = HDMI_COLORSPACE_YUV422;
+             break;
+     case DRM_COLOR_FORMAT_YCBCR420:
+             frame.colorspace = HDMI_COLORSPACE_YUV420;
+             break;
+     default:
+             frame.colorspace = HDMI_COLORSPACE_RGB;
+             break;
+     }
+
+     drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state);
+
+     adj_mode = &mhdp->bridge.encoder->crtc->state->adjusted_mode;
+
+     qr = drm_default_rgb_quant_range(adj_mode);
+
+     drm_hdmi_avi_infoframe_quant_range(&frame, mhdp->curr_conn,
+                                        adj_mode, qr);
+
+     ret = hdmi_avi_infoframe_check(&frame);
+     if (WARN_ON(ret))
+             return -EINVAL;
+
+     ret = hdmi_avi_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
+     if (ret < 0) {
+             DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
+             return -1;
+     }
+
+     buf[0] = 0;
+     cdns_mhdp_infoframe_set(mhdp, 0, sizeof(buf), buf,

HDMI_INFOFRAME_TYPE_AVI); +

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +1 -0

+     return 0;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+}
+
+static void hdmi_vendor_info_set(struct cdns_mhdp_device *mhdp,
+                             struct drm_display_mode *mode) {
+     struct hdmi_vendor_infoframe frame;
+     u8 buf[32];
+     int ret;
+
+     /* Initialise vendor frame from DRM mode */
+     ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame,

mhdp-

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 9 lines

curr_conn,
mode); + if (ret < 0) {

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +7 -0

+             DRM_INFO("No vendor infoframe\n");
+             return;
+     }
+
+     ret = hdmi_vendor_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
+     if (ret < 0) {
+             DRM_WARN("Unable to pack vendor infoframe: %d\n",

ret);

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+             return;
+     }
+
+     buf[0] = 0;
+     cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf,

HDMI_INFOFRAME_TYPE_VENDOR); +}

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+
+static void hdmi_drm_info_set(struct cdns_mhdp_device *mhdp) {
+     struct drm_connector_state *conn_state;
+     struct hdmi_drm_infoframe frame;
+     u8 buf[32];

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     int ret;
+
+     conn_state = mhdp->curr_conn->state;
+
+     if (!conn_state->hdr_output_metadata)
+             return;
+
+     ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
+     if (ret < 0) {
+             DRM_DEBUG_KMS("couldn't set HDR metadata in

infoframe\n");

Quoted 32 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +11 -0

+             return;
+     }
+
+     ret = hdmi_drm_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
+     if (ret < 0) {
+             DRM_DEBUG_KMS("couldn't pack HDR infoframe\n");
+             return;
+     }
+
+     buf[0] = 0;
+     cdns_mhdp_infoframe_set(mhdp, 3, sizeof(buf), buf,

HDMI_INFOFRAME_TYPE_DRM); +}

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +20 -0

+
+static int hdmi_phy_colorspace(int color_fmt) {
+     int color_space;
+
+     switch (color_fmt) {
+     case DRM_COLOR_FORMAT_YCBCR444:
+             color_space = HDMI_PHY_COLORSPACE_YUV444;
+             break;
+     case DRM_COLOR_FORMAT_YCBCR422:
+             color_space = HDMI_PHY_COLORSPACE_YUV422;
+             break;
+     case DRM_COLOR_FORMAT_YCBCR420:
+             color_space = HDMI_PHY_COLORSPACE_YUV420;
+             break;
+     case DRM_COLOR_FORMAT_RGB444:
+     default:
+             color_space = HDMI_PHY_COLORSPACE_RGB;
+             break;
+     }
+

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     return color_space;
+}
+
+void cdns_hdmi_mode_set(struct cdns_mhdp_device *mhdp) {
+     struct drm_display_mode *mode = &mhdp->mode;
+     union phy_configure_opts phy_cfg;
+     int ret;
+
+     /* video mode check */
+     if (mode->clock == 0 || mode->hdisplay == 0 ||  mode->vdisplay ==

0)

Quoted 33 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +7 -0

+             return;
+
+     hdmi_lanes_config(mhdp);
+
+     phy_cfg.hdmi.pixel_clk_rate = mode->clock;
+     phy_cfg.hdmi.bpc = mhdp->video_info.bpc;
+     phy_cfg.hdmi.color_space =

hdmi_phy_colorspace(mhdp->video_info.color_fmt); + ret =
phy_configure(mhdp->phy, &phy_cfg);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +9 -0

+     if (ret) {
+             dev_err(mhdp->dev, "%s: phy_configure() failed: %d\n",
+                     __func__, ret);
+             return;
+     }
+
+     hdmi_sink_config(mhdp);
+
+     ret = cdns_hdmi_ctrl_init(mhdp, mhdp->hdmi.hdmi_type,

mhdp->hdmi.char_rate); + if (ret < 0) {

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +14 -0

+             DRM_ERROR("%s, ret = %d\n", __func__, ret);
+             return;
+     }
+
+     /* Config GCP */
+     if (mhdp->video_info.bpc == 8)
+             cdns_hdmi_disable_gcp(mhdp);
+     else
+             cdns_hdmi_enable_gcp(mhdp);
+
+     ret = hdmi_avi_info_set(mhdp, mode);
+     if (ret < 0) {
+             DRM_ERROR("%s ret = %d\n", __func__, ret);
+             return;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     }
+
+     /* vendor info frame is enabled only for HDMI1.4 4K mode */
+     hdmi_vendor_info_set(mhdp, mode);
+
+     hdmi_drm_info_set(mhdp);
+
+     ret = cdns_hdmi_mode_config(mhdp, mode, &mhdp->video_info);
+     if (ret < 0) {
+             DRM_ERROR("CDN_API_HDMITX_SetVic_blocking ret

= %d\n",
ret);

Quoted 17 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +17 -0

+             return;
+     }
+}
+static enum drm_connector_status
+cdns_hdmi_detect(struct cdns_mhdp_device *mhdp) {
+     u8 hpd = 0xf;
+
+     hpd = cdns_mhdp_hdmi_read_hpd(mhdp);
+     if (hpd == 1)
+             return connector_status_connected;
+     else if (hpd == 0)
+             return connector_status_disconnected;
+
+     DRM_INFO("Unknown cable status, hdp=%u\n", hpd);
+     return connector_status_unknown; }
+
+static enum drm_connector_status

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+cdns_hdmi_bridge_detect(struct drm_bridge *bridge) {
+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+
+     return cdns_hdmi_detect(mhdp);
+}
+
+static int cdns_hdmi_connector_get_modes(struct drm_connector
+*connector) {
+     struct cdns_mhdp_device *mhdp =
+                             container_of(connector, struct

cdns_mhdp_device, connector);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+     int num_modes = 0;
+     struct edid *edid;
+
+     edid = drm_do_get_edid(connector,
+                                cdns_hdmi_get_edid_block,

mhdp);

Quoted 26 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +26 -0

+     if (edid) {
+             dev_info(mhdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n",
+                      edid->header[0], edid->header[1],
+                      edid->header[2], edid->header[3],
+                      edid->header[4], edid->header[5],
+                      edid->header[6], edid->header[7]);
+             drm_connector_update_edid_property(connector, edid);
+             num_modes = drm_add_edid_modes(connector, edid);
+             kfree(edid);
+     }
+
+     if (num_modes == 0)
+             DRM_ERROR("Invalid edid\n");
+     return num_modes;
+}
+
+static bool blob_equal(const struct drm_property_blob *a,
+                    const struct drm_property_blob *b) {
+     if (a && b)
+             return a->length == b->length &&
+                     !memcmp(a->data, b->data, a->length);
+
+     return !a == !b;
+}
+
+static int cdns_hdmi_connector_atomic_check(struct drm_connector

Quoted 1 line

*connector, + struct

drm_atomic_state *state)

Quoted 20 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +19 -0

+{
+     struct drm_connector_state *new_con_state =
+             drm_atomic_get_new_connector_state(state, connector);
+     struct drm_connector_state *old_con_state =
+             drm_atomic_get_old_connector_state(state, connector);
+     struct drm_crtc *crtc = new_con_state->crtc;
+     struct drm_crtc_state *new_crtc_state;
+
+     if (!blob_equal(new_con_state->hdr_output_metadata,
+                     old_con_state->hdr_output_metadata) ||
+         new_con_state->colorspace != old_con_state->colorspace) {
+             new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
+             if (IS_ERR(new_crtc_state))
+                     return PTR_ERR(new_crtc_state);
+
+             new_crtc_state->mode_changed =
+                     !new_con_state->hdr_output_metadata ||
+                     !old_con_state->hdr_output_metadata ||
+                     new_con_state->colorspace != old_con_state-

colorspace;

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     }
+
+     return 0;
+}
+
+static const struct drm_connector_funcs cdns_hdmi_connector_funcs = {
+     .fill_modes = drm_helper_probe_single_connector_modes,
+     .destroy = drm_connector_cleanup,
+     .reset = drm_atomic_helper_connector_reset,
+     .atomic_duplicate_state =

drm_atomic_helper_connector_duplicate_state,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 717

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+     .atomic_destroy_state =
+drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_connector_helper_funcs

cdns_hdmi_connector_helper_funcs = { + .get_modes =
cdns_hdmi_connector_get_modes,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+     .atomic_check = cdns_hdmi_connector_atomic_check, };
+
+static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge,
+                              enum drm_bridge_attach_flags flags)

{

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+     struct drm_mode_config *config = &bridge->dev->mode_config;
+     struct drm_encoder *encoder = bridge->encoder;
+     struct drm_connector *connector = &mhdp->connector;
+
+     if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+             connector->interlace_allowed = 0;
+             connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+             drm_connector_helper_add(connector,

&cdns_hdmi_connector_helper_funcs);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 2 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +2 -0

+
+             drm_connector_init(bridge->dev, connector,

&cdns_hdmi_connector_funcs,

Quoted 1 line

+

DRM_MODE_CONNECTOR_HDMIA);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+
+             drm_object_attach_property(&connector->base,
+                                        config-

hdr_output_metadata_property, 0);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +2 -0

+
+             if

(!drm_mode_create_hdmi_colorspace_property(connector))

Quoted 1 line

+

drm_object_attach_property(&connector->base,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 13 lines

+ connector-
colorspace_property, 0);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +11 -0

+
+             drm_connector_attach_encoder(connector, encoder);
+     }
+
+     return 0;
+}
+
+static enum drm_mode_status
+cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
+                             const struct drm_display_info *info,
+                             const struct drm_display_mode

*mode) {

Quoted 19 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +19 -0

+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+     enum drm_mode_status mode_status = MODE_OK;
+     union phy_configure_opts phy_cfg;
+     int ret;
+
+     /* We don't support double-clocked and Interlaced modes */
+     if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
+                     mode->flags & DRM_MODE_FLAG_INTERLACE)
+             return MODE_BAD;
+
+     /* MAX support pixel clock rate 594MHz */
+     if (mode->clock > 594000)
+             return MODE_CLOCK_HIGH;
+
+     /* 4096x2160 is not supported */
+     if (mode->hdisplay > 3840 || mode->vdisplay > 2160)
+             return MODE_BAD_HVALUE;
+
+     /* Check modes supported by PHY */

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+     phy_cfg.hdmi.pixel_clk_rate = mode->clock;
+     ret = phy_validate(mhdp->phy, PHY_MODE_HDMI, 0, &phy_cfg);
+     if (ret < 0)
+             return MODE_CLOCK_RANGE;
+
+     return mode_status;
+}
+
+bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
+                              const struct drm_display_mode

*mode,

Quoted 1 line

+ struct drm_display_mode

*adjusted_mode)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 12 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +12 -0

+{
+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+     struct video_info *video = &mhdp->video_info;
+
+     video->bpc = 8;
+     video->color_fmt = DRM_COLOR_FORMAT_RGB444;
+
+     return true;
+}
+
+static struct edid *cdns_hdmi_bridge_get_edid(struct drm_bridge *bridge,
+                                           struct

drm_connector
*connector)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 8 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +8 -0

+{
+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+
+     return drm_do_get_edid(connector, cdns_hdmi_get_edid_block,
+mhdp); }
+
+static void cdns_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
+                                       struct drm_bridge_state

*old_state)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 12 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +12 -0

+{
+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+
+     mhdp->curr_conn = NULL;
+
+     mutex_lock(&mhdp->lock);
+     phy_power_off(mhdp->phy);
+     mutex_unlock(&mhdp->lock);
+}
+
+static void cdns_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
+                                      struct drm_bridge_state

*old_state)

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c line 826

Quoted 11 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +11 -0

+{
+     struct cdns_mhdp_device *mhdp = bridge->driver_private;
+     struct drm_atomic_state *state = old_state->base.state;
+     struct drm_connector *connector;
+     struct video_info *video = &mhdp->video_info;
+     struct drm_crtc_state *crtc_state;
+     struct drm_connector_state *conn_state;
+     const struct drm_display_mode *mode;
+
+     connector = drm_atomic_get_new_connector_for_encoder(state,
+

bridge->encoder);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +6 -0

+     if (WARN_ON(!connector))
+             return;
+
+     mhdp->curr_conn = connector;
+
+     conn_state = drm_atomic_get_new_connector_state(state,

connector);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 4 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +4 -0

+     if (WARN_ON(!conn_state))
+             return;
+
+     crtc_state = drm_atomic_get_new_crtc_state(state,

conn_state->crtc);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+     if (WARN_ON(!crtc_state))
+             return;
+
+     mode = &crtc_state->adjusted_mode;
+     DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay,

mode->vdisplay,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 5 lines

+ mode-
clock);

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +3 -0

+     memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
+
+     video->v_sync_polarity = !!(mode->flags &

DRM_MODE_FLAG_NVSYNC);

Quoted 1 line

+ video->h_sync_polarity = !!(mode->flags &

DRM_MODE_FLAG_NHSYNC);

Quoted 5 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +5 -0

+
+     mutex_lock(&mhdp->lock);
+     cdns_hdmi_mode_set(mhdp);
+     mutex_unlock(&mhdp->lock);
+}

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 10 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +10 -0

+
+static const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = {
+     .attach = cdns_hdmi_bridge_attach,
+     .detect = cdns_hdmi_bridge_detect,
+     .get_edid = cdns_hdmi_bridge_get_edid,
+     .mode_valid = cdns_hdmi_bridge_mode_valid,
+     .mode_fixup = cdns_hdmi_bridge_mode_fixup,
+     .atomic_enable = cdns_hdmi_bridge_atomic_enable,
+     .atomic_disable = cdns_hdmi_bridge_atomic_disable,
+     .atomic_duplicate_state =

drm_atomic_helper_bridge_duplicate_state,

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c

Quoted 6 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +6 -0

+     .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+     .atomic_reset = drm_atomic_helper_bridge_reset, };
+
+static void hotplug_work_func(struct work_struct *work) {
+     struct cdns_mhdp_device *mhdp = container_of(work,
+                                        struct

cdns_mhdp_device,
hotplug_work.work);

Quoted 42 lines

drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c new file +42 -0

+     enum drm_connector_status status = cdns_hdmi_detect(mhdp);
+
+     drm_bridge_hpd_notify(&mhdp->bridge, status);
+
+     if (status == connector_status_connected) {
+             DRM_INFO("HDMI Cable Plug In\n");
+             enable_irq(mhdp->irq[IRQ_OUT]);
+     } else if (status == connector_status_disconnected) {
+             /* Cable Disconnedted  */
+             DRM_INFO("HDMI Cable Plug Out\n");
+             enable_irq(mhdp->irq[IRQ_IN]);
+     }
+}
+
+static irqreturn_t cdns_hdmi_irq_thread(int irq, void *data) {
+     struct cdns_mhdp_device *mhdp = data;
+
+     disable_irq_nosync(irq);
+
+     mod_delayed_work(system_wq, &mhdp->hotplug_work,
+                     msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
+
+     return IRQ_HANDLED;
+}
+
+static int cdns_mhdp_imx_probe(struct platform_device *pdev) {
+     struct device *dev = &pdev->dev;
+     struct cdns_mhdp_device *mhdp;
+     struct platform_device_info pdevinfo;
+     struct resource *res;
+     u32 reg;
+     int ret;
+
+     mhdp = devm_kzalloc(dev, sizeof(*mhdp), GFP_KERNEL);
+     if (!mhdp)
+             return -ENOMEM;
+
+     mutex_init(&mhdp->lock);
+     mutex_init(&mhdp->mbox_mutex);
+
+     INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func);
+