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Add support for Variscite VAR-SOM-MX7 and MX7CustomBoard

PATCH Superseded Stefano Radaelli 3 participants 7 messages Aug 25

Subsystems (2)

v4 of 8 Superseded Latest is v8 →

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#0 lore raw

v4 cover Add support for Variscite VAR-SOM-MX7 and MX7CustomBoard

This patch series adds support for the Variscite VAR-SOM-MX7 system on module and the MX7CustomBoard carrier board.

The series includes:

- DT bindings for the supported VAR-SOM-MX7 board configurations
- VAR-SOM-MX7 device tree support, including V1 and V2 hardware revisions
- MX7CustomBoard carrier board support
- eMMC and NAND storage variants
- optional WM8731 audio codec support

The implementation follows the standard SOM + carrier board pattern, where the common SOM dtsi contains the on-module peripherals and hardware revision differences, while the MX7CustomBoard dtsi contains the carrier-specific interfaces.

The final board device trees combine the supported VAR-SOM-MX7 configurations with the MX7CustomBoard carrier board.

v3->v4:
- Fixed non-generic names and wrong separators
- Fixed ads7846_ts pendown gpio

v2->v3:
- Removed wrong header in dtsi
- Fixed pinctrl name
- Fixed sai clocks

v1->v2:
- Fixed commit messages and spacing
- Moved ethphy1 reset pin mux
- Fixed irq types
- Removed duplicate assigned-clock-rates property
- fixed wifi child node name
- Added color property in gpio led definition
- Updated deprecated reset-gpio property
- Added disable-over-current property in usb nodes
- Fixed model names

Stefano Radaelli (3):
dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards
ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support
ARM: dts: imx7d: add Variscite MX7CustomBoard support

 .../devicetree/bindings/arm/fsl.yaml          |  17 +
 arch/arm/boot/dts/nxp/imx/Makefile            |   6 +
 .../imx/imx7d-var-som-emmc-mx7customboard.dts |  22 +
 ...x7d-var-som-emmc-wm8731-mx7customboard.dts |  23 +
 .../boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi  |  99 +++
 .../nxp/imx/imx7d-var-som-mx7customboard.dtsi | 382 +++++++++++
 .../imx/imx7d-var-som-nand-mx7customboard.dts |  22 +
 ...x7d-var-som-nand-wm8731-mx7customboard.dts |  23 +
 .../boot/dts/nxp/imx/imx7d-var-som-nand.dtsi  |  73 ++
 .../imx7d-var-som-v2-emmc-mx7customboard.dts  |  23 +
 .../imx7d-var-som-v2-nand-mx7customboard.dts  |  23 +
 .../boot/dts/nxp/imx/imx7d-var-som-v2.dtsi    |  66 ++
 .../dts/nxp/imx/imx7d-var-som-wm8731.dtsi     |  65 ++
 arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi  | 635 ++++++++++++++++++
 14 files changed, 1479 insertions(+)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-wm8731-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-emmc-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-nand-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi

base-commit: 9400c5b6aa357be2379c98ae86a207bc21dc7a48

Signature · 1 line
2.47.3
#1 lore raw

PATCH v4 1/3 dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards

From: Stefano Radaelli <[email protected]>

Add DT compatible strings for the Variscite VAR-SOM-MX7 SoM variants used with the MX7CustomBoard carrier board.

Both the first and second hardware revisions are supported, including eMMC and NAND configurations, with WM8731 variants available for the first hardware revision.

---
v3->v4:
-

v2->v3:
-

v1->v2:
- Fixed commit message
- Fixed spacing

 Documentation/devicetree/bindings/arm/fsl.yaml | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
Documentation/devicetree/bindings/arm/fsl.yaml +17 -0
index 656f2596e1d5..b732ff810265 100644
@@ -950,6 +950,23 @@ properties:
           - const: toradex,colibri-imx7d-emmc
           - const: fsl,imx7d
 
+      - description: i.MX7D Variscite Boards based on VAR-SOM-MX7 Module
+        oneOf:
+          - items:
+              - enum:
+                  - variscite,var-som-imx7d-emmc-mx7customboard
+                  - variscite,var-som-imx7d-emmc-wm8731-mx7customboard
+                  - variscite,var-som-imx7d-nand-mx7customboard
+                  - variscite,var-som-imx7d-nand-wm8731-mx7customboard
+              - const: variscite,var-som-imx7d
+              - const: fsl,imx7d
+          - items:
+              - enum:
+                  - variscite,var-som-imx7d-v2-emmc-mx7customboard
+                  - variscite,var-som-imx7d-v2-nand-mx7customboard
+              - const: variscite,var-som-imx7d-v2
+              - const: fsl,imx7d
+
       - description: i.MX7ULP based Boards
         items:
           - enum:
Signature · 1 line
2.47.3
#2 lore raw

PATCH v4 2/3 ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add device tree support for the Variscite VAR-SOM-MX7 system on module.

The module is based on the NXP i.MX7Dual SoC and is available in multiple configurations and hardware revisions.

Add the common SoM description together with support for:
- eMMC storage
- NAND storage
- WM8731 audio codec
- VAR-SOM-MX7 V2 hardware revision

Only SoM-specific peripherals are described here. Carrier board specific interfaces are provided by the respective carrier board device trees.

---
v3->v4:
- Fixed non-generic names and wrong separators
- Fixed ads7846_ts pendown gpio

v2->v3:
- Removed wrong header in dtsi
- Fixed pinctrl name
- Fixed sai clocks

v1->v2:
- Moved ethphy1 reset pin mux
- Fixed irq types
- Removed duplicate assigned-clock-rates property
- fixed wifi child node name
- Added color property in gpio led definition
- Updated deprecated reset-gpio propery
- Added disable-over-current property in usb nodes

 .../boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi  |  99 +++
 .../nxp/imx/imx7d-var-som-mx7customboard.dtsi | 382 +++++++++++
 .../boot/dts/nxp/imx/imx7d-var-som-nand.dtsi  |  73 ++
 .../boot/dts/nxp/imx/imx7d-var-som-v2.dtsi    |  66 ++
 .../dts/nxp/imx/imx7d-var-som-wm8731.dtsi     |  65 ++
 arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi  | 635 ++++++++++++++++++
 6 files changed, 1320 insertions(+)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +99 -0
new file mode 100644
index 000000000000..2f8185f8c526
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common dtsi for eMMC support on Variscite VAR-SOM-MX7
+ *
+ * Link: https://variscite.com/system-on-module-som/i-mx-7/var-som-mx7/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+&gpio6 {
+	sd3-pwr-hog {
+		gpio-hog;
+		gpios = <11 0>;
+		output-low;
+		line-name = "sd3_pwr";
+	};
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+	vmmc-supply = <&vgen3_reg>;
+	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+	assigned-clock-rates = <400000000>;
+	no-1-8-v;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59
+			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
+			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
+			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
+			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
+			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
+			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
+			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
+			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
+			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
+			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
+		>;
+	};
+
+	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__GPIO6_IO11	0x10
+			MX7D_PAD_SD3_CMD__GPIO6_IO1		0x10
+			MX7D_PAD_SD3_CLK__GPIO6_IO0		0x10
+			MX7D_PAD_SD3_DATA0__GPIO6_IO2		0x10
+			MX7D_PAD_SD3_DATA1__GPIO6_IO3		0x10
+			MX7D_PAD_SD3_DATA2__GPIO6_IO4		0x10
+			MX7D_PAD_SD3_DATA3__GPIO6_IO5		0x10
+			MX7D_PAD_SD3_DATA4__GPIO6_IO6		0x10
+			MX7D_PAD_SD3_DATA5__GPIO6_IO7		0x10
+			MX7D_PAD_SD3_DATA6__GPIO6_IO8		0x10
+			MX7D_PAD_SD3_DATA7__GPIO6_IO9		0x10
+		>;
+	};
+};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +382 -0

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arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand.dtsi new file +73 -0

73 lines not on this page · raw message

arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi new file +66 -0

66 lines not on this page · raw message

arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +65 -0

65 lines not on this page · raw message

arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +635 -0

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Signature · 1 line
2.47.3
#3 lore raw

Re: [PATCH v4 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] The `sw1a` regulator maximum voltage is set to 3.3V, which violates the i.MX7D core voltage limits…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The sw1a regulator maximum voltage is set to 3.3V, which violates the i.MX7D core voltage limits (typically 1.0V, max 1.15V) and the PFUZE3000 SW1A hardware limit for this design (max 1.475V).
- [High] Deleting fsl,sai-mclk-direction-output prevents the SoC from outputting the required Master Clock (MCLK) to the WM8731 audio codec.
- [Medium] The sd3-pwr-hog GPIO hog on gpio6 11 directly conflicts with the native usdhc3 pinctrl configuration for SD3_RESET_B.
--

--- Patch [2]: [PATCH v4 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support --- commit a699faaceb07c2b3521d089b94e7deba5e25dd8b
Author: Stefano Radaelli <[email protected]>

ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

Add device tree support for the Variscite VAR-SOM-MX7 system on module. The module is based on the NXP i.MX7Dual SoC.

Quoted 4 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +0 -0
new file mode 100644

[ ... ]

Quoted 8 lines

+&gpio6 {

arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +7 -0
+	sd3-pwr-hog {
+		gpio-hog;
+		gpios = <11 0>;
+		output-low;
+		line-name = "sd3_pwr";
+	};
+};

[ ... ]

arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi line 38

Quoted 4 lines

+&iomuxc {

arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +3 -0
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59

[Severity: Medium]
Does this GPIO hog conflict with the native usdhc3 pinctrl configuration for SD3_RESET_B?

The sd3-pwr-hog statically claims gpio6 11, which corresponds to MX7D_PAD_SD3_RESET_B. The pinctrl_usdhc3 later claims the exact same pad as SD3_RESET_B in its native mode.

Could this cause a device tree resource conflict over the pad, and potentially spuriously reset the eMMC during sleep transitions if the pin reverts to the driven-low GPIO state?

Quoted 4 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +0 -0
new file mode 100644

[ ... ]

arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi line 65

Quoted 4 lines

+&sai1 {

arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +3 -0
+	assigned-clock-rates = <0>, <36864000>;
+	/delete-property/ fsl,sai-mclk-direction-output;
+};

[Severity: High]
Does deleting the fsl,sai-mclk-direction-output property prevent the SoC from outputting the required master clock to the WM8731 audio codec?

The WM8731 codec requires an MCLK to function. By removing this direction property, the SAI block might configure the pad as an input, which would leave the codec without a master clock from the SoC.

Quoted 4 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +0 -0
new file mode 100644

[ ... ]

Quoted 1 line

+&i2c1 {

[ ... ]

arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi line 204

Quoted 8 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +8 -0
+	pfuze300: pmic@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;

[Severity: High]
Does setting the sw1a maximum voltage to 3.3V violate the hardware limits for the i.MX7D core voltage?

The sw1a regulator supplies the cpu0 and cpu1 cores. The PFUZE3000 SW1A limit for this design is typically around 1.475V, and the absolute maximum rating for the i.MX7D ARM cores is usually around 1.15V.

If a driver scales the core voltage up to 3.3V based on these boundaries, could this result in hardware damage?

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
#4 lore raw

Re: [PATCH v4 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

Quoted 40 lines · On Tue, Aug 25, 2026 at 07:16:48AM +0000, [email protected] wrote:

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The sw1a regulator maximum voltage is set to 3.3V, which violates the i.MX7D core voltage limits (typically 1.0V, max 1.15V) and the PFUZE3000 SW1A hardware limit for this design (max 1.475V).
- [High] Deleting fsl,sai-mclk-direction-output prevents the SoC from outputting the required Master Clock (MCLK) to the WM8731 audio codec.
- [Medium] The sd3-pwr-hog GPIO hog on gpio6 11 directly conflicts with the native usdhc3 pinctrl configuration for SD3_RESET_B.
--

--- Patch [2]: [PATCH v4 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support --- commit a699faaceb07c2b3521d089b94e7deba5e25dd8b
Author: Stefano Radaelli <[email protected]>

ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

Add device tree support for the Variscite VAR-SOM-MX7 system on module. The module is based on the NXP i.MX7Dual SoC.

Quoted 4 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +0 -0
new file mode 100644

[ ... ]

Quoted 8 lines

+&gpio6 {

arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +7 -0
+	sd3-pwr-hog {
+		gpio-hog;
+		gpios = <11 0>;
+		output-low;
+		line-name = "sd3_pwr";
+	};
+};

[ ... ]

arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi line 38

Quoted 4 lines

+&iomuxc {

arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +3 -0
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x59

[Severity: Medium]
Does this GPIO hog conflict with the native usdhc3 pinctrl configuration for SD3_RESET_B?

Quoted 4 lines

The sd3-pwr-hog statically claims gpio6 11, which corresponds to MX7D_PAD_SD3_RESET_B. The pinctrl_usdhc3 later claims the exact same pad as SD3_RESET_B in its native mode.

Is it true?

Quoted 42 lines

Could this cause a device tree resource conflict over the pad, and potentially spuriously reset the eMMC during sleep transitions if the pin reverts to the driven-low GPIO state?

Quoted 4 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +0 -0
new file mode 100644

[ ... ]

arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi line 65

Quoted 4 lines

+&sai1 {

arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +3 -0
+	assigned-clock-rates = <0>, <36864000>;
+	/delete-property/ fsl,sai-mclk-direction-output;
+};

[Severity: High]
Does deleting the fsl,sai-mclk-direction-output property prevent the SoC from outputting the required master clock to the WM8731 audio codec?

The WM8731 codec requires an MCLK to function. By removing this direction property, the SAI block might configure the pad as an input, which would leave the codec without a master clock from the SoC.

Quoted 4 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +0 -0
new file mode 100644

[ ... ]

Quoted 1 line

+&i2c1 {

[ ... ]

arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi line 204

Quoted 8 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +8 -0
+	pfuze300: pmic@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;

[Severity: High]
Does setting the sw1a maximum voltage to 3.3V violate the hardware limits for the i.MX7D core voltage?

Quoted 6 lines

The sw1a regulator supplies the cpu0 and cpu1 cores. The PFUZE3000 SW1A limit for this design is typically around 1.475V, and the absolute maximum rating for the i.MX7D ARM cores is usually around 1.15V.

If a driver scales the core voltage up to 3.3V based on these boundaries, could this result in hardware damage?

Please double check this one?

Frank

Quoted 4 lines

--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2

#5 lore raw

Re: [PATCH v4 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support

Quoted 11 lines · Frank Li
Quoted 9 lines

[Severity: Medium]
Does this GPIO hog conflict with the native usdhc3 pinctrl configuration for SD3_RESET_B?

The sd3-pwr-hog statically claims gpio6 11, which corresponds to MX7D_PAD_SD3_RESET_B. The pinctrl_usdhc3 later claims the exact same pad as SD3_RESET_B in its native mode.

Is it true?

It's true, I'll fix it.

Quoted 5 lines
Quoted 5 lines

[Severity: High]
Does setting the sw1a maximum voltage to 3.3V violate the hardware limits for the i.MX7D core voltage?

Quoted 9 lines
Quoted 6 lines

The sw1a regulator supplies the cpu0 and cpu1 cores. The PFUZE3000 SW1A limit for this design is typically around 1.475V, and the absolute maximum rating for the i.MX7D ARM cores is usually around 1.15V.

If a driver scales the core voltage up to 3.3V based on these boundaries, could this result in hardware damage?

Please double check this one?

I double-checked this.
PFUZE3000 SW1A supports selector values up to 3.3 V;
the 1.475V limit applies to SW1B, not SW1A.
The regulator-max-microvolt value only defines the regulator constraint, while the actual CPU voltage is selected according to the i.MX7 OPP table. Therefore, the 3.3 V constraint does not cause the CPU supply to be driven to 3.3 V.

Best Regards,
Stefano

#6 lore raw

PATCH v4 3/3 ARM: dts: imx7d: add Variscite MX7CustomBoard support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add device tree support for the Variscite MX7CustomBoard carrier board with the VAR-SOM-MX7 system on module.

This includes supported board configurations for both VAR-SOM-MX7 hardware revisions, with eMMC and NAND variants, and WM8731 variants for the first hardware revision.

Also add the resulting DTBs to the i.MX7D device tree Makefile.

---
v3->v4:
-

v2->v3:
-

v1->v2:
- Fixed commit message
- Fixed model names

 arch/arm/boot/dts/nxp/imx/Makefile            |  6 +++++
 .../imx/imx7d-var-som-emmc-mx7customboard.dts | 22 ++++++++++++++++++
 ...x7d-var-som-emmc-wm8731-mx7customboard.dts | 23 +++++++++++++++++++
 .../imx/imx7d-var-som-nand-mx7customboard.dts | 22 ++++++++++++++++++
 ...x7d-var-som-nand-wm8731-mx7customboard.dts | 23 +++++++++++++++++++
 .../imx7d-var-som-v2-emmc-mx7customboard.dts  | 23 +++++++++++++++++++
 .../imx7d-var-som-v2-nand-mx7customboard.dts  | 23 +++++++++++++++++++
 7 files changed, 142 insertions(+)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-wm8731-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-emmc-mx7customboard.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-nand-mx7customboard.dts
arch/arm/boot/dts/nxp/imx/Makefile +6 -0
index 1a2539fa19b4..37da667f9ffb 100644
@@ -444,6 +444,12 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-reva.dtb \
 	imx7d-sdb-sht11.dtb \
 	imx7d-smegw01.dtb \
+	imx7d-var-som-emmc-mx7customboard.dtb \
+	imx7d-var-som-emmc-wm8731-mx7customboard.dtb \
+	imx7d-var-som-nand-mx7customboard.dtb \
+	imx7d-var-som-nand-wm8731-mx7customboard.dtb \
+	imx7d-var-som-v2-emmc-mx7customboard.dtb \
+	imx7d-var-som-v2-nand-mx7customboard.dtb \
 	imx7d-zii-rmu2.dtb \
 	imx7d-zii-rpu2.dtb \
 	imx7s-colibri-aster.dtb \
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-mx7customboard.dts new file +22 -0
new file mode 100644
index 000000000000..855b621b0ee8
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * VAR-MX7CustomBoard for VAR-SOM-MX7 with eMMC
+ *
+ * Link: https://variscite.com/carrier-boards/var-mx7customboard/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx7d-var-som.dtsi"
+#include "imx7d-var-som-emmc.dtsi"
+#include "imx7d-var-som-mx7customboard.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX7 with eMMC & WM8904 on VAR-MX7CustomBoard";
+	compatible = "variscite,var-som-imx7d-emmc-mx7customboard",
+		     "variscite,var-som-imx7d",
+		     "fsl,imx7d";
+};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts new file +23 -0
new file mode 100644
index 000000000000..94c4b1fa5d6c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * VAR-MX7CustomBoard for VAR-SOM-MX7 with eMMC and WM8731
+ *
+ * Link: https://variscite.com/carrier-boards/var-mx7customboard/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx7d-var-som.dtsi"
+#include "imx7d-var-som-emmc.dtsi"
+#include "imx7d-var-som-wm8731.dtsi"
+#include "imx7d-var-som-mx7customboard.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX7 with eMMC & WM8731 on VAR-MX7CustomBoard";
+	compatible = "variscite,var-som-imx7d-emmc-wm8731-mx7customboard",
+		     "variscite,var-som-imx7d",
+		     "fsl,imx7d";
+};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-mx7customboard.dts new file +22 -0
new file mode 100644
index 000000000000..0da9653ecffc
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * VAR-MX7CustomBoard for VAR-SOM-MX7 with NAND
+ *
+ * Link: https://variscite.com/carrier-boards/var-mx7customboard/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx7d-var-som.dtsi"
+#include "imx7d-var-som-nand.dtsi"
+#include "imx7d-var-som-mx7customboard.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX7 with NAND flash & WM8904 on VAR-MX7CustomBoard";
+	compatible = "variscite,var-som-imx7d-nand-mx7customboard",
+		     "variscite,var-som-imx7d",
+		     "fsl,imx7d";
+};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-wm8731-mx7customboard.dts new file +23 -0
new file mode 100644
index 000000000000..603b2dbf4c8e
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * VAR-MX7CustomBoard for VAR-SOM-MX7 with NAND and WM8731
+ *
+ * Link: https://variscite.com/carrier-boards/var-mx7customboard/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx7d-var-som.dtsi"
+#include "imx7d-var-som-nand.dtsi"
+#include "imx7d-var-som-wm8731.dtsi"
+#include "imx7d-var-som-mx7customboard.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX7 with NAND flash & WM8731 on VAR-MX7CustomBoard";
+	compatible = "variscite,var-som-imx7d-nand-wm8731-mx7customboard",
+		     "variscite,var-som-imx7d",
+		     "fsl,imx7d";
+};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-emmc-mx7customboard.dts new file +23 -0
new file mode 100644
index 000000000000..12971bfefdcc
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * VAR-MX7CustomBoard for VAR-SOM-MX7 V2 with eMMC
+ *
+ * Link: https://variscite.com/carrier-boards/var-mx7customboard/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx7d-var-som.dtsi"
+#include "imx7d-var-som-v2.dtsi"
+#include "imx7d-var-som-emmc.dtsi"
+#include "imx7d-var-som-mx7customboard.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX7-5G_V2 with eMMC & WM8904 on VAR-MX7CustomBoard";
+	compatible = "variscite,var-som-imx7d-v2-emmc-mx7customboard",
+		     "variscite,var-som-imx7d-v2",
+		     "fsl,imx7d";
+};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-nand-mx7customboard.dts new file +23 -0
new file mode 100644
index 000000000000..1c465e89f198
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * VAR-MX7CustomBoard for VAR-SOM-MX7 V2 with NAND
+ *
+ * Link: https://variscite.com/carrier-boards/var-mx7customboard/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx7d-var-som.dtsi"
+#include "imx7d-var-som-v2.dtsi"
+#include "imx7d-var-som-nand.dtsi"
+#include "imx7d-var-som-mx7customboard.dtsi"
+
+/ {
+	model = "Variscite VAR-SOM-MX7-5G_V2 with NAND flash & WM8904 on VAR-MX7CustomBoard";
+	compatible = "variscite,var-som-imx7d-v2-nand-mx7customboard",
+		     "variscite,var-som-imx7d-v2",
+		     "fsl,imx7d";
+};
Signature · 1 line
2.47.3