Add support for Variscite VAR-SOM-MX7 and MX7CustomBoard
Subsystems (2)
cover Add support for Variscite VAR-SOM-MX7 and MX7CustomBoard
This patch series adds support for the Variscite VAR-SOM-MX7 system on module and the MX7CustomBoard carrier board.
The series includes:
- DT bindings for the supported VAR-SOM-MX7 board configurations
- VAR-SOM-MX7 device tree support, including V1 and V2 hardware revisions
- MX7CustomBoard carrier board support
- eMMC and NAND storage variants
- optional WM8731 audio codec support
The implementation follows the standard SOM + carrier board pattern, where the common SOM dtsi contains the on-module peripherals and hardware revision differences, while the MX7CustomBoard dtsi contains the carrier-specific interfaces.
The final board device trees combine the supported VAR-SOM-MX7 configurations with the MX7CustomBoard carrier board.
Stefano Radaelli (3):
dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards
ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support
ARM: dts: imx7d: add Variscite MX7CustomBoard support
.../devicetree/bindings/arm/fsl.yaml | 17 + arch/arm/boot/dts/nxp/imx/Makefile | 6 + .../imx/imx7d-var-som-emmc-mx7customboard.dts | 22 + ...x7d-var-som-emmc-wm8731-mx7customboard.dts | 23 + .../boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi | 99 +++ .../nxp/imx/imx7d-var-som-mx7customboard.dtsi | 378 +++++++++++ .../imx/imx7d-var-som-nand-mx7customboard.dts | 22 + ...x7d-var-som-nand-wm8731-mx7customboard.dts | 23 + .../boot/dts/nxp/imx/imx7d-var-som-nand.dtsi | 73 ++ .../imx7d-var-som-v2-emmc-mx7customboard.dts | 23 + .../imx7d-var-som-v2-nand-mx7customboard.dts | 23 + .../boot/dts/nxp/imx/imx7d-var-som-v2.dtsi | 64 ++ .../dts/nxp/imx/imx7d-var-som-wm8731.dtsi | 65 ++ arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi | 633 ++++++++++++++++++ 14 files changed, 1471 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-wm8731-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-emmc-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-nand-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi
base-commit: 9400c5b6aa357be2379c98ae86a207bc21dc7a48
Signature · 1 line
2.47.3
PATCH 1/3 dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards
From: Stefano Radaelli <[email protected]>
Add DT compatible strings for the Variscite VAR-SOM-MX7 SoM variants used with the MX7CustomBoard carrier board.
Both the first and second hardware revisions are supported, with eMMC, NAND and WM8731 configurations.
--- Documentation/devicetree/bindings/arm/fsl.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
Documentation/devicetree/bindings/arm/fsl.yaml +17 -0
@@ -950,6 +950,23 @@ properties: - const: toradex,colibri-imx7d-emmc - const: fsl,imx7d + - description: i.MX7D Variscite Boards based on VAR-SOM-MX7 Module + oneOf: + - items: + - enum: + - variscite,var-som-imx7d-emmc-mx7customboard + - variscite,var-som-imx7d-emmc-wm8731-mx7customboard + - variscite,var-som-imx7d-nand-mx7customboard + - variscite,var-som-imx7d-nand-wm8731-mx7customboard + - const: variscite,var-som-imx7d + - const: fsl,imx7d + - items: + - enum: + - variscite,var-som-imx7d-v2-emmc-mx7customboard + - variscite,var-som-imx7d-v2-nand-mx7customboard + - const: variscite,var-som-imx7d-v2 + - const: fsl,imx7d + - description: i.MX7ULP based Boards items: - enum:
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v1 1/3] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Medium] Mismatch between commit message and schema definition regarding v2 WM8731 hardware…
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Mismatch between commit message and schema definition regarding v2 WM8731 hardware configurations.
- [Low] YAML formatting violates the 'indent-sequences: true' rule, causing yamllint validation failures. --
--- Patch [1]: [PATCH v1 1/3] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards --- commit 52d9fb69ce3c9933762d9090a8a1790cd333bffd
Author: Stefano Radaelli <[email protected]>
dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards
Add DT compatible strings for the Variscite VAR-SOM-MX7 SoM variants used with the MX7CustomBoard carrier board.
Quoted 2 lines
Both the first and second hardware revisions are supported, with eMMC, NAND and WM8731 configurations.
[Severity: Medium]
Does the v2 hardware revision actually support the WM8731 configurations?
The commit message states these configurations are supported for both hardware revisions, but the expected compatible strings for v2 (such as variscite,var-som-imx7d-v2-emmc-wm8731-mx7customboard and variscite,var-som-imx7d-v2-nand-wm8731-mx7customboard) are omitted from the v2 enum in the schema below.
Quoted 4 lines
Documentation/devicetree/bindings/arm/fsl.yaml +0
-0
[ ... ]
Documentation/devicetree/bindings/arm/fsl.yaml properties: · line 956
Quoted 4 lines
Documentation/devicetree/bindings/arm/fsl.yaml +4
-0+ - description: i.MX7D Variscite Boards based on VAR-SOM-MX7 Module + oneOf: + - items: + - enum:
[Severity: Low]
Will this formatting fail the kernel's yamllint checks during make dt_binding_check?
The block sequences (- enum: and - const:) under the items: keys are placed at the exact same indentation level as their parent mapping key. The
indent-sequences: true rule requires them to be indented further to pass schema validation checks.
Quoted 1 line
+ - variscite,var-som-imx7d-emmc-mx7customboard
[ ... ]
Quoted 6 lines
Documentation/devicetree/bindings/arm/fsl.yaml +6
-0+ - items: + - enum: + - variscite,var-som-imx7d-v2-emmc-mx7customboard + - variscite,var-som-imx7d-v2-nand-mx7customboard + - const: variscite,var-som-imx7d-v2 + - const: fsl,imx7d
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
Re: [PATCH v1 1/3] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX7 boards
In reply to Stefano Radaellipw-bot: not-applicable
PATCH 2/3 ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Add device tree support for the Variscite VAR-SOM-MX7 system on module.
The module is based on the NXP i.MX7Dual SoC and is available in multiple configurations and hardware revisions.
Add the common SoM description together with support for:
- eMMC storage
- NAND storage
- WM8731 audio codec
- VAR-SOM-MX7 V2 hardware revision
Only SoM-specific peripherals are described here. Carrier board specific interfaces are provided by the respective carrier board device trees.
--- .../boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi | 99 +++ .../nxp/imx/imx7d-var-som-mx7customboard.dtsi | 378 +++++++++++ .../boot/dts/nxp/imx/imx7d-var-som-nand.dtsi | 73 ++ .../boot/dts/nxp/imx/imx7d-var-som-v2.dtsi | 64 ++ .../dts/nxp/imx/imx7d-var-som-wm8731.dtsi | 65 ++ arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi | 633 ++++++++++++++++++ 6 files changed, 1312 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc.dtsi new file +99 -0
@@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for eMMC support on Variscite VAR-SOM-MX7 + * + * Link: https://variscite.com/system-on-module-som/i-mx-7/var-som-mx7/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +&gpio6 { + sd3-pwr-hog { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "sd3_pwr"; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <&vgen3_reg>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + no-1-8-v; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x10 + MX7D_PAD_SD3_CMD__GPIO6_IO1 0x10 + MX7D_PAD_SD3_CLK__GPIO6_IO0 0x10 + MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x10 + MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x10 + MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x10 + MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x10 + MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x10 + MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x10 + MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x10 + MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x10 + >; + }; +};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +378 -0
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand.dtsi new file +73 -0
73 lines not on this page · raw message
arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi new file +64 -0
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +65 -0
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arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +633 -0
633 lines not on this page · raw message
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v1 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider: - [High] The Ethernet PHY reset pin for `ethphy1` is muxed on the `fec2` node instead of `fec1`, causing…
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] The Ethernet PHY reset pin for ethphy1 is muxed on the fec2 node instead of fec1, causing PHY detection to fail during MDIO bus probe.
- [Medium] Use of IRQ_TYPE_NONE (0) for touchscreen controller interrupts.
- [Low] Duplicate assigned-clock-rates property in the &sai1 node.
- [Low] Attempting to delete a non-existent child node bcrmf@1 instead of wifi@1.
- [Low] Missing required color property in the GPIO LED definition.
- [Low] Use of deprecated reset-gpio property instead of reset-gpios in the PCIe node.
--
--- Patch [2]: [PATCH v1 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support --- commit 910d1859fce3905900b424cb29918719c63275b0
Author: Stefano Radaelli <[email protected]>
ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support
This commit adds device tree support for the Variscite VAR-SOM-MX7 system on module. It provides the common SoM description along with configurations for eMMC, NAND, WM8731 audio codec, and the V2 hardware revision.
Quoted 5 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +0
-0@@ -0,0 +1,378 @@
[ ... ]
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi line 50
Quoted 11 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +11
-0+ leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-d10 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + };
[Severity: Low]
Does this led-d10 node also need a color property? When function is specified, modern LED bindings generally require the color property to form sysfs directories in the format color:function.
[ ... ]
Quoted 6 lines
+&i2c4 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +5
-0+ clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi line 135
Quoted 10 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +10
-0+ sda-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio2>; + interrupts = <30 0>;
[Severity: Medium]
Is it intentional to use 0 (IRQ_TYPE_NONE) for the touchscreen interrupt trigger type here? This can cause the interrupt to be unconfigured or incorrectly configured by default, which may lead to missed touch events or an interrupt storm.
[ ... ]
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi line 146
Quoted 4 lines
+&pcie {
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +3
-0+ pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 31 GPIO_ACTIVE_LOW>;
[Severity: Low]
Could this use the standard reset-gpios property instead? The reset-gpio property is deprecated, and dtbs_check validation may emit warnings for it.
Quoted 5 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi new file +0
-0@@ -0,0 +1,64 @@
[ ... ]
arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi line 64
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi new file +5
-0+/* WiFi */ +&usdhc2 { + mmc-pwrseq = <&wifi_pwrseq>; + /delete-node/ bcrmf@1; +};
[Severity: Low]
Is there a typo in the node name here? The node defined in the base dtsi is wifi@1 (with the label brcmf). Trying to delete bcrmf@1 will cause the device tree compiler to fail since the node doesn't exist.
Quoted 5 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +0
-0@@ -0,0 +1,65 @@
[ ... ]
arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi line 63
Quoted 6 lines
+&sai1 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +5
-0+ assigned-clock-rates = <0>, <36864000>; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>;
[Severity: Low]
Does this node intend to duplicate the assigned-clock-rates property? The second definition (<0>, <12288000>) will silently overwrite the first one (<0>, <36864000>), which will cause DTC to emit a duplicate property warning and the intended 36.864MHz clock rate configuration to be lost.
Quoted 7 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +2
-0+ /delete-property/ fsl,sai-mclk-direction-output; +};arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +0
-0@@ -0,0 +1,633 @@
[ ... ]
Quoted 5 lines
+&ecspi1 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +4
-0+ pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-1 = <&pinctrl_ecspi1_sleep>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi line 108
Quoted 10 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +10
-0+ status = "okay"; + + /* Resistive touch controller */ + ads7846_ts: ads7846@0 { + reg = <0>; + compatible = "ti,ads7846"; + pinctrl-names ="default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <9 0>;
[Severity: Medium]
Is it intentional to use 0 (IRQ_TYPE_NONE) for this touch controller interrupt trigger type? This might result in the interrupt being unconfigured by default.
[ ... ]
Quoted 3 lines
+&fec1 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +2
-0+ pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_rst>;
[ ... ]
Quoted 17 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +17
-0+ mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <80000>; + vddio-supply = <®_phy_vddio>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi line 169
Quoted 10 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +10
-0+ reset-assert-us = <20000>; + reset-deassert-us = <80000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_rst>;
[Severity: High]
Does ethphy1 fail to reset during the MDIO bus probe on fec1?
Since ethphy1 is a child of the fec1 MDIO bus, fec1 will attempt to toggle its reset GPIO (&gpio4 3) when it probes. However, the pinctrl for this GPIO (&pinctrl_enet2_rst) is attached to fec2 instead of fec1. Since fec2 has not probed yet, the reset pin may not be muxed properly, preventing the reset toggle from reaching the PHY and causing detection to fail.
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
Re: [PATCH v1 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support
Quoted 69 lines · On Fri, Aug 21, 2026 at 12:41:07PM +0000, [email protected] wrote:
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] The Ethernet PHY reset pin forethphy1is muxed on thefec2node instead offec1, causing PHY detection to fail during MDIO bus probe.
- [Medium] Use ofIRQ_TYPE_NONE(0) for touchscreen controller interrupts.
- [Low] Duplicateassigned-clock-ratesproperty in the&sai1node.
- [Low] Attempting to delete a non-existent child nodebcrmf@1instead ofwifi@1.
- [Low] Missing requiredcolorproperty in the GPIO LED definition.
- [Low] Use of deprecatedreset-gpioproperty instead ofreset-gpiosin the PCIe node.
----- Patch [2]: [PATCH v1 2/3] ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support --- commit
910d1859fce3905900b424cb29918719c63275b0
Author: Stefano Radaelli <[email protected]>ARM: dts: imx7d: add Variscite VAR-SOM-MX7 support
This commit adds device tree support for the Variscite VAR-SOM-MX7 system on module. It provides the common SoM description along with configurations for eMMC, NAND, WM8731 audio codec, and the V2 hardware revision.
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +0
-0@@ -0,0 +1,378 @@[ ... ]
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi line 50
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +11
-0+ leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-d10 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + };[Severity: Low]
Does this led-d10 node also need a color property? When function is specified, modern LED bindings generally require the color property to form sysfs directories in the format color:function.[ ... ]
Quoted 6 lines
+&i2c4 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +5
-0+ clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi line 135
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +10
-0+ sda-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio2>; + interrupts = <30 0>;[Severity: Medium]
Is it intentional to use 0 (IRQ_TYPE_NONE) for the touchscreen interrupt trigger type here? This can cause the interrupt to be unconfigured or incorrectly configured by default, which may lead to missed touch events or an interrupt storm.[ ... ]
Quoted 8 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi line 146
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+&pcie {
arch/arm/boot/dts/nxp/imx/imx7d-var-som-mx7customboard.dtsi new file +3
-0+ pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 31 GPIO_ACTIVE_LOW>;[Severity: Low]
Could this use the standard reset-gpios property instead? The reset-gpio property is deprecated, anddtbs_checkvalidation may emit warnings for it.
Yes, please add reset-gpios under pci port (&pcie0_port0) for new dts.
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi new file +0
-0@@ -0,0 +1,64 @@[ ... ]
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi line 64
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2.dtsi new file +5
-0+/* WiFi */ +&usdhc2 { + mmc-pwrseq = <&wifi_pwrseq>; + /delete-node/ bcrmf@1; +};[Severity: Low]
Is there a typo in the node name here? The node defined in the base dtsi is wifi@1 (with the label brcmf). Trying to delete bcrmf@1 will cause the device tree compiler to fail since the node doesn't exist.
Now don't prefer delete-node.
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +0
-0@@ -0,0 +1,65 @@[ ... ]
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi line 63
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+&sai1 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +5
-0+ assigned-clock-rates = <0>, <36864000>; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>;[Severity: Low]
Does this node intend to duplicate the assigned-clock-rates property? The second definition (<0>, <12288000>) will silently overwrite the first one (<0>, <36864000>), which will cause DTC to emit a duplicate property warning and the intended 36.864MHz clock rate configuration to be lost.
Yes, please fix it.
Quoted 20 lines
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi new file +2
-0+ /delete-property/ fsl,sai-mclk-direction-output; +};arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +0
-0@@ -0,0 +1,633 @@[ ... ]
Quoted 11 lines
+&ecspi1 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +10
-0+ pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-1 = <&pinctrl_ecspi1_sleep>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + ads7846_ts: ads7846@0 { + reg = <0>; + compatible = "ti,ads7846";
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arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi line 108
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arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +4
-0+ pinctrl-names ="default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <9 0>;[Severity: Medium]
Is it intentional to use 0 (IRQ_TYPE_NONE) for this touch controller interrupt trigger type? This might result in the interrupt being unconfigured by default.
why type is NONE?
Frank
Quoted 45 lines
[ ... ]
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+&fec1 {
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +2
-0+ pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_rst>;[ ... ]
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arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +17
-0+ mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <80000>; + vddio-supply = <®_phy_vddio>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi line 169
Quoted 10 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som.dtsi new file +10
-0+ reset-assert-us = <20000>; + reset-deassert-us = <80000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_rst>;[Severity: High]
Does ethphy1 fail to reset during the MDIO bus probe on fec1?Since ethphy1 is a child of the fec1 MDIO bus, fec1 will attempt to toggle its reset GPIO (&gpio4 3) when it probes. However, the pinctrl for this GPIO (
&pinctrl_enet2_rst) is attached to fec2 instead of fec1. Since fec2 has not probed yet, the reset pin may not be muxed properly, preventing the reset toggle from reaching the PHY and causing detection to fail.--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
PATCH 3/3 ARM: dts: imx7d: add Variscite MX7CustomBoard support
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Add device tree support for the Variscite MX7CustomBoard carrier board with the VAR-SOM-MX7 system on module.
Add the supported board configurations for both VAR-SOM-MX7 hardware revisions, including eMMC, NAND and WM8731 variants.
Also add the resulting DTBs to the i.MX7D device tree Makefile.
--- arch/arm/boot/dts/nxp/imx/Makefile | 6 +++++ .../imx/imx7d-var-som-emmc-mx7customboard.dts | 22 ++++++++++++++++++ ...x7d-var-som-emmc-wm8731-mx7customboard.dts | 23 +++++++++++++++++++ .../imx/imx7d-var-som-nand-mx7customboard.dts | 22 ++++++++++++++++++ ...x7d-var-som-nand-wm8731-mx7customboard.dts | 23 +++++++++++++++++++ .../imx7d-var-som-v2-emmc-mx7customboard.dts | 23 +++++++++++++++++++ .../imx7d-var-som-v2-nand-mx7customboard.dts | 23 +++++++++++++++++++ 7 files changed, 142 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-wm8731-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-emmc-mx7customboard.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-nand-mx7customboard.dts
arch/arm/boot/dts/nxp/imx/Makefile +6 -0
@@ -444,6 +444,12 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ imx7d-smegw01.dtb \ + imx7d-var-som-emmc-mx7customboard.dtb \ + imx7d-var-som-emmc-wm8731-mx7customboard.dtb \ + imx7d-var-som-nand-mx7customboard.dtb \ + imx7d-var-som-nand-wm8731-mx7customboard.dtb \ + imx7d-var-som-v2-emmc-mx7customboard.dtb \ + imx7d-var-som-v2-nand-mx7customboard.dtb \ imx7d-zii-rmu2.dtb \ imx7d-zii-rpu2.dtb \ imx7s-colibri-aster.dtb \
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-mx7customboard.dts new file +22 -0
@@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * VAR-MX7CustomBoard for VAR-SOM-MX7 with eMMC + * + * Link: https://variscite.com/carrier-boards/var-mx7customboard/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx7d-var-som.dtsi" +#include "imx7d-var-som-emmc.dtsi" +#include "imx7d-var-som-mx7customboard.dtsi" + +/ { + model = "Variscite VAR-SOM-MX7 with eMMC on VAR-MX7CustomBoard"; + compatible = "variscite,var-som-imx7d-emmc-mx7customboard", + "variscite,var-som-imx7d", + "fsl,imx7d"; +};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts new file +23 -0
@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * VAR-MX7CustomBoard for VAR-SOM-MX7 with eMMC and WM8731 + * + * Link: https://variscite.com/carrier-boards/var-mx7customboard/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx7d-var-som.dtsi" +#include "imx7d-var-som-emmc.dtsi" +#include "imx7d-var-som-wm8731.dtsi" +#include "imx7d-var-som-mx7customboard.dtsi" + +/ { + model = "Variscite VAR-SOM-MX7 with eMMC & WM8731 on VAR-MX7CustomBoard"; + compatible = "variscite,var-som-imx7d-emmc-wm8731-mx7customboard", + "variscite,var-som-imx7d", + "fsl,imx7d"; +};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-mx7customboard.dts new file +22 -0
@@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * VAR-MX7CustomBoard for VAR-SOM-MX7 with NAND + * + * Link: https://variscite.com/carrier-boards/var-mx7customboard/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx7d-var-som.dtsi" +#include "imx7d-var-som-nand.dtsi" +#include "imx7d-var-som-mx7customboard.dtsi" + +/ { + model = "Variscite VAR-SOM-MX7 with NAND flash on VAR-MX7CustomBoard"; + compatible = "variscite,var-som-imx7d-nand-mx7customboard", + "variscite,var-som-imx7d", + "fsl,imx7d"; +};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-nand-wm8731-mx7customboard.dts new file +23 -0
@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * VAR-MX7CustomBoard for VAR-SOM-MX7 with NAND and WM8731 + * + * Link: https://variscite.com/carrier-boards/var-mx7customboard/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx7d-var-som.dtsi" +#include "imx7d-var-som-nand.dtsi" +#include "imx7d-var-som-wm8731.dtsi" +#include "imx7d-var-som-mx7customboard.dtsi" + +/ { + model = "Variscite VAR-SOM-MX7 with NAND flash & WM8731 on VAR-MX7CustomBoard"; + compatible = "variscite,var-som-imx7d-nand-wm8731-mx7customboard", + "variscite,var-som-imx7d", + "fsl,imx7d"; +};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-emmc-mx7customboard.dts new file +23 -0
@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * VAR-MX7CustomBoard for VAR-SOM-MX7 V2 with eMMC + * + * Link: https://variscite.com/carrier-boards/var-mx7customboard/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx7d-var-som.dtsi" +#include "imx7d-var-som-v2.dtsi" +#include "imx7d-var-som-emmc.dtsi" +#include "imx7d-var-som-mx7customboard.dtsi" + +/ { + model = "Variscite VAR-SOM-MX7_V2 with eMMC flash on VAR-MX7CustomBoard"; + compatible = "variscite,var-som-imx7d-v2-emmc-mx7customboard", + "variscite,var-som-imx7d-v2", + "fsl,imx7d"; +};
arch/arm/boot/dts/nxp/imx/imx7d-var-som-v2-nand-mx7customboard.dts new file +23 -0
@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * VAR-MX7CustomBoard for VAR-SOM-MX7 V2 with NAND + * + * Link: https://variscite.com/carrier-boards/var-mx7customboard/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx7d-var-som.dtsi" +#include "imx7d-var-som-v2.dtsi" +#include "imx7d-var-som-nand.dtsi" +#include "imx7d-var-som-mx7customboard.dtsi" + +/ { + model = "Variscite VAR-SOM-MX7_V2 with NAND flash on VAR-MX7CustomBoard"; + compatible = "variscite,var-som-imx7d-v2-nand-mx7customboard", + "variscite,var-som-imx7d-v2", + "fsl,imx7d"; +};
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v1 3/3] ARM: dts: imx7d: add Variscite MX7CustomBoard support
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [Medium] The V2 hardware revision variants with the WM8731 codec are missing, despite the commit message claiming to support them.
Pre-existing issues:
- [Medium] The assigned-clock-rates property is defined twice in the &sai1 node. --
--- Patch [3]: [PATCH v1 3/3] ARM: dts: imx7d: add Variscite MX7CustomBoard support --- commit 453bab576a5d3f561e4803a647eb9654e584d623
Author: Stefano Radaelli <[email protected]>
ARM: dts: imx7d: add Variscite MX7CustomBoard support
Add device tree support for the Variscite MX7CustomBoard carrier board with the VAR-SOM-MX7 system on module. This includes supported board configurations for both VAR-SOM-MX7 hardware revisions (eMMC, NAND, and WM8731 variants), and adds the resulting DTBs to the i.MX7D device tree Makefile.
Quoted 5 lines
arch/arm/boot/dts/nxp/imx/Makefile +0
-0
arch/arm/boot/dts/nxp/imx/Makefile dtb-$(CONFIG_SOC_IMX7D) += \ · line 452
Quoted 9 lines
arch/arm/boot/dts/nxp/imx/Makefile +6
-0@@ -444,6 +444,12 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ imx7d-smegw01.dtb \ + imx7d-var-som-emmc-mx7customboard.dtb \ + imx7d-var-som-emmc-wm8731-mx7customboard.dtb \ + imx7d-var-som-nand-mx7customboard.dtb \ + imx7d-var-som-nand-wm8731-mx7customboard.dtb \ + imx7d-var-som-v2-emmc-mx7customboard.dtb \ + imx7d-var-som-v2-nand-mx7customboard.dtb \
[Severity: Medium]
Are the V2 hardware revision variants with the WM8731 codec missing here?
The commit message states that configurations for both hardware revisions include the WM8731 variants, but it seems there are no dtb targets (nor source dts files) added for V2 with WM8731.
[ ... ]
Quoted 11 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts new file +5
-0@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * VAR-MX7CustomBoard for VAR-SOM-MX7 with eMMC and WM8731 + * + * Link: https://variscite.com/carrier-boards/var-mx7customboard/
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts line 15
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arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts new file +10
-0+ * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx7d-var-som.dtsi" +#include "imx7d-var-som-emmc.dtsi" +#include "imx7d-var-som-wm8731.dtsi"
[Severity: Medium]
This is a pre-existing issue, but does the included imx7d-var-som-wm8731.dtsi file define the assigned-clock-rates property twice?
Looking at &sai1 in arch/arm/boot/dts/nxp/imx/imx7d-var-som-wm8731.dtsi:
&sai1 {
assigned-clock-rates = <0>, <36864000>;
assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
<&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <12288000>;
/delete-property/ fsl,sai-mclk-direction-output;
};The assigned-clock-rates property is defined twice, which causes a device tree compiler warning and ambiguity about which clock rates are intended.
Could this lead to incorrect clock configuration and non-working audio when this file is included?
Quoted 8 lines
arch/arm/boot/dts/nxp/imx/imx7d-var-som-emmc-wm8731-mx7customboard.dts new file +8
-0+#include "imx7d-var-som-mx7customboard.dtsi" + +/ { + model = "Variscite VAR-SOM-MX7 with eMMC & WM8731 on VAR-MX7CustomBoard"; + compatible = "variscite,var-som-imx7d-emmc-wm8731-mx7customboard", + "variscite,var-som-imx7d", + "fsl,imx7d"; +};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3