riscv: sophgo: add clock support for sg2042

PATCH Superseded Chen Wang 3 participants 10 messages Feb 2, 2024 – Feb 12, 2024

Subsystems (4)

Device tree bindings Common clk RISC-V Sophgo devicetrees and drivers

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Chen Wang

author

2024-02-02 06:39 UTC #0 lore raw

v9 cover riscv: sophgo: add clock support for sg2042

From: Chen Wang <[email protected]>

This series adds clock controller support for sophgo sg2042.

Thanks,
Chen

---

Changes in v9:
The patch series is based on v6.8-rc2.

From this version, drop the system-controller node due to there is no actual device corresponding to it in IC design. SYS_CTRL is just a registers segment defined on TRM for misc functions. Now three clock-controllers are defined for SG2042, the control registers of the three clock-controllers are scattered in different memory address spaces:
- the first one is for pll clocks;
- the second one is for gate clocks for RP subsystem;
- the third one is for div/mux, and gate clocks working for other subsystem than RP subsystem.

Changes in v8:
The patch series is based on v6.7. You can simply review or test the patches at the link [9].

In this version, the main change is to split one clock provider into two. Strictly follow the hardware instructions, in the memoymap, the control registers of some clocks are defined in the SYS_CTRL segment, and the control registers of other clocks are defined in the CLOCK segment. Therefore, the new design defines two clock controllers, one as a child node of the system control and the other as an independent clock controller node.

This modification involves a major modification to the binding files, so the reviewed-by tags has been deleted.

Changes in v7:
The patch series is based on v6.7. You can simply review or test the patches at the link [8].
- fixed initval issue.
- fixed pll clk crash issue.
- fixed warning reported by <[email protected]>
- code optimization as per review comments.
- code cleanup and style improvements as per review comments and checkpatch

    with "--strict"

Changes in v6:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [7].
- fixed some warnings/errors reported by kernel test robot <[email protected]>.

Changes in v5:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [6].
- dt-bindings: improved yaml, such as:
- add vendor prefix for system-ctrl property for clock generator.
- Add explanation for system-ctrl property.
- move sophgo,sg2042-clkgen.yaml to directly under clock folder.
- fixed bugs for driver Makefile/Kconfig
- continue cleaning-up debug print for driver code.

Changes in v4:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [5].
- dt-bindings: fixed a dt_binding_check error.

Changes in v3:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [3].
- DTS: don't use syscon but define sg2042 specific system control node. More background info can read [4].
- Updating minor issues in dt-bindings as per input from reviews.

Changes in v2:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [2].
- Squashed the patch adding clock definitions with the patch adding the binding for the clock controller.
- Updating dt-binding for syscon, remove oneOf for property compatible; define clock controller as child of syscon.
- DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency property of osc to board devicethree due to the oscillator is outside the SoC.
- Fixed some bugs in driver code during testing, including removing warnings for rv32_defconfig.
- Updated MAINTAINERS info.

Changes in v1:
The patch series is based on v6.7-rc1. You can simply review or test the patches at the link [1].

Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here

Link https://lore.kernel.org/linux-riscv/[email protected]/ [2] open here

Link https://lore.kernel.org/linux-riscv/[email protected]/ [3] open here

Link https://lore.kernel.org/linux-riscv/MA0P287MB03329AE180378E1A2E034374FE82A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/ [4] open here

Link https://lore.kernel.org/linux-riscv/[email protected]/ [5] open here

Link https://lore.kernel.org/linux-riscv/[email protected]/ [6] open here

Link https://lore.kernel.org/linux-riscv/[email protected]/ [7] open here

Link https://lore.kernel.org/linux-riscv/[email protected]/ [8] open here

Link https://lore.kernel.org/linux-riscv/[email protected]/ [9] open here

---

Chen Wang (5):
dt-bindings: clock: sophgo: add pll clocks for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add clkgen for SG2042
clk: sophgo: Add SG2042 clock driver
riscv: dts: add clock generator for Sophgo SG2042 SoC

 .../bindings/clock/sophgo,sg2042-clkgen.yaml  |   37 +
 .../bindings/clock/sophgo,sg2042-pll.yaml     |   45 +
 .../bindings/clock/sophgo,sg2042-rpgate.yaml  |   37 +
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   12 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |   41 +
 drivers/clk/Kconfig                           |    1 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/sophgo/Kconfig                    |    8 +
 drivers/clk/sophgo/Makefile                   |    2 +
 drivers/clk/sophgo/clk-sophgo-sg2042.c        | 1401 +++++++++++++++++
 drivers/clk/sophgo/clk-sophgo-sg2042.h        |  233 +++
 .../dt-bindings/clock/sophgo,sg2042-clkgen.h  |  111 ++
 include/dt-bindings/clock/sophgo,sg2042-pll.h |   14 +
 .../dt-bindings/clock/sophgo,sg2042-rpgate.h  |   58 +
 14 files changed, 2001 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h

base-commit: 41bccc98fb7931d63d03f326a746ac4d429c1dd3

Signature · 1 line

2.25.1

Chen Wang

author

2024-02-02 06:41 UTC #1 lore raw

PATCH v9 1/5 dt-bindings: clock: sophgo: add pll clocks for SG2042

From: Chen Wang <[email protected]>

Add bindings for the pll clocks for Sophgo SG2042.

Signed-off-by Chen Wang <[email protected]>

---
 .../bindings/clock/sophgo,sg2042-pll.yaml     | 45 +++++++++++++++++++
 include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++
 2 files changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h

Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml new file +45 -0

new file mode 100644
index 000000000000..b9af733e8a73
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PLL Clock Generator
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-pll
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
+      - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
+      - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@10000000 {
+      compatible = "sophgo,sg2042-pll";
+      reg = <0x10000000 0x10000>;
+      clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
+      #clock-cells = <1>;
+    };

include/dt-bindings/clock/sophgo,sg2042-pll.h new file +14 -0

new file mode 100644
index 000000000000..2d519b3bf51c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+
+#define MPLL_CLK			0
+#define FPLL_CLK			1
+#define DPLL0_CLK			2
+#define DPLL1_CLK			3
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */

Signature · 1 line

2.25.1

Rob Herring

maintainer Reviewed-by on v9 1/5

2024-02-05 17:22 UTC #2 lore raw

Re: [PATCH v9 1/5] dt-bindings: clock: sophgo: add pll clocks for SG2042

Quoted 4 lines · Chen Wang

From: Chen Wang <[email protected]>
Add bindings for the pll clocks for Sophgo SG2042.

Quoted 8 lines

Signed-off-by Chen Wang <[email protected]>

---
 .../bindings/clock/sophgo,sg2042-pll.yaml     | 45 +++++++++++++++++++
 include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 ++++++
 2 files changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h

Reviewed-by Rob Herring <[email protected]>

Chen Wang

author

2024-02-02 06:42 UTC #3 lore raw

PATCH v9 2/5 dt-bindings: clock: sophgo: add RP gate clocks for SG2042

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.

Signed-off-by Chen Wang <[email protected]>

---
 .../bindings/clock/sophgo,sg2042-rpgate.yaml  | 37 ++++++++++++
 .../dt-bindings/clock/sophgo,sg2042-rpgate.h  | 58 +++++++++++++++++++
 2 files changed, 95 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +37 -0

new file mode 100644
index 000000000000..69ce3a64f66c
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-rpgate
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@10000000 {
+      compatible = "sophgo,sg2042-rpgate";
+      reg = <0x10000000 0x10000>;
+      #clock-cells = <1>;
+    };

include/dt-bindings/clock/sophgo,sg2042-rpgate.h new file +58 -0

58 lines not on this page · raw message

Signature · 1 line

2.25.1

Rob Herring

maintainer

2024-02-05 17:24 UTC #4 lore raw

Re: [PATCH v9 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042

Quoted 44 lines · Chen Wang

From: Chen Wang <[email protected]>

Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.

Signed-off-by Chen Wang <[email protected]>

---
 .../bindings/clock/sophgo,sg2042-rpgate.yaml  | 37 ++++++++++++
 .../dt-bindings/clock/sophgo,sg2042-rpgate.h  | 58 +++++++++++++++++++
 2 files changed, 95 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +26 -0

new file mode 100644
index 000000000000..69ce3a64f66c
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-rpgate
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
+
+required:
+  - compatible
+  - reg

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml line 36

Quoted 10 lines

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +10 -0

+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@10000000 {
+      compatible = "sophgo,sg2042-rpgate";
+      reg = <0x10000000 0x10000>;
+      #clock-cells = <1>;

No input clocks?

Quoted 68 lines

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +1 -0

+    };

include/dt-bindings/clock/sophgo,sg2042-rpgate.h new file +58 -0

new file mode 100644
index 000000000000..8b4522d5f559
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+
+#define GATE_CLK_RXU0			0
+#define GATE_CLK_RXU1			1
+#define GATE_CLK_RXU2			2
+#define GATE_CLK_RXU3			3
+#define GATE_CLK_RXU4			4
+#define GATE_CLK_RXU5			5
+#define GATE_CLK_RXU6			6
+#define GATE_CLK_RXU7			7
+#define GATE_CLK_RXU8			8
+#define GATE_CLK_RXU9			9
+#define GATE_CLK_RXU10			10
+#define GATE_CLK_RXU11			11
+#define GATE_CLK_RXU12			12
+#define GATE_CLK_RXU13			13
+#define GATE_CLK_RXU14			14
+#define GATE_CLK_RXU15			15
+#define GATE_CLK_RXU16			16
+#define GATE_CLK_RXU17			17
+#define GATE_CLK_RXU18			18
+#define GATE_CLK_RXU19			19
+#define GATE_CLK_RXU20			20
+#define GATE_CLK_RXU21			21
+#define GATE_CLK_RXU22			22
+#define GATE_CLK_RXU23			23
+#define GATE_CLK_RXU24			24
+#define GATE_CLK_RXU25			25
+#define GATE_CLK_RXU26			26
+#define GATE_CLK_RXU27			27
+#define GATE_CLK_RXU28			28
+#define GATE_CLK_RXU29			29
+#define GATE_CLK_RXU30			30
+#define GATE_CLK_RXU31			31
+#define GATE_CLK_MP0			32
+#define GATE_CLK_MP1			33
+#define GATE_CLK_MP2			34
+#define GATE_CLK_MP3			35
+#define GATE_CLK_MP4			36
+#define GATE_CLK_MP5			37
+#define GATE_CLK_MP6			38
+#define GATE_CLK_MP7			39
+#define GATE_CLK_MP8			40
+#define GATE_CLK_MP9			41
+#define GATE_CLK_MP10			42
+#define GATE_CLK_MP11			43
+#define GATE_CLK_MP12			44
+#define GATE_CLK_MP13			45
+#define GATE_CLK_MP14			46
+#define GATE_CLK_MP15			47
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ */

Signature · 1 line

2.25.1

Chen Wang

2024-02-06 12:57 UTC #5 lore raw

Re: [PATCH v9 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042

Quoted 48 lines · Rob Herring

Quoted 47 lines · Chen Wang

From: Chen Wang <[email protected]>

Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.

Signed-off-by Chen Wang <[email protected]>

---
  .../bindings/clock/sophgo,sg2042-rpgate.yaml  | 37 ++++++++++++
  .../dt-bindings/clock/sophgo,sg2042-rpgate.h  | 58 +++++++++++++++++++
  2 files changed, 95 insertions(+)

create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +29 -0

new file mode 100644
index 000000000000..69ce3a64f66c
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-rpgate
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false

Quoted 8 lines

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml line 36
Quoted 7 lines
Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +7 -0
+
+examples:
+  - |
+    clock-controller@10000000 {
+      compatible = "sophgo,sg2042-rpgate";
+      reg = <0x10000000 0x10000>;
+      #clock-cells = <1>;
No input clocks?

I think it should have some input, I will add it, thanks.

BTW, can we ignore this property if driver doesn't use it？ In other words, do we have to add this clocks property just to indicate that this node requires some clocks as input from a hardware perspective?

Quoted 69 lines

Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +1 -0

+    };

include/dt-bindings/clock/sophgo,sg2042-rpgate.h new file +58 -0

new file mode 100644
index 000000000000..8b4522d5f559
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+
+#define GATE_CLK_RXU0			0
+#define GATE_CLK_RXU1			1
+#define GATE_CLK_RXU2			2
+#define GATE_CLK_RXU3			3
+#define GATE_CLK_RXU4			4
+#define GATE_CLK_RXU5			5
+#define GATE_CLK_RXU6			6
+#define GATE_CLK_RXU7			7
+#define GATE_CLK_RXU8			8
+#define GATE_CLK_RXU9			9
+#define GATE_CLK_RXU10			10
+#define GATE_CLK_RXU11			11
+#define GATE_CLK_RXU12			12
+#define GATE_CLK_RXU13			13
+#define GATE_CLK_RXU14			14
+#define GATE_CLK_RXU15			15
+#define GATE_CLK_RXU16			16
+#define GATE_CLK_RXU17			17
+#define GATE_CLK_RXU18			18
+#define GATE_CLK_RXU19			19
+#define GATE_CLK_RXU20			20
+#define GATE_CLK_RXU21			21
+#define GATE_CLK_RXU22			22
+#define GATE_CLK_RXU23			23
+#define GATE_CLK_RXU24			24
+#define GATE_CLK_RXU25			25
+#define GATE_CLK_RXU26			26
+#define GATE_CLK_RXU27			27
+#define GATE_CLK_RXU28			28
+#define GATE_CLK_RXU29			29
+#define GATE_CLK_RXU30			30
+#define GATE_CLK_RXU31			31
+#define GATE_CLK_MP0			32
+#define GATE_CLK_MP1			33
+#define GATE_CLK_MP2			34
+#define GATE_CLK_MP3			35
+#define GATE_CLK_MP4			36
+#define GATE_CLK_MP5			37
+#define GATE_CLK_MP6			38
+#define GATE_CLK_MP7			39
+#define GATE_CLK_MP8			40
+#define GATE_CLK_MP9			41
+#define GATE_CLK_MP10			42
+#define GATE_CLK_MP11			43
+#define GATE_CLK_MP12			44
+#define GATE_CLK_MP13			45
+#define GATE_CLK_MP14			46
+#define GATE_CLK_MP15			47
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ */

Signature · 1 line

2.25.1

Rob Herring

maintainer

2024-02-12 15:14 UTC #6 lore raw

Re: [PATCH v9 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042

Quoted 59 lines · Chen Wang

Quoted 48 lines · Rob Herring
Quoted 47 lines · Chen Wang
From: Chen Wang <[email protected]>
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
Signed-off-by Chen Wang <[email protected]>
---
  .../bindings/clock/sophgo,sg2042-rpgate.yaml  | 37 ++++++++++++
  .../dt-bindings/clock/sophgo,sg2042-rpgate.h  | 58 +++++++++++++++++++
  2 files changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +29 -0
new file mode 100644
index 000000000000..69ce3a64f66c
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-rpgate
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
Quoted 8 lines
Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml line 36
Quoted 7 lines
Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml new file +7 -0
+
+examples:
+  - |
+    clock-controller@10000000 {
+      compatible = "sophgo,sg2042-rpgate";
+      reg = <0x10000000 0x10000>;
+      #clock-cells = <1>;
No input clocks?

Quoted 5 lines

I think it should have some input, I will add it, thanks.
BTW, can we ignore this property if driver doesn't use it？ In other words, do we have to add this clocks property just to indicate that this node requires some clocks as input from a hardware perspective?

Yes and no. The kernel will see the dependency and track that. But your driver doesn't have to get the clock or anything. Though presumably the source is a fixed-clock and you need its frequency to calculate child clock rates.

Rob

Chen Wang

author

2024-02-02 06:42 UTC #7 lore raw

PATCH v9 3/5 dt-bindings: clock: sophgo: add clkgen for SG2042

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add bindings for the clock generator of divider/mux and gates working for other subsystem than RP subsystem for Sophgo SG2042.

Signed-off-by Chen Wang <[email protected]>

---
 .../bindings/clock/sophgo,sg2042-clkgen.yaml  |  37 ++++++
 .../dt-bindings/clock/sophgo,sg2042-clkgen.h  | 111 ++++++++++++++++++
 2 files changed, 148 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
 create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h

Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml new file +37 -0

new file mode 100644
index 000000000000..5c33eb20c76e
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Clock Generator for divider/mux/gate
+
+maintainers:
+  - Chen Wang <[email protected]>
+
+properties:
+  compatible:
+    const: sophgo,sg2042-clkgen
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@30012000 {
+      compatible = "sophgo,sg2042-clkgen";
+      reg = <0x30012000 0x1000>;
+      #clock-cells = <1>;
+    };

include/dt-bindings/clock/sophgo,sg2042-clkgen.h new file +111 -0

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Signature · 1 line

2.25.1

Chen Wang

author

2024-02-02 06:42 UTC #8 lore raw

PATCH v9 4/5 clk: sophgo: Add SG2042 clock driver

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add a driver for the SOPHGO SG2042 clocks.

Signed-off-by Chen Wang <[email protected]>

---
 drivers/clk/Kconfig                    |    1 +
 drivers/clk/Makefile                   |    1 +
 drivers/clk/sophgo/Kconfig             |    8 +
 drivers/clk/sophgo/Makefile            |    2 +
 drivers/clk/sophgo/clk-sophgo-sg2042.c | 1401 ++++++++++++++++++++++++
 drivers/clk/sophgo/clk-sophgo-sg2042.h |  233 ++++
 6 files changed, 1646 insertions(+)
 create mode 100644 drivers/clk/sophgo/Kconfig
 create mode 100644 drivers/clk/sophgo/Makefile
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.c
 create mode 100644 drivers/clk/sophgo/clk-sophgo-sg2042.h

drivers/clk/Kconfig +1 -0

index 50af5fc7f570..bc28502ec3c9 100644
@@ -489,6 +489,7 @@ source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
 source "drivers/clk/sifive/Kconfig"
 source "drivers/clk/socfpga/Kconfig"
+source "drivers/clk/sophgo/Kconfig"
 source "drivers/clk/sprd/Kconfig"
 source "drivers/clk/starfive/Kconfig"
 source "drivers/clk/sunxi/Kconfig"

drivers/clk/Makefile +1 -0

index 14fa8d4ecc1f..4abe16c8ccdf 100644
@@ -118,6 +118,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_CLK_SIFIVE)		+= sifive/
 obj-y					+= socfpga/
+obj-y					+= sophgo/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/
 obj-y					+= sprd/
 obj-$(CONFIG_ARCH_STI)			+= st/

drivers/clk/sophgo/Kconfig new file +8 -0

new file mode 100644
index 000000000000..feab0b805a29
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_SOPHGO_SG2042
+	bool "Sophgo SG2042 clock support"
+	depends on ARCH_SOPHGO || COMPILE_TEST
+	default y
+	help
+	  Say yes here to support the clock controller on the Sophgo SG2042 SoC.

drivers/clk/sophgo/Makefile new file +2 -0

new file mode 100644
index 000000000000..13834cce260c
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_SOPHGO_SG2042)	+= clk-sophgo-sg2042.o

drivers/clk/sophgo/clk-sophgo-sg2042.c new file +1401 -0

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drivers/clk/sophgo/clk-sophgo-sg2042.h new file +233 -0

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Signature · 1 line

2.25.1

Chen Wang

author

2024-02-02 06:43 UTC #9 lore raw

PATCH v9 5/5 riscv: dts: add clock generator for Sophgo SG2042 SoC

In reply to Chen Wang

From: Chen Wang <[email protected]>

Add clock generator node to device tree for SG2042, and enable clock for uart.

Signed-off-by Chen Wang <[email protected]>

---
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 12 ++++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        | 41 +++++++++++++++++++
 2 files changed, 53 insertions(+)

arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +12 -0

index 49b4b9c2c101..80cb017974d8 100644
@@ -14,6 +14,18 @@ chosen {
 	};
 };
 
+&cgi_main {
+	clock-frequency = <25000000>;
+};
+
+&cgi_dpll0 {
+	clock-frequency = <25000000>;
+};
+
+&cgi_dpll1 {
+	clock-frequency = <25000000>;
+};
+
 &uart0 {
 	status = "okay";
 };

arch/riscv/boot/dts/sophgo/sg2042.dtsi +41 -0

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Signature · 1 line

2.25.1